Printed Exception strings - what do all
|
|
- Trevor Wiggins
- 8 years ago
- Views:
Transcription
1 Printed Exception strings - what do all those flags mean? Data Abort: Thread=9352cc9c Proc=90876ea0 'shell32.exe' AKY= PC=03f74680(coredll.dll+0x ) RA= (aygshell.dll+0x ) BVA=060000e0 FSR= AKY "Access Key" Process slot bitmask corresponding to the processes the excepting thread has access to. For example, the above exception is 0x , which corresponds to: (Hint: the following was copied from Platform Builder window: View Debug Windows Processes) Name VMBase AccessKey TrustLevel hprocess btstereoappui.exe 0x1A x Full 0xB30E2766 connmgr.exe 0x x Full 0x E cprog.exe 0x1C x Full 0xF device.exe 0x0A x Full 0xB3CEC78E filesys.exe 0x x Full 0x13EEE762 gwes.exe 0x0C x Full 0x737A498A nk.exe 0xC x Full 0x13EFF002 pmsnserver.exe 0x x Full 0x5333CD86 poutlook.exe 0x x Full 0xD308FA02 sddaemon.exe 0x x Full 0x7314C62A services.exe 0x0E x Full 0x7352CFAA shell.exe 0x x Full 0xD3CD7A82 shell32.exe 0x x Full 0xD352CEDE srvtrust.exe 0x x Full 0x33105BCA PC "Program Counter" Represents the current line of instruction. On ARM platforms, this is the current value of the PC register and EIP (Instruction Pointer) on x86 platforms. If symbols are available, the exception handler will attempt to provide an offset line into the DLL that caused the exception. In the
2 example above we can find the (fixed up, closest instruction but not over) instruction offset 0x14680 in the coredll.map for the offending instruction. In this case: (Hint: the following was copied and pasted from the coredll.map text file found in the image release directory.) 0001: GetWindowLongW f coredll_all:twinuser.obj 0001: BeginPaint f coredll_all:twinuser.obj 0001:000136cc EndPaint cc f coredll_all:twinuser.obj 0001: GetDC f coredll_all:twinuser.obj 0001:000137d4 ReleaseDC d4 f coredll_all:twinuser.obj 0001: GetParent f coredll_all:twinuser.obj Subtract the function base address above from the remainder reported in the exception handler to find the exact instruction that caused the exception. RA "Return Address" Pointer to the instruction address of the function that called the current function. Had the current function NOT caused an exception, this is where we would return to. The same symbol logic used to resolve function addresses in PC can be used to resolve RA. ARM platforms store this value in LR register and since our example above has a RA= 0x It should have jumped here: (Hint: the following disassembler output was copied and pasted from the Platform Builder disassembly window found either by right-clicking on the current source file or Window Disassembly.) FC add r1, sp, #0x bl BeginPaint (0325aee0) < Exception caused in here ldr lr, [sp, #0x44] < Would have returned here ldr r3, [sp, #0x38] C ldr r2, [sp, #0x3C] ARM, like most platforms manages function Return Addresses on the local stack which allows for nested functions and recursion. Unfortunately this can also lead to problems if the stack somehow gets corrupted not only do you lose the values stored in the stack, but you are at
3 risk of losing your place and the processor won t know where to resume execution. A good indicator this has happened is when your PC == LR.
4 BVA "Base Virtual Address" The contents of BVA depend on the type of exception found. If the exception is a Prefetch Abort, the value points directly to the PC register (execution point). If the exception is a Data Abort, then this value points to why the exception was caused. It is a combination of the Virtual Memory base of the module found plus the value that caused the exception. This is easiest to explain through some examples, starting with our original exception BVA=060000e0 which represents: Processes: (Hint: the following was copied from Platform Builder window: View Debug Windows Processes) Name VMBase AccessKey TrustLevel hprocess shell.exe 0x x Full 0xD3CD7A82 shell32.exe 0x x Full 0xD352CEDE srvtrust.exe 0x x Full 0x33105BCA Registers: (Hint: the following was copied from Platform Builder window: View Debug Windows Registers) R2 = F R3 = R4 = F Disassembly: (Hint: the following disassembler output was copied and pasted from the Platform Builder disassembly window found either by right-clicking on the current source file or Window Disassembly.) 03F7467C ldr r3, [r3] 03F74680 ldr r3, [r3, #0xE0] <<< Exception here, invalid pointer. 03F74684 mov lr, pc 03F74688 bx r3 This line of execution is trying to store the contents of Register 3 into the memory address located at Register 3 + 0xE0 in the context of Shell32.exe (invalid in this case): R3 + 0xE0 + VMBase(shell32.exe) == 0x060000E0
5 An additional BVA example in ossvcs.dll: (Hint: the following was copied from Platform Builder Output window) Data Abort: Thread=92f44574 Proc=90876ea0 'shell32.exe' AKY=ffffffff PC=02e320c8(ossvcs.dll+0x000320c8) RA=02e0f524(ossvcs.dll+0x0000f524) BVA=07ece200 FSR= Registers: (Hint: the following was copied from Platform Builder window: View Debug Windows Registers) R8 = R9 = R10 = 01F31AD0 R11 = 1C05E918 R12 = 01ECE200 Sp = 1C05E500 Lr = 02E0F524 Pc = 02E320C8 Disassembly: (Hint: the following disassembler output was copied and pasted from the Platform Builder disassembly window found either by right-clicking on the current source file or Window Disassembly.) CeGetCurrentTrust: 02E320C4 ldr r12, [pc, #4] 02E320C8 ldr r12, [r12] <<< Exception here, invalid pointer. 02E320CC bx r12 02E320D0??? The line of execution is trying to store Register 12 at the value pointed at in Register 12 in the context of Shell32 (which happens to be invalid). R12 + VMBase(shell32.exe) == 0x07ece200
6 FSR "Fault Status Register" The FSR represents several flags that will help you understand the nature of your exception. For ARM devices the following flags can be set: #define FSR_ALIGNMENT #define FSR_PAGE_ERROR #define FSR_TRANSLATION #define FSR_DOMAIN_ERROR #define FSR_PERMISSION 0x01 0x02 0x05 0x09 0x0D So, taking our example above, we have: FSR= == FSR_PAGE_ERROR FSR_TRANSLATION
Slaying the Virtual Memory Monster - Part II
1 of 8 04/19/2012 07:53 PM Slaying the Virtual Memory Monster - Part II Reed Robison 1 Oct 2007 4:46 PM 17 Someday I ll learn to write a simple blog post a couple of paragraphs about something cool and
More informationException and Interrupt Handling in ARM
Exception and Interrupt Handling in ARM Architectures and Design Methods for Embedded Systems Summer Semester 2006 Author: Ahmed Fathy Mohammed Abdelrazek Advisor: Dominik Lücke Abstract We discuss exceptions
More informationPSM/SAK Event Log Error Codes
PSM Error Codes PSM/SAK Event Log Error Codes If you experience a problem using Persistent Storage Manager, the following list of event log messages can be used to troubleshoot. Error codes are logged
More informationFaculty of Engineering Student Number:
Philadelphia University Student Name: Faculty of Engineering Student Number: Dept. of Computer Engineering Final Exam, First Semester: 2012/2013 Course Title: Microprocessors Date: 17/01//2013 Course No:
More informationHelping you avoid stack overflow crashes!
Helping you avoid stack overflow crashes! One of the toughest (and unfortunately common) problems in embedded systems is stack overflows and the collateral corruption that it can cause. As a result, we
More informationAn Introduction to Assembly Programming with the ARM 32-bit Processor Family
An Introduction to Assembly Programming with the ARM 32-bit Processor Family G. Agosta Politecnico di Milano December 3, 2011 Contents 1 Introduction 1 1.1 Prerequisites............................. 2
More informationReturn-oriented programming without returns
Faculty of Computer Science Institute for System Architecture, Operating Systems Group Return-oriented programming without urns S. Checkoway, L. Davi, A. Dmitrienko, A. Sadeghi, H. Shacham, M. Winandy
More informationTHUMB Instruction Set
5 THUMB Instruction Set This chapter describes the THUMB instruction set. Format Summary 5-2 Opcode Summary 5-3 5. Format : move shifted register 5-5 5.2 Format 2: add/subtract 5-7 5.3 Format 3: move/compare/add/subtract
More informationInterrupt handling. Andrew N. Sloss (asloss@arm.com)
Interrupt handling Andrew N. Sloss (asloss@arm.com) April 25th, 2001 CHAPTER 1 Interrupt handling Handling interrupts is at the heart of an embedded system. By managing the interaction with external systems
More informationChapter 7D The Java Virtual Machine
This sub chapter discusses another architecture, that of the JVM (Java Virtual Machine). In general, a VM (Virtual Machine) is a hypothetical machine (implemented in either hardware or software) that directly
More informationCHAPTER 6 TASK MANAGEMENT
CHAPTER 6 TASK MANAGEMENT This chapter describes the IA-32 architecture s task management facilities. These facilities are only available when the processor is running in protected mode. 6.1. TASK MANAGEMENT
More informationM A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 1. Introduction 6.004 Computation Structures β Documentation This handout is
More information10 STEPS TO YOUR FIRST QNX PROGRAM. QUICKSTART GUIDE Second Edition
10 STEPS TO YOUR FIRST QNX PROGRAM QUICKSTART GUIDE Second Edition QNX QUICKSTART GUIDE A guide to help you install and configure the QNX Momentics tools and the QNX Neutrino operating system, so you can
More informationApplication Note 195. ARM11 performance monitor unit. Document number: ARM DAI 195B Issued: 15th February, 2008 Copyright ARM Limited 2007
Application Note 195 ARM11 performance monitor unit Document number: ARM DAI 195B Issued: 15th February, 2008 Copyright ARM Limited 2007 Copyright 2007 ARM Limited. All rights reserved. Application Note
More informationiphone Exploitation One ROPe to bind them all?
http://www.sektioneins.de iphone Exploitation One ROPe to bind them all? Stefan Esser Who am I? Stefan Esser from Cologne / Germany in information security since 1998 PHP
More informationCSE 141L Computer Architecture Lab Fall 2003. Lecture 2
CSE 141L Computer Architecture Lab Fall 2003 Lecture 2 Pramod V. Argade CSE141L: Computer Architecture Lab Instructor: TA: Readers: Pramod V. Argade (p2argade@cs.ucsd.edu) Office Hour: Tue./Thu. 9:30-10:30
More informationDongwoo Kim : Hyeon-jeong Lee s Husband
2/ 32 Who we are Dongwoo Kim : Hyeon-jeong Lee s Husband Ph.D. Candidate at Chungnam National University in South Korea Majoring in Computer Communications & Security Interested in mobile hacking, digital
More informationOff-by-One exploitation tutorial
Off-by-One exploitation tutorial By Saif El-Sherei www.elsherei.com Introduction: I decided to get a bit more into Linux exploitation, so I thought it would be nice if I document this as a good friend
More informationThe ARM Architecture. With a focus on v7a and Cortex-A8
The ARM Architecture With a focus on v7a and Cortex-A8 1 Agenda Introduction to ARM Ltd ARM Processors Overview ARM v7a Architecture/Programmers Model Cortex-A8 Memory Management Cortex-A8 Pipeline 2 ARM
More informationThe stack and the stack pointer
The stack and the stack pointer If you google the word stack, one of the definitions you will get is: A reserved area of memory used to keep track of a program's internal operations, including functions,
More informationCS61: Systems Programing and Machine Organization
CS61: Systems Programing and Machine Organization Fall 2009 Section Notes for Week 2 (September 14 th - 18 th ) Topics to be covered: I. Binary Basics II. Signed Numbers III. Architecture Overview IV.
More informationHTC Windows Phone 7 Arbitrary Read/Write of Kernel Memory 10/11/2011
MWR InfoSecurity Advisory HTC Windows Phone 7 Arbitrary Read/Write of Kernel Memory 10/11/2011 Package Name Date 10/11/2011 Affected Versions HTC Windows Phone 7 Phones HTC HD7 confirmed to be vulnerable.
More informationOverview of the Cortex-M3
CHAPTER Overview of the Cortex-M3 2 In This Chapter Fundamentals 11 Registers 12 Operation Modes 14 The Built-In Nested Vectored Interrupt Controller 15 The Memory Map 16 The Bus Interface 17 The MPU 18
More informationQ N X S O F T W A R E D E V E L O P M E N T P L A T F O R M v 6. 4. 10 Steps to Developing a QNX Program Quickstart Guide
Q N X S O F T W A R E D E V E L O P M E N T P L A T F O R M v 6. 4 10 Steps to Developing a QNX Program Quickstart Guide 2008, QNX Software Systems GmbH & Co. KG. A Harman International Company. All rights
More informationEliminate Memory Errors and Improve Program Stability
Eliminate Memory Errors and Improve Program Stability with Intel Parallel Studio XE Can running one simple tool make a difference? Yes, in many cases. You can find errors that cause complex, intermittent
More informationForensic Analysis of Internet Explorer Activity Files
Forensic Analysis of Internet Explorer Activity Files by Keith J. Jones keith.jones@foundstone.com 3/19/03 Table of Contents 1. Introduction 4 2. The Index.dat File Header 6 3. The HASH Table 10 4. The
More informationUSB Card Reader Configuration Utility. User Manual. Draft!
USB Card Reader Configuration Utility User Manual Draft! SB Research 2009 The Configuration Utility for USB card reader family: Concept: To allow for field programming of the USB card readers a configuration
More informationApplication Note. Introduction AN2471/D 3/2003. PC Master Software Communication Protocol Specification
Application Note 3/2003 PC Master Software Communication Protocol Specification By Pavel Kania and Michal Hanak S 3 L Applications Engineerings MCSL Roznov pod Radhostem Introduction The purpose of this
More informationHacking Techniques & Intrusion Detection. Ali Al-Shemery arabnix [at] gmail
Hacking Techniques & Intrusion Detection Ali Al-Shemery arabnix [at] gmail All materials is licensed under a Creative Commons Share Alike license http://creativecommonsorg/licenses/by-sa/30/ # whoami Ali
More informationA Choices Hypervisor on the ARM architecture
A Choices Hypervisor on the ARM architecture Rishi Bhardwaj, Phillip Reames, Russell Greenspan Vijay Srinivas Nori, Ercan Ucan ABSTRACT Choices is an object oriented operating system that runs on the x86
More informationGraded ARM assembly language Examples
Graded ARM assembly language Examples These examples have been created to help students with the basics of Keil s ARM development system. I am providing a series of examples that demonstrate the ARM s
More informationSYMETRIX SOLUTIONS: TECH TIP August 2015
String Output Modules The purpose of this document is to provide an understanding of operation and configuration of the two different String Output modules available within SymNet Composer. The two different
More informationOPERATING SYSTEMS MEMORY MANAGEMENT
OPERATING SYSTEMS MEMORY MANAGEMENT Jerry Breecher 8: Memory Management 1 OPERATING SYSTEM Memory Management What Is In This Chapter? Just as processes share the CPU, they also share physical memory. This
More informationNemo 96HD/HD+ MODBUS
18/12/12 Pagina 1 di 28 MULTIFUNCTION FIRMWARE 2.30 Nemo 96HD/HD+ MODBUS COMMUNICATION PROTOCOL CONTENTS 1.0 ABSTRACT 2.0 DATA MESSAGE DESCRIPTION 2.1 Parameters description 2.2 Data format 2.3 Description
More informationHotpatching and the Rise of Third-Party Patches
Hotpatching and the Rise of Third-Party Patches Alexander Sotirov asotirov@determina.com BlackHat USA 2006 Overview In the next one hour, we will cover: Third-party security patches _ recent developments
More information3. USB FLASH DRIVE PREPARATION. Almost all current PC firmware permits booting from a USB drive, allowing the launch
3. USB FLASH DRIVE PREPARATION 3.1 INTRODUCTION Almost all current PC firmware permits booting from a USB drive, allowing the launch of an operating system from a bootable flash drive. Such a configuration
More informationPreface. DirX Document Set
Preface DirX Document Set Preface The DirX Troubleshooting Guide describes how to solve problems that can occur in DirX installations. The book is organized as follows: Chapter 1 provides a summary of
More informationApplication Note: AN00141 xcore-xa - Application Development
Application Note: AN00141 xcore-xa - Application Development This application note shows how to create a simple example which targets the XMOS xcore-xa device and demonstrates how to build and run this
More informationSoftware security. Buffer overflow attacks SQL injections. Lecture 11 EIT060 Computer Security
Software security Buffer overflow attacks SQL injections Lecture 11 EIT060 Computer Security Buffer overflow attacks Buffer overrun is another common term Definition A condition at an interface under which
More informationUnix Security Technologies. Pete Markowsky <peterm[at] ccs.neu.edu>
Unix Security Technologies Pete Markowsky What is this about? The goal of this CPU/SWS are: Introduce you to classic vulnerabilities Get you to understand security advisories Make
More informationErasure Codes Made So Simple, You ll Really Like Them
Erasure Codes Made So Simple, You ll Really Like Them W. David Schwaderer August 7, 214 schwaderer_1@comcast.net Santa Clara, CA 1 Agenda Errors Versus Erasures HDD Bit Error Rate Implications RAID 4,
More informationPROGRAMMING CONCEPTS AND EMBEDDED PROGRAMMING IN C, C++ and JAVA: Lesson-4: Data Structures: Stacks
PROGRAMMING CONCEPTS AND EMBEDDED PROGRAMMING IN C, C++ and JAVA: Lesson-4: Data Structures: Stacks 1 STACK A structure with a series of data elements with last sent element waiting for a delete operation.
More informationChapter 1. Bootstrap. Hardware
DRAFT as of September 23, 2010: Copyright 2009 Cox, Kaashoek, Morris Chapter 1 Bootstrap Hardware A computer s CPU (central processing unit, or processor) runs a conceptually simple loop: it inspects the
More informationNios II IDE Help System
Nios II IDE Help System 101 Innovation Drive San Jose, CA 95134 www.altera.com Nios II IDE Version: 9.0 Document Version: 1.7 Document Date: March 2009 UG-N2IDEHELP-1.7 Table Of Contents About This Document...1
More informationWe r e going to play Final (exam) Jeopardy! "Answers:" "Questions:" - 1 -
. (0 pts) We re going to play Final (exam) Jeopardy! Associate the following answers with the appropriate question. (You are given the "answers": Pick the "question" that goes best with each "answer".)
More informationComputer Organization and Architecture
Computer Organization and Architecture Chapter 11 Instruction Sets: Addressing Modes and Formats Instruction Set Design One goal of instruction set design is to minimize instruction length Another goal
More informationCS:APP Chapter 4 Computer Architecture Instruction Set Architecture. CS:APP2e
CS:APP Chapter 4 Computer Architecture Instruction Set Architecture CS:APP2e Instruction Set Architecture Assembly Language View Processor state Registers, memory, Instructions addl, pushl, ret, How instructions
More informationGPU Tools Sandra Wienke
Sandra Wienke Center for Computing and Communication, RWTH Aachen University MATSE HPC Battle 2012/13 Rechen- und Kommunikationszentrum (RZ) Agenda IDE Eclipse Debugging (CUDA) TotalView Profiling (CUDA
More informationModbus RTU Communications RX/WX and MRX/MWX
15 Modbus RTU Communications RX/WX and MRX/MWX In This Chapter.... Network Slave Operation Network Master Operation: RX / WX Network Master Operation: DL06 MRX / MWX 5 2 D0 Modbus Network Slave Operation
More informationGB ethernet UDP interface in FPGA
GB ethernet UDP interface in FPGA NIKHEF, PeterJ 05 August 2013 1 LED0 RxFifos 0 1 n Rx Stream Select Rx_buf2data pkt_buffers Rx Packet Buffer 64 KB Flags Rx_mac2buf Overview Good/Bad Frame Rx FPGA ML605
More informationCaml Virtual Machine File & data formats Document version: 1.4 http://cadmium.x9c.fr
Caml Virtual Machine File & data formats Document version: 1.4 http://cadmium.x9c.fr Copyright c 2007-2010 Xavier Clerc cadmium@x9c.fr Released under the LGPL version 3 February 6, 2010 Abstract: This
More information612 CHAPTER 11 PROCESSOR FAMILIES (Corrisponde al cap. 12 - Famiglie di processori) PROBLEMS
612 CHAPTER 11 PROCESSOR FAMILIES (Corrisponde al cap. 12 - Famiglie di processori) PROBLEMS 11.1 How is conditional execution of ARM instructions (see Part I of Chapter 3) related to predicated execution
More informationAltera Monitor Program
Altera Monitor Program This tutorial presents an introduction to the Altera Monitor Program, which can be used to compile, assemble, download and debug programs for Altera s Nios II processor. The tutorial
More informationCS412/CS413. Introduction to Compilers Tim Teitelbaum. Lecture 20: Stack Frames 7 March 08
CS412/CS413 Introduction to Compilers Tim Teitelbaum Lecture 20: Stack Frames 7 March 08 CS 412/413 Spring 2008 Introduction to Compilers 1 Where We Are Source code if (b == 0) a = b; Low-level IR code
More informationPaul Sabanal IBM X-Force Advanced Research. State Of The ART. Exploring The New Android KitKat Runtime. 2014 IBM Corporation
Paul Sabanal IBM X-Force Advanced Research State Of The ART Exploring The New Android KitKat Runtime Agenda Introduc)on Ahead of )me compila)on OAT file format Security implica)ons Reverse engineering
More informationStrongARM** SA-110 Microprocessor Instruction Timing
StrongARM** SA-110 Microprocessor Instruction Timing Application Note September 1998 Order Number: 278194-001 Information in this document is provided in connection with Intel products. No license, express
More informationHardware Assisted Virtualization
Hardware Assisted Virtualization G. Lettieri 21 Oct. 2015 1 Introduction In the hardware-assisted virtualization technique we try to execute the instructions of the target machine directly on the host
More informationLecture 7: Machine-Level Programming I: Basics Mohamed Zahran (aka Z) mzahran@cs.nyu.edu http://www.mzahran.com
CSCI-UA.0201-003 Computer Systems Organization Lecture 7: Machine-Level Programming I: Basics Mohamed Zahran (aka Z) mzahran@cs.nyu.edu http://www.mzahran.com Some slides adapted (and slightly modified)
More informationWIZnet S2E (Serial-to-Ethernet) Device s Configuration Tool Programming Guide
WIZnet S2E (Serial-to-Ethernet) Device s Configuration Tool Programming Guide Rev 0.2 This document describes how to make your own Configuration Tool for WIZ100SR, WIZ105SR and WIZ110SR of WIZnet. And
More information02 B The Java Virtual Machine
02 B The Java Virtual Machine CS1102S: Data Structures and Algorithms Martin Henz January 22, 2010 Generated on Friday 22 nd January, 2010, 09:46 CS1102S: Data Structures and Algorithms 02 B The Java Virtual
More informationAn Introduction to the ARM 7 Architecture
An Introduction to the ARM 7 Architecture Trevor Martin CEng, MIEE Technical Director This article gives an overview of the ARM 7 architecture and a description of its major features for a developer new
More informationNo. Time Source Destination Protocol Info 1 0.000000 192.168.1.28 192.168.1.2 DNS Standard query A weather.noaa.gov
/tmp/dump/dump02_arp_dns-weather_syn_fin complete-session - Ethereal Page 1 1 0.000000 192.168.1.28 192.168.1.2 DNS Standard query A weather.noaa.gov Frame 1 (76 bytes on wire, 76 bytes captured) Arrival
More informationMarshallSoft AES. (Advanced Encryption Standard) Reference Manual
MarshallSoft AES (Advanced Encryption Standard) Reference Manual (AES_REF) Version 3.0 May 6, 2015 This software is provided as-is. There are no warranties, expressed or implied. Copyright (C) 2015 All
More informationWhere s the FEEB? The Effectiveness of Instruction Set Randomization
Where s the FEEB? The Effectiveness of Instruction Set Randomization Ana Nora Sovarel David Evans Nathanael Paul University of Virginia, Department of Computer Science http://www.cs.virginia.edu/feeb Abstract
More informationHow To Understand How A Process Works In Unix (Shell) (Shell Shell) (Program) (Unix) (For A Non-Program) And (Shell).Orgode) (Powerpoint) (Permanent) (Processes
Content Introduction and History File I/O The File System Shell Programming Standard Unix Files and Configuration Processes Programs are instruction sets stored on a permanent medium (e.g. harddisc). Processes
More informationTowards A Unified Hardware Abstraction Layer Architecture for Embedded Systems
Towards A Unified Hardware Abstraction Layer Architecture for Embedded Systems Hao Peng 1,2 hao.peng@uci.edu R. Dömer 1 doemer@uci.edu CECS Technical Report 12 14 Nov. 26, 2012 1 Center for Embedded Computer
More informationCMUX User Guide 30268ST10299A Rev. 3 19/01/09
This document is referred to the following products: APPLICABILITY TABLE PRODUCT PART NUMBER (1) GT864-QUAD 4990150069 GT864-PY 4990150070 GM862-GPS GM862-QUAD-PY GM862-QUAD GC864-QUAD GC864-PY GC864-QUAD-C2
More informationDEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Question Bank Subject Name: EC6504 - Microprocessor & Microcontroller Year/Sem : II/IV
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Question Bank Subject Name: EC6504 - Microprocessor & Microcontroller Year/Sem : II/IV UNIT I THE 8086 MICROPROCESSOR 1. What is the purpose of segment registers
More informationTechnical Properties. Mobile Operating Systems. Overview Concepts of Mobile. Functions Processes. Lecture 11. Memory Management.
Overview Concepts of Mobile Operating Systems Lecture 11 Concepts of Mobile Operating Systems Mobile Business I (WS 2007/08) Prof Dr Kai Rannenberg Chair of Mobile Business and Multilateral Security Johann
More informationVolume Serial Numbers and Format Date/Time Verification
Volume Serial Numbers and Format Date/Time Verification Written by Craig Wilson, MSc MBCS CITP Digital Detective Group October 2003 (updated June 2005) Table of Contents Table of Contents... 2 Introduction...
More informationInterrupts and the Timer Overflow Interrupts Huang Sections 6.1-6.4. What Happens When You Reset the HCS12?
Interrupts and the Timer Overflow Interrupts Huang Sections 6.1-6.4 o Using the Timer Overflow Flag to interrupt a delay o Introduction to Interrupts o How to generate an interrupt when the timer overflows
More informationQLogic SRP Module on Linux for OpenFabrics and InfiniPath Version 1.3.0.0.15. Table of Contents
QLogic SRP Module on Linux for OpenFabrics and InfiniPath Version 1.3.0.0.15 This software license applies only to QLogic customers. QLogic Corporation. All rights reserved. 1. Introduction 2. OS Support
More informationDebugging of Application Programs on Altera s DE-Series Boards. 1 Introduction
Debugging of Application Programs on Altera s DE-Series Boards 1 Introduction This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II
More informationTCG Algorithm Registry. Family 2.0" Level 00 Revision 01.15. April 17, 2014. Published. Contact: admin@trustedcomputinggroup.org.
Family 2.0" Level 00 Revision 01.15 April 17, 2014 Published Contact: admin@trustedcomputinggroup.org TCG TCG Published Copyright TCG 2014 Disclaimers, Notices, and License Terms THIS SPECIFICATION IS
More informationCSC 2405: Computer Systems II
CSC 2405: Computer Systems II Spring 2013 (TR 8:30-9:45 in G86) Mirela Damian http://www.csc.villanova.edu/~mdamian/csc2405/ Introductions Mirela Damian Room 167A in the Mendel Science Building mirela.damian@villanova.edu
More information6809 SBUG-E Monitor ROM Version 1.5
6809 SBUG-E Monitor ROM Version 1.5 The 6809 SBUG monitor ROM is provided to enable the computer to communicate with a terminal for the purpose of various programming and debugging functions. It has been
More informationCortex -M0 Devices. Generic User Guide. Copyright 2009 ARM Limited. All rights reserved. ARM DUI 0497A (ID112109)
Cortex -M0 Devices Generic User Guide Copyright 2009 ARM Limited. All rights reserved. ARM DUI 0497A () Cortex-M0 Devices Generic User Guide Copyright 2009 ARM Limited. All rights reserved. Release Information
More informationEfficient Program Exploration by Input Fuzzing
Efficient Program Exploration by Input Fuzzing towards a new approach in malcious code detection Guillaume Bonfante Jean-Yves Marion Ta Thanh Dinh Université de Lorraine CNRS - INRIA Nancy First Botnet
More informationUNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180B Lab 7: MISP Processor Design Spring 1995
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180B Lab 7: MISP Processor Design Spring 1995 Objective: In this lab, you will complete the design of the MISP processor,
More informationA JIT Compiler for Android s Dalvik VM. Ben Cheng, Bill Buzbee May 2010
A JIT Compiler for Android s Dalvik VM Ben Cheng, Bill Buzbee May 2010 Overview View live session notes and ask questions on Google Wave: http://bit.ly/bizjnf Dalvik Environment Trace vs. Method Granularity
More informationUSB - FPGA MODULE (PRELIMINARY)
DLP-HS-FPGA LEAD-FREE USB - FPGA MODULE (PRELIMINARY) APPLICATIONS: - Rapid Prototyping - Educational Tool - Industrial / Process Control - Data Acquisition / Processing - Embedded Processor FEATURES:
More informationhttp://www.nologin.org Bypassing Windows Hardware-enforced Data Execution Prevention
http://www.nologin.org Bypassing Windows Hardware-enforced Data Execution Prevention Oct 2, 2005 skape mmiller@hick.org Skywing Skywing@valhallalegends.com One of the big changes that Microsoft introduced
More informationIntroduction. Application Security. Reasons For Reverse Engineering. This lecture. Java Byte Code
Introduction Application Security Tom Chothia Computer Security, Lecture 16 Compiled code is really just data which can be edit and inspected. By examining low level code protections can be removed and
More informationInstruction Set Reference
2015.04.02 Set Reference NII51017 Subscribe This section introduces the Nios II instruction word format and provides a detailed reference of the Nios II instruction set. Word Formats There are three types
More informationAltera Monitor Program
Altera Monitor Program This tutorial presents an introduction to the Altera Monitor Program, which can be used to compile, assemble, download and debug programs for Altera s Nios II processor. The tutorial
More informationONLINEHELP. Flexi Soft RK512. RK512 Telegram-Listing. RK512 Telegram-Listing
ONLINEHELP Flexi Soft RK512 RK512 Telegram-Listing RK512 Telegram-Listing GB This document is protected by the law of copyright, whereby all rights established therein remain with the company SICK AG.
More informationThe Operating System and the Kernel
The Kernel and System Calls 1 The Operating System and the Kernel We will use the following terminology: kernel: The operating system kernel is the part of the operating system that responds to system
More informationEMV (Chip-and-PIN) Protocol
EMV (Chip-and-PIN) Protocol Märt Bakhoff December 15, 2014 Abstract The objective of this report is to observe and describe a real world online transaction made between a debit card issued by an Estonian
More informationHacking Leopard: Tools and Techniques for Attacking the Newest Mac OS X
Hacking Leopard: Tools and Techniques for Attacking the Newest Mac OS X Charles Miller Independent Security Evaluators August 2, 2007 cmiller@securityevaluators.com Charles Miller Independent Security
More informationPersist It Using and Abusing Microsoft s Fix It Patches
Persist It Using and Abusing Microsoft s Fix It Patches Jon Erickson : isight Partners : jerickson@isightpartners.com Abstract: Microsoft has often used Fix it patches, which are a subset of Application
More informationCommand Param1 Param2 Return1 Return2 Description. 0xE9 0..0x7F (id) speed pos_high pos_low Set servo #id speed & read position
set Description 0..0x7F (id) Set servo #id target position 0xE1 Read EEPROM 0xE2 Write EEPROM 0xE3 Read memory 0xE4 Write memory 0xE5 Read position 0xE6 Set target position 0xE7 version id Read version
More informationDeveloper Suite ARM. Assembler Guide. Version 1.2. Copyright 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
ARM Developer Suite Version 1.2 Assembler Guide Copyright 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B ARM Developer Suite Assembler Guide Copyright 2000, 2001 ARM Limited. All rights reserved.
More informationJava Virtual Machine, JVM
Java Virtual Machine, JVM a Teodor Rus rus@cs.uiowa.edu The University of Iowa, Department of Computer Science a These slides have been developed by Teodor Rus. They are copyrighted materials and may not
More informationAdvanced Computer Architecture-CS501. Computer Systems Design and Architecture 2.1, 2.2, 3.2
Lecture Handout Computer Architecture Lecture No. 2 Reading Material Vincent P. Heuring&Harry F. Jordan Chapter 2,Chapter3 Computer Systems Design and Architecture 2.1, 2.2, 3.2 Summary 1) A taxonomy of
More informationSoftware based Finite State Machine (FSM) with general purpose processors
Software based Finite State Machine (FSM) with general purpose processors White paper Joseph Yiu January 2013 Overview Finite state machines (FSM) are commonly used in electronic designs. FSM can be used
More informationLeak Check Version 2.1 for Linux TM
Leak Check Version 2.1 for Linux TM User s Guide Including Leak Analyzer For x86 Servers Document Number DLC20-L-021-1 Copyright 2003-2009 Dynamic Memory Solutions LLC www.dynamic-memory.com Notices Information
More informationUsing System Tracing Tools to Optimize Software Quality and Behavior
Using System Tracing Tools to Optimize Software Quality and Behavior Thomas Fletcher, Director, Automotive Solutions QNX Software Systems Ltd. thomasf@qnx.com Gaining Insight At one time, embedded devices
More informationIOActive Security Advisory
IOActive Security Advisory Title Severity Discovered by Admin ACL Bypass and Double Fetch Issue in F-Secure Internet Security 2015 High/Important Ilja van Sprundel Advisory Date September 3, 2015 Affected
More informationApplication Report AN01286 May 2012
Application Report Diagnosing Software Faults in Stellaris Microcontrollers Joe Kroesche, Stellaris Software ABSTRACT During typical development efforts, system operation can sometimes end up in a fault
More information