VPX. Sub headline on second deck. GE Fanuc Intelligent Platforms

Transcription

1 VPX Sub headline on second deck GE Fanuc Intelligent Platforms

2 Forward The VPX standard (ANSI/VITA ) represents the culmination of over four years of effort by a dedicated committee made up of system integrators and COTS manufacturers. Remarkably the standard achieves two opposing goals: (i) VPX incorporates state-of-the-art technology in order to deliver levels of performance and I/O connectivity until now unheard of in an open architecture COTS standard, a revolutionary step forward. (ii) VPX maintains mechanical and electrical compatibility with VMEbus and other comparable architectures allowing equipment upgrades to more easily take advantage of new the new technology, an evolutionary step forward. These dual strengths mean that VPX can be seen as a candidate solution for both totally new equipment builds and upgrades where it may be most cost effective to retain key legacy board level or chassis components. VPX the Book has been designed to provide an introduction to VPX technology. As such this document should make the reader familiar with the basic concepts, application related features and decision criteria to allow informed decisions to be made when specifying, evaluating or simply using VPX technology. For information purposes this book also attempts to provide a preview of future enhancements to the VPX infrastructure. VPX the Book does not, however, replace a thorough study of the relevant standards required in order to be able to design, certify or troubleshoot components or systems based upon VPX technology. The book is organised into a number of easy to read sections: Section 1 VPX Executive Summary provides a non-technical introduction to VPX identifying its key features and where it is most likely to be used. Section 2 ANSI/VITA VPX Technical description analyses key aspects of the baseline standard and explains the rationale behind the inclusion of major features. Section 3 VPX application offers a number of VPX design examples and introduces the Dot specifications that define incorporation of architectures such as VMEbus. Section 4 Future enhancements describes planned enhancements to VPX including VITA 48 (REDI) Appendix A Sources of further information references VPX and related standards. Section 1 VPX Executive Summary 1.1 Why VPX? The need for a new standard VPX objectives The progression to VPX What is VPX? Features and benefits Board level mechanics MultiGig RT2 connector system Serial fabric connections Hybrid backplanes and legacy architectures Why and where to use VPX 00 Section 2 ANSI/VITA VPX Technical description 2.1 Introduction VPX baseline standard compliance System level considerations Safety Ground Power supply System Functions Common requirements Overview Connectors Form Factors Alignment and Keying Two Level Maintenance Geographical Addressing P1 connector signals U modules 00 2 gefanuc.com VPX 3

3 2.6 6U modules U Backplane Keying VPX backplanes Hybrid Backplanes 00 Section 3 VPX application 3.1 Example architectures Development environments Dot standards ANSI/VITA , VMEbus signal mapping VITA46.1 application VITA 46.3 Serial RapidIO on VPX Fabric Connector VITA46.3 application VITA 46.4 PCI Express on VPX Fabric Connector VITA46.4 application PCIe Endpoints and Root Complex VITA 46.7 Ethernet on VPX Fabric Connector VITA 46.9 PMC/XMC signal mapping VITA Rear Transition module for VPX 00 Section 4 Future enhancements Appendix A Sources of further information 00 VPX standards 00 Related standards 00 Appendix B Signal mapping for a 3U VPX Rear Transition Module Figures Page Figure 1 Key VPX (VITA 46.0) working group members 00 Figure 2 VPX standardisation development 00 Figure 3 Serial fabric interconnect options 00 Figure 4 VME, VXS and VPX form factors 00 Figure 5 Key board level dimensions, 3U VPX 00 Figure 6 VPX connector positions 00 Figure 7 3U and 6U form factor board level features 00 Figure 8 The Tyco MultiGig RT2 connector 00 Figure 9 A serial fabric lane 00 Figure 10 A switched fabric network 00 Figure 11 VPX and VMEbus 00 Figure 12 VPX Market positioning 00 Figure 13 MAGIC1 embedded training solution 00 Figure 14 An embedded training scenario 00 Figure 15 The VPX logo 00 Figure 16 Power wafer to backplane pin mappings 00 Figure 17 Single ended wafer mappings 00 Figure 18 Odd differential wafer mappings 00 Figure 19 Even differential wafer mappings 00 Figure 20 VPX connector definitions 00 Figure 21 VITA 46 Keying system 00 Figure 22 Mechanical and ESD protection covers 00 Figure 23 SBC340 block diagram 00 Figure 24 SBC340 P1 connector signal designations 00 Figure 25 3U air cooled module key dimensions 00 Figure 26 3U conduction cooled module key dimensions 00 Figure 27 6U conduction cooled module key dimensions 00 Figure 28 A 9 slot 3U VPX backplane 00 4 gefanuc.com VPX 5

4 Figure 29 A conceptual VPX/VXS/VME64 hybrid backplane 00 Figure 30 SBC610 VPX module with VME interface 00 Figure 31 VPX bridging to VME in an Axis MultiComputer 00 Figure 32 A VPX graphics architecture 00 Figure 33 A VPX processing architecture 00 Figure 34 A nine slot VPX architecture 00 Figure 35 A compact, rugged, nine slot VPX chassis for 3U boards 00 Figure 36 The SBC320 and its VPX3UX Rear Transition Module 00 Figure 37 VPX3UX Rear Transition Module block diagram 00 Figure 38 A VPX development chassis with rear 6U RTM slots 00 Figure 39 3U form factor VMEbus signal mapping 00 Figure 40 Y46.1-8S-3:2-6U hybrid backplane 00 Figure 41 PPC9A and SBC610 Single Board Computer architectures 00 Figure 42 Five payload slots connected together 00 Figure 43 Generic Serial RapidIO architecture 00 Figure 44 DSP230, a 6U VPX module with Serial RapidIO 00 Figure 45 DSP230 block diagram 00 Figure 46 VITA 46.4 PCI Express through the VPX P1 connector 00 Figure 47 SBC310 Single Board Computer with PCIe connection 00 Figure 48 A generic PCI Express architecture 00 Figure 49 PCIe Endpoint processors 00 Figure 50 SBC320 which can act as Root Complex or Endpoint 00 Figure 51 VITA 46.7 Ethernet mapping 00 Figure 52 VITA 46.9 mapping patterns 00 Figure 53 P2-P64s mapping 00 Figure 54 3U VPX Rear Transition Module connector definition 00 Figure 55 REDI Glyphs 00 Tables Page Table 1 References, the road to VPX 00 Table 2 VPX features and benefits 00 Table 3 Key board level dimensions 00 Table 4 P0 and P1 connector definitions 00 Table 5 Key serial fabrics in active use today 00 Table 6 P0 Utility Connector 00 Table 7 VPX connector wafers 00 Table 8 Geographical Address pin assignments 00 Table 9 P1 connector signal set 00 Table 10 3U module connectors 00 Table 11 6U module connectors 00 Table 12 High Voltage Power Input Key 1 options 00 Table 13 6U case slot keying 00 Table 14 Serial RapidIO P1 connector link population 00 Table 15 VITA 46.9 mapping patterns 00 Table 16 REDI standards under development 00 6 gefanuc.com VPX 7

5 Section One VPX Executive Summary 8 gefanuc.com VPX 9

6 VPX Executive Summary 1.1 Why VPX? The need for a new standard The first VMEbus specification, VME32, was published in August 1982 and later became IEEE Remarkably this and derivative architectures are still in active use today, testament to the skills of the designers and standard custodians that have guided its existence. The longevity of VMEbus does, however, prompt a question. Why has VMEbus survived for so long when other architectures such as MultibusTM have fallen by the wayside? To answer this question many might point to technical excellence and this is in part true. Innovation has been a key part of the VME story and designers have continued to push the boundaries. Evidence of this is provided by the VME 2eSST standard (ANSI/VITA ); a flexible and feature rich interconnect with the capability to move data at up to 320 Mbytes/ second, a far cry from the 40 Mbytes/second of the original VME32 standard. There is an alternative explanation for the continued use of the VMEbus architecture though. Successive VMEbus generations have retained backward compatibility; they have been evolutionary steps forward rather than revolutionary. Thus if an integrator had a mind to he or she could deploy an early generation IEEE-1014 compliant, 16 or 32 bit, board in a VME 2eSST, 64 bit, system. Such a career limiting move is of course unlikely but it illustrates both a strength and a weakness. The strength is that as each new VMEbus generation has been introduced it has always been possible to carry forward legacy boards into that new environment. The weakness, of 10 gefanuc.com VPX 11

7 course, is that carrying such history forward can stifle innovation. Of candidate improvements only those that can co-exist and interoperate with previous generations are eligible for inclusion whenever an updated standard is under consideration. By default performance increases tend to be moderated and incremental. Contrast this story with what has happened in the wider computing market over recent years. Multi-core designs have pushed us beyond the comfort zone of Moore s law and delivered step increases in performance. Similarly PCIexpress and other high speed serial interconnect technologies have revolutionised inter-processor communications. Data bottlenecks no longer limit performance increases VPX objectives VPX was developed by a working group made up of both system integrators and COTS vendors. Figure 1 identifies key working group members. Not unnaturally system integrators witnessed such widespread changes and had little difficulty in seeing how they could benefit applications. Frustratingly though integrators also realised that VME and the other parallel buses that they were using could never innovate fast enough to catch wider technological advances. What s more even if a partial solution could be found connector sets and other fixed parameters placed a natural ceiling on performance. Enhancements would never be able to break free of the curve that had mapped development for over twenty-five years. Thus, a need for VPX was born. The market had a thirst for a compatible, but revolutionary, technology that packed new features and could be deployed alongside existing architectures to enable new applications. Figure 1. Key VPX (VITA 46.0) working group members 12 gefanuc.com VPX 13

8 Pooling many years of experience the working group defined a set of broad objectives that VPX had to achieve: 6 Establish an advanced COTS standard for the mil/aero market Offering more I/O at higher data rates and with support for serial fabrics 6 Retain standard 6U and 3U form factors Height, depth, pitch, conduction-cooled interfaces, etc. Support existing PMC and XMC mezzanines 6 Full compatibility with VME boards Hybrid backplane ensures existing VME boards can be used with new equipment 6 Support high-speed serial fabrics on the backplane PCI Express, Serial RapidIO, Infiniband, 10G Ethernet etc. 6 Improved logistics ESD-protected connector and optional covers facilitate 2-level maintenance Practically, the ratified VPX standard either achieves all these goals or passes responsibility to a lower tier dot specification (section 3.3). VPX the Book provides an overview of how VPX achieves these goals in section 1.2 and a detailed technical review in Section The progression to VPX Having established a set of high-level objectives members of the VPX working group looked to how they might achieve them and to what other operational details they should build into a new standard. In doing this they based their efforts on information taken from two major sources: (ii) New features that experience suggested or performance enhancements required. Considering the first of these factors it s fair to say that through employing such previously standardised mechanisms VPX arrived with a proven pedigree. At this stage it is important to recognise the genealogy of VPX and identify the standards that shaped its development including the VME:VXS:VPX progression. For completeness a number of older IEEE standards are also included in the table below in order to identify the first definition of comparable technologies prior to adoption, reference or further development by ANSI/VITA committees. Standard IEEE IEC IEEE ANSI/VITA Overview VME32 standard. Baseline 8/16/32 bit parallel bus standard. Based on the VMEbus specification, released by the VME Manufacturers Group in August of Electromechanical components for electronic equipment: Basic testing procedures and measurement methods IEEE Standard for Mechanical Core Specification for Conduction- Cooled Eurocards VME64 Standard - This standard covers the main body of the VMEbus specification. It includes both 32 bit and 64 bit usage. Reaffirmed in (i) Proven, user must have features found in existing standards, most notably the ANSI/ VITA series. 14 gefanuc.com VPX 15

9 IEEE ANSI/VITA IEEE Standard for Additional Mechanical Specifications for Microcomputers using IEEE STD Equipment Practice. Includes: Positive alignment pin, unit keying, injector/ejector handles, card guide/front panel ESD contacts. Reaffirmed 2002 VME64 Extensions - This standard covers extensions to the VME64 specification including the 160 pin connector, geographical addressing, and added 3.3V power pins. Reaffirmed in 2003 ANSI/VITA ANSI/VITA ANSI/VITA System Management for VME Environments, Design and Construction, Safety and Quality for plug in units VXS, VMEbus Switched Serial Standard - This standard defines a method for using switched serial fabrics over a high performance P0 connector within the VMEbus framework IEEE IEEE The I2C Bus Specification IEC :2001 IEEE ANSI/VITA ANSI/VITA ANSI/VITA IEEE Standards for Mechanical Core Specifications for Microcomputers using IEC connectors IEEE Standard for Mechanical Rear Plug in Units Specifications for Microcomputers Using IEEE and IEEE Equipment Practice Version 2.1 January 2000 (Philips Semiconductor) Information Technology Equipment - Safety part 1 general requirements IEEE Standard Test Access Port and Boundary Scan Architecture CCPMC - Conduction Cooled PMC - This standard defines the mechanical requirements for compliance with conduction cooled PMC modules. Revised in mm Connector Practice for Conduction Cooled Euroboard Systems - This standard defines the dimensions for conduction cooled Euroboards when used with 2mm connectors. 2eSST - This standard defines a new VME dual edge source synchronous block transfer protocol that allows data transfers of up to 320 Mbytes/second. ANSI/VITA ANSI/VITA VXS 4X Serial RapidIO Protocol Layer Standard - This standard describes a method for implementing Serial Rapid I/O on ANSI/VITA 41.0, VXS Baseline VPX standard Table 1. References, the road to VPX (Standards are available from their respective owners) 16 gefanuc.com VPX 17

10 1.2 What is VPX? VPX (ANSI/VITA ) establishes a new direction for the next revolution in bus based architectures. Now ratified as an ANSI/VITA standard VPX breaks from the traditional VMEbus connector scheme merging the latest in packaging technology with the latest in bus and serial fabric technology. VPX combines best in class technologies to assure a long technology cycle similar to that of the original VMEbus solutions. VPX also supports existing architectures, such as VMEbus, through bridging schemes that assure a solid migration pathway. These bridging schemes are defined in the dot standards identified in Figure 2. Technologies incorporated in VPX include: 6 3U and 6U formats 6 New 7 row high speed connector rated at up to 6.25 Gbps 6 Choice of high speed serial fabrics used as the primary interconnect between modules 6 PMC and XMC mezzanines 6 Alignment pins with keying mechanism 6 Hybrid backplanes to accommodate VME64, VXS and VPX boards Architecturally it is the use of serial fabric interconnects that most shapes VPX system design. A technology overview is provided in section but the important thing to note is that each serial fabric is a point to point, serial, data pipeline. If this point to point pipeline, or link, needs to connect to several possible endpoints then a switch is required to achieve this. Also, if increased data communication bandwidth is required multiple pipelines can be connected in parallel. To illustrate this consider a number of VPX compute nodes, each having two serial fabric ports. These can be connected in a variety of ways depending upon the functionality required. Figure 3 illustrates several options. Figure 2 VPX standardisation development (source A B (i) 2 nodes, each must be able to pass data directly the other node A B C (ii) 3 nodes, each must be able to pass data directly to each of the other nodes 18 gefanuc.com VPX 19

11 A B C D Switch (iii) 4 nodes, each must be able to pass data directly to each of the other nodes Features and Benefits Features and benefits of VPX Technology concentrate on real-time, deterministic operation in harsh environments with demands on high reliability/availability and a requirement for long-term availability. A B Figure 3. Serial fabric interconnect options (iv) 2 nodes, each must be able to pass data directly the other node, similar to case (i) but data bandwidth needs to be doubled Clearly as the way that the VPX module serial fabrics are connected determines functionality and connections are not repetitive, bussed, lines the backplane that carries this interconnect will vary between systems. Standard VPX modules such as A, B, C and D in Figure 3 can be connected in different ways, by different backplanes, in order to deliver different operational functionality. This is why there will, over time, be many VPX backplane designs, each being specific to a particular application. As a side issue some serial fabrics operate in a master-slave relationship. For example PCI Express has the concept of a Root Complex master and an end point slave. If a PCI Express link from a VPX module can only be a Root Complex then the only way that it can communicate with another similar module is through a switch. Section deals with this in greater detail but suffice to say switches are sometimes required even when a connection is a single point to point link. The inclusion of a switching element from day one does, however, ensure future upgradeability and in this context it is sometimes a prudent investment. VPX feature Preserves proven 3U and 6U mechanical form factors Inclusion of a high performance connector set Dedicated power connector Inclusion of a robust alignment and keying method Hybrid architectures supported Overview Simplified system upgrades often only requiring the inclusion of a VPX backplane Supports high speed signals allowing use of serial fabrics and other high performance interconnects Provides increased number of I/O pins with both single ended and differential options Modular wafer structure opens the door to specialised functionality including optical connections Ensures delivery of high quality supply voltages even at very high power levels Ensures that VPX modules are inserted correctly minimising the possibility of connector damage and promoting longevity Ensures that VPX modules can only be plugged into their allocated slot Allows inclusion of legacy backplane segments such as VMEbus (specified through dot specifications) 20 gefanuc.com VPX 21

12 Supports 2 Level Maintenance (2LM) Standardises new cooling methodologies for high power applications Allows alternative card slot pitches Committed support from large number of system integrators and COTS manufacturers Table 2 VPX features and benefits Covers, defined in VITA 48 REDI, provide mechanical and ESD protection for modules allowing board level field upgrades Power densities are increasing, standardising future candidate cooling solutions, such as Liquid Flow Through defined in VITA 48 REDI, prevents the growth of incompatible solutions Wider slot pitches (0.8, 0.85 and 1 inch) simplify cooling and allow inclusion of tall board level devices such as high capacity FLASH disks. Ensures high VPX adoption rates and market longevity Board level mechanics As previously stated VPX preserves both the 3U and 6U Eurocard mechanics made popular by VMEbus, CompactPCI and other similar architectures. This covers both air cooled and conduction cooled formats. Figure 4 illustrates this consistency by showing a 6U form factor multiprocessing solution implemented across VME, VXS and VPX architectures. VME: G4DSPXE VXS: DSP220 VPX DSP230 Figure 4. VME, VXS and VPX form factors 22 gefanuc.com VPX 23

13 Figure 5 illustrates the dimensions for a 3U VPX board while, for comparative purposes, Table 3 details key dimensions for VMEbus, CompactPCI and VPX architectures. image cant open cdr file Architecture Reference Depth Width 3U VME ANSI/VITA mm 100mm 3U CompactPCI PICMG 2.0 Rev 3.0 ANSI/VITA mm 100mm 3U VPX ANSI/VITA mm 100mm 6U VME ANSI/VITA mm 233mm 6U CompactPCI PICMG 2.0 Rev 3.0 ANSI/VITA mm 233mm 6U VPX ANSI/VITA mm 233mm Table 3. Key board level dimensions With reference to Table 3 then it should be noted that VPX mechanics are compatible with IEEE and ANSI/VITA (Conduction cooled boards) and IEEE /10 and PICMG 2.0 Rev 3 (air cooled boards) ensuring complete compatibility with existing enclosures. The VPX standard, ANSI/VITA , defines connector positions and basic signalling options at the physical layer. It also defines the metal alignment and keying blocks that also provide a safety ground connection. Figure 6 illustrates connector positioning while Figure 7 translates these features to real board level products. Note: as with VMEbus board level connectors are defined as P0, P1, P2 and so on (P for Plug in module) while the corresponding backplane connectors are numbered J0, J1, J2. Figure 5. Key board level dimensions, 3U VPX. 24 gefanuc.com VPX 25

14 3U board Alignment and keying PO P1 P2 P0 is defined as a power/utility connector. P1 is loaded with 16 differential wafers (see section 1.2.3) Figure 6. VPX connector positions 8 wafers 16 wafers 3U board Alignment and keying PO P1 P2 P3 P4 P5 P6 8 wafers 16 wafers MultiGig RT2 connector system At the heart of the VPX standard is a new, high bandwidth connector system. The defined connector system is constructed from individual wafers stacked together to form connector blocks. Each wafer supports 7 connections, hence it is termed a 7 row wafer. As an open standard VPX can not explicitly name a particular manufacturers proprietary technology, however, at launch only the Tyco MultiGig RT2 was available as meeting the requirements. Thus the VPX standard identifies Tyco part numbers but allows the use of an equivalent when such becomes available. Table 4 acknowledges this. Connector P0 Description Left end module, 8 wafers, right angle Tyco part number , or equivalent Tyco MultiGig RT2 connectors Robust alignment and keying blocks that also provide a safety ground P1 Centre module, 16 differential wafers, right angle Tyco part number , or equivalent Table 4. P0 and P1 connector definitions SBC310 SBC610 Full length PMC/XMC sites with rear I/O capability Figure 7. 3U and 6U form factor board level features Figure 8. The Tyco MultiGig RT2 connector 26 gefanuc.com VPX 27

15 A more complete description of the connector system is given in section 2.3 but for now it is important to recognize that within each connector block wafers can be defined as one of three types: Power P0 Single ended P0 and P2 to P6 (see dot specification definitions) Differential P0, P1 and P2 to P6 (see dot specification definitions) P0, the power and utility connector, delivers power and a number of general purpose control signals such as SYSRESET*, JTAG and Geographical Addressing. As a result it requires multiple wafer types, heavy duty power traces, single ended and differential. The new connector provides for a total of 707 non-power electrical contacts and a total of 464 signal contacts. The latter are usable as: 6 64 signals implemented as 32 high speed differential pairs for core fabric VME64 signals signals for user I/O, including 128 high speed differential pairs 6 28 for system utilities or spares Technically the connector system delivers highly controlled impedances, minimal insertion loss and less than 3% crosstalk at transfer rates up to 6.25 Gbit/second. A 3U board features one 8-column 7-row RT2 connector (P0) and two16-column 7-row RT2 connectors (P1, P2). A 6U VPX board features one 8-column 7-row RT2 connector (P0) and six 16-column 7-row RT2 connectors (P1 to P6). In addition to its signaling properties the connector was also chosen because it allowed a central stiffening bar and a standard length PMC/XMC to fit within the standard board depth. This ensured that current and legacy PMC/XMC modules could be used within the VPX environment. Prior to inclusion in the VPX standard the new Tyco MultiGig RT2 connector system was submitted to Contech Research, Inc. for independent and exhaustive reliability qualification testing in order to establish its suitability for harsh military environments. Tests performed by Contech included: 6 shock 6 random vibration 6 bench handling 6 humidity 6 salt fog 6 sulphur dioxide 6 dust and sand 6 durability with misalignment 6 ESD 6 current overload. The ruggedness of the MultiGig RT2 connector was found to be exemplary, with similar performance under stress conditions to that of existing VMEbus connectors. A full test report can be downloaded from 28 gefanuc.com VPX 29

16 1.2.4 Serial fabric connections With parallel busses such as VME and CompactPCI multiple data lines need to settle to a valid state before they can be clocked into a recipient board. Performance is ultimately limited by this settling time or synchronisation delay, the determination of which is a complex calculation depending upon many factors. Most easy to understand is skew introduced across multiple data lines by the different signal trace lengths employed. Thus by simple physics a signal can arrive before its neighbour because it encountered a shorter length of copper en route. To a degree this can be controlled by careful backplane layout but this is not always easy as standards such as VMEbus interleave data lines with other signals that may not simply be bussed between adjacent slots. Note also the physical structure of a VMEbus or CompactPCI connector. The inner pins offer a shorter signal path than the outer yet data and control signals travel on both. Also data may be split across multiple connectors contributing to variations in on card signal trace lengths and a worst case scenario that timings defined in a standard must consider. inductive and resistive loading components. The lumped or distributed loading model is then further complicated by the fact that a signal may only reach a valid state once it has encountered a number of reflections. To reach a valid state on the first pass involves incident wave switching, a topic considered in more detail in more advanced texts. By using serial fabrics VPX exhibits none of this complexity. Data flows in each direction along a pair of dedicated conductors, as illustrated in Figure 9. This makes it relatively simple to match trace lengths. In addition connectors have been chosen to further match signal path lengths and minimise cross talk, measures reinforced by careful signal mapping. Finally all links are point to point simplifying the task of controlling impedances and termination. Packet Secondly there is the issue of cross-talk. Changes on one signal trace can induce comparable changes on nearby traces and the need to let this noise settle can lengthen cycle times. Again careful backplane design and the use of guard tracks can limit the effects of this problem but if the connector design and signal mappings are not optimum then this can be an uphill struggle. Node A LANE Node B More complex is the analysis of bus loading and termination that defines how and when a data bit achieves a valid state. Modelling this accurately was an essential part of the formulation of advanced specifications such as ANSI/VITA and it is made more difficult by the fact that on card functionality and signal trace lengths can vary between slots. Thus each slot may present a different characteristic impedance due to variations in capacitive, Figure 9. A serial fabric lane Packet 30 gefanuc.com VPX 31

17 The result is that a well designed parallel bus can achieve 80 MTransfers per second, or, looking at it practically, 320 Mbytes/second in one direction for a 64 bit bus. By contrast a single PCI Express serial fabric lane (Figure 9) can deliver 250 Mbytes/second in each direction, a potential of 500 Mbytes/second. Next generation fabrics will raise the bar even further. It is important to note that serial fabrics still experience latency, there will be a delay through copper traces. Latency is consistent though and because each lane is self clocking there is no associated synchronisation delay to limit performance. Reliability. It is possible to add error detection recovery mechanisms to each serial fabric. For this consider proven techniques utilised for many years in conventional serial protocols such as X.25. S: 4 port switch A,B,C,D: Single Board Computers G: Graphics Processing Unit Serial fabric lanes can be combined in order to deliver increased performance. A X4 link consists of four lanes of the type illustrated in figure 9. In the case of PCI Express then this equates to 1 Gbyte/second in each direction. Similarly a X16 link consists of sixteen lanes of the type illustrated in figure 9 corresponding to 4 Gbytes/second in each direction in the case of PCI Express. Again as individual lanes are self clocking performance is not restricted by such parallelism and data synchronisation becomes a higher level function.. In addition to performance serial fabrics offer better scalability, availability, and reliability: Scalability. If a data path requires increased bandwidth then in principle this simply requires more serial fabric lanes to be allocated. Note the high bandwidth X16 link between Single Board Computer (A) and its Graphics Processing Unit (G) in Figure 5. I/O C X1 I/O D S X1 X1 X1 G A X16 Availability. Point to point serial fabrics, such as the X1 link between Single Board Computer A and Single Board Computer D in Figure 5, are a dedicated resource not shared with any other nodes. No arbitration is required to gain control as would be required for a shared VME or CompactPCI bus. Note: availability is a prerequisite to determinism and real-time performance X1 I/O X1 B Figure 10. A switched fabric network 32 gefanuc.com VPX 33

18 Considering the availability and reliability issues further then switches and/or data relay techniques allow alternative data routings to be built into an architecture. In Figure 5 Single Board Computers A and D normally utilise a direct X1 link. However, there is an alternative routing through Switch S should the direct A:D routing be unavailable. The Switch S may be included specifically for this purpose or because on occasion A needs to pass data to/from C or B. Serial FPDP FireWire (IEEE 1394) 10G Ethernet Table 5. Key serial fabrics in active use today At time of writing in excess of sixty serial fabrics were in active use. To some this may seem excessive but it must be recognised that each has been developed to serve a particular market need. As such there is likely to be little short term rationalisation of this situation. Rather many of the fabrics listed in Table 5 are likely to remain in active use for many years to come. It should also be recognised that many of the fabrics listed in Table 5 share the same, or very similar, physical layer definitions. Thus the VPX baseline standard, ANSI/VITA , can allocate signal pairs across each connector for direct use or for further consideration in the appropriate dot specification. The dot specifications will be considered in more detail in section Hybrid backplanes and legacy architectures VPX is able to incorporate legacy architectures through allocation of specific connector pins to the required signal set. Such definitions will form part of dedicated ancillary standards. These legacy pin mappings will only be used on the slots that require access to legacy architectures. By definition such slots will be part of a VPX/legacy hybrid backplane. In the case of ANSI/VITA the legacy interface is VMEbus and the hybrid backplane will consist of a VPX segment, with VPX connectors, and a VMEbus segment, with VMEbus connectors. Serial Fabric PCI Express (PCIe) Serial RapidIO Infiniband Starfabric (Stargen) Fibre Channel USB 2.X Hypertransport Bus Serial ATA (SATA) ATM Reference Figure 11 illustrates the ANSI/VITA arrangement for VMEbus. A more detailed consideration of hybrid backplanes is given in section gefanuc.com VPX 35

19 6U board A32:D32 (ANSI/VITA ) Row G Row F Row E Row D Row C Row B Row A 1 D08 ACFAIL* GND BBSY* GND SYSFAIL* D00 2 D09 BG2IN* GND BCLR* GND BR0* D01 3 D10 BG2OUT* GND BG0IN* GND BR1* D02 4 D11 BG3IN* GND BG0OUT* GND BR2* D03 5 D12 BG3OUT* GND BG1IN* GND BR3* D04 6 D13 BERR* GND BG1OUT* GND AM0 D05 7 D14 LWORD* GND SYSCLK GND AM1 D06 8 D15 AM5 GND DS1* GND AM2 D07 9 A22 A23 GND DS0* GND AM3 AM4 10 A20 A21 GND WRITE* GND IRQ7* A07 11 A18 A19 GND DTACK* GND IRQ6* A06 12 A16 A17 GND AS* GND IRQ5* A05 13 A14 A15 GND IACK* GND IRQ4* A04 14 A12 A13 GND IACKIN* GND IRQ3* A03 15 A10 A11 GND IACKOUT* GND IRQ2* A02 16 A08 A09 GND RETRY* GND IRQ1* A01 P0 is mapped as per VITA 46.0 (includes SYSRESET*) P1 is mapped as per the appropriate serial fabric dot standard Figure 11. VPX and VMEbus A24 to A32 Other signals as V46.0 D16 to D23 Other signals as V46.0 D24 to D31 Other signals as V P0 Utility P1 Differential P2 Single ended P3 Differential P4 Differential P5 Differential P6 Differential As V46.0 From figure 11 the following rules can be defined: 6 A 6U board mapping P2 to P5 can achieve full VMEbus A32:D32. 6 A 6U board mapping P2 only for VMEbus achieves VMEbus A24:D16. 6 A 3U board, which can only map P2 to VMEbus can achieve A24:D Why and where to use VPX Firstly it is important to recognise that VPX has not been designed to replace existing architectures such as VMEbus. Fundamentally VPX provides new features and a massive increase in performance opening the door to a new generation of applications that could previously only be served by bespoke solutions. Military/Aerospace Defense electronic subsystems $18 Billion* (including proprietary) Figure 12. VPX Market positioning From figure 12 it can be seen that VPX has the potential to encroach upon certain highend VMEbus solutions. 36 gefanuc.com VPX 37

20 In part this is due to the fact that it is possible to realise hybrid architectures mixing existing, legacy, VMEbus components with higher performance VPX bus segments. Thus today s designs that combine proven and highly cost effective VME I/O components with VMEbus central processing elements that are struggling to maintain the required data throughput can be replaced by a VME/VPX solution. The real world VMEbus I/O modules are retained and through the use of a new system backplane are combined with a high performance VPX processing sub-system. It is also true to say that VPX represents a more natural solution for some of today s more difficult signal processing applications. Consider multiple VMEbus quad processor boards strapped together to form a single multiprocessing array. VMEbus in itself does not provide the bandwidth required for inter-nodal data transfer. As a result existing VME solutions often use star fabric, Ethernet or even a bespoke data communication mechanism to support high speed data movement between nodes and boards. Under these circumstances VMEbus becomes little more than a command and control bus. VPX using multiple switched fabric interconnect lanes can provide a scalable architecture that embodies the required inter-processor communication protocols. In practice Serial RapidIOTM is often utilised as the interconnect of choice for such applications. What s more, through the use of dedicated switches and redundant communication links, such a VPX architecture can include the resilience to cope with varying data throughput loading and even link failures. In short VPX offers improved scalability, availability, and reliability. Many of these high-end applications have until now been forced to use custom or proprietary solutions. As a result they have not normally been able to benefit from the reduced through life cost base offered by COTS components supplied through an open and competitive market environment. Typically these new VPX applications are characterised by one or more of the following traits: (i) The requirement for extremely high levels of performance. Even in large configurations the use of inter-module switch fabric connections delivers full silicon performance to the application. (ii) The requirement to produce a physically compact solution. In this context 3U VPX packs a powerful punch. Thanks to increased integration a 3U VPX card often carries the functionality of a 6U VMEbus card. The key difference is that normally the 3U VPX card also delivers much higher performance! (iii) Simplification or unification of the software environment. Switched fabrics originate directly from processing elements. Consequently software tends to be more portable and there is little room for a board level designer to introduce a core data transport mechanism requiring special driver software. (iv) The need for a flexible, modular solution. Particularly in its 3U format VPX modules tend to each focus on the delivery of specific functionality processing, storage, graphics processing, I/O and so on. By combining different sets of modules extremely cost effective and focussed solutions can be realised. Looking at the bigger picture then VPX provides a solution for many of the more demanding sets of requirements where VMEbus, CompactPCI and other similar open architectures have never been able to present a viable solution. 38 gefanuc.com VPX 39

21 As an example of what can be achieved consider the MAGIC1 embedded training solution illustrated in Figure 13. In this application the MAGIC1 needs to interpret vehicle controls, compute actions and deliver very high graphics rendering performance in order to maintain high frame update rates together with high image detail to vehicle displays. Conceptually this is illustrated in Figure 14. Of course the MAGIC1 needs to be small in order to locate in a cramped land vehicle environment. It also has to be extremely rugged. Practically the MAGIC1 must also be based upon an Intel processing solution running a Microsoft or Linux operating system in order to allow use of the many available COTS scene generation development tools. Imaging Device Fire Control Drive System Image Generator Mission Simulator Controls Inputs Figure 14. An embedded training scenario To achieve the required performance the MAGIC1 utilises a combination of three 3U VPX modules: 6 SBC340 processor module 6 GRA110 Graphics Processing Unit (GPU) 6 SDD910 FLASH disk module For details reference should be made to VPX connectivity supports a X16 PCI Express link between the SBC340 and GRA110 delivering a massive 4 GBytes/second data pipe for image data. This data flow is not interrupted by control inputs or disk traffic though, these route through separate links. Figure 13. MAGIC1 embedded training solution 40 gefanuc.com VPX 41

22 No other COTS standard can deliver such a compact, high performance solution. This is exactly why VPX technology is finding a natural home in applications such as radar data processing, Software Defined Radio, surveillance image processing, FPGA networks and many other similar high-end applications. Having said this there is also another very important reason for the rapid adoption of VPX. Market forces and the sheer elegance of implementations tend to result very cost effective solutions! Other market segments that could benefit from the use of VPX technology include: Section Two ANSI/VITA VPX Technical description 6 medical 6 scientific 6 signal processing 6 aerospace 6 industrial automation and control 6 measurement/instrumentation 6 transportation 6 communications 6 man portable compute platforms 42 gefanuc.com VPX 43

23 ANSI/VITA VPX Technical description 2.1 Introduction Section 2 of VPX the Book highlights key features of the VPX baseline specification, ANSI/ VITA The intent is to offer background information, pointers to other sources of information and where useful the rationale behind the inclusion a particular feature. As such this section is intended to be a useful introductory text for VPX system designers, specifiers and users alike. It is suggested that this section be read in conjunction with the VPX standard, not instead of it! For convenience chapter headings have been selected to match those found in the VPX baseline specification itself. VPX, and therefore VPX the Book, use the following convention with regard to keywords: 6 Rule 6 Recommendation 6 Suggestion 6 Permission 6 Observation Rule Rules form the basic framework of the VPX standard. They are sometimes expressed in text form and sometimes in the form of figures, tables, or drawings. All rules shall be followed to ensure compatibility between board and backplane designs. All rules use the shall or shall not words to emphasize their importance. 44 gefanuc.com VPX 45

24 Recommendation Wherever a recommendation appears, designers would be wise to take the advice given. Doing otherwise might result in poor performance or problems that are difficult to resolve. Recommendations found in the VPX standard are based on experience and are provided to designers to speed their traversal of the learning curve. All recommendations use the should or should not words to emphasize their importance. Suggestion A suggestion contains advice which is helpful but not vital. The reader is encouraged to consider the advice before discarding it. Some design decisions that need to be made are difficult until experience has been gained. Suggestions are included to help a designer who has not yet gained this experience. Permission In some cases a rule does not specifically prohibit a certain design approach, but the reader might be left wondering whether that approach might violate the spirit of the rule, or whether it might lead to some subtle problem. Permissions reassure the reader that a certain approach is acceptable and will cause no problems. All permissions use the term may to emphasize the importance of the permission. Observation Observations do not offer any specific advice. They usually follow naturally from what has just been discussed. They spell out the implications of certain rules and bring attention to things that might otherwise be overlooked. They also give the rationale behind certain rules, so that the reader understands why the rule must be followed. 2.2 VPX baseline standard compliance VPX is a complex standard with many options and dependencies. Historically such flexible standards have achieved a degree of notoriety because vendors have rushed to declare compliance even though they may only be offering partial solutions. To prevent such an injustice the VPX standard opens with a definition of the minimum feature set that must be incorporated in any compliant plug-in module or backplane. As a result users can be assured that modules will offer the correct connector set, keying and alignment, support for power rails, support for utility signals and of course support for one or more of the various protocol layer standards. In its compliance section the VPX standard also recommends that vendors should consider offering compliance to appropriate sections of ANSI/VITA 47. There is in fact no deep, meaningful, technical reason for this recommendation, VITA 46 and VITA 47 exist as two totally separate standards and neither relies on the other for its existence. Rather the reason for this recommendation is that over the years vendors have evolved their own environmental performance definitions. From a users perspective it would be convenient if all manufacturers adopted a common standard, such as VITA 47, in order to allow a direct comparison to be made between VPX modules. This is a noble, long term, goal but in the short term the fact that legacy cards and chassis may form part of any VPX solution introduces a degree of complexity. Manufacturers are unlikely to re-qualify legacy modules and system components to the newer VITA 47 standard without additional cost so users may be willing to live with proven regimes until VITA 47 becomes universally accepted. 46 gefanuc.com VPX 47

25 In terms of product marketing collateral then the VPX logo illustrated in Figure 15 is meant to indicate compliance. However, it should be recognised that use of the VPX logo does not indicate that any formal compliance testing has been undertaken. The VPX logo is a trademark of VITA. Safety is of course a major concern and VPX mandates a ground connection in order to protect operators from possible exposure to electric shock. Remember the P0 utility connector allows high levels of power to be transferred to a VPX plug-in module and many applications now include the generation of high voltages. The safety ground is made more important by the ability to support two level maintenance and the consequent likelihood that powered equipment may be opened. Practically the board level alignment keys provide a mechanism to achieve a safety ground as they provide the required 20 ampere current carrying capability, low contact resistance (<100 milliohms) and a mate first, break last capability. Figure 15 The VPX logo 2.3 System level considerations The System section of the VPX standard defines functionality that does not properly belong in either plug-in module or backplane sections. Considering the most important features: Safety Ground The VPX standard also highlights elements of safety ground connectivity: Rule 3-1 states that plug-in modules shall not connect safety ground to signal ground. To any that have fought erratic behaviour caused by ground loops this may seem like common sense but hopefully the rule will reduce the number of future incidents. Rule 3-2 places a requirement on the chassis vendor, the backplane shall provide a separate terminal post for safety ground. Additionally this lug must be capable of carrying fault currents from plug-in modules and performance must be documented in the form SG = x where x is the aggregate rated concurrent current carrying capability. Observation 3-2 alerts designers to the need to consider the current carrying capacity of PCB designs. It is all too easy to sign off a net-list that includes a 20mA signal trace as a safety ground connection! All VPX plug-in modules are required to provide a safety ground connection, something not normally found as part of a COTS architecture. 48 gefanuc.com VPX 49

26 2.3.2 Power Supply Primary power In a VPX system primary power to plug-in modules is provided by one or more power contacts labelled Vs1, Vs2 and Vs3. It is important to note that only Vs3 (+5 Volts) is guaranteed to be present, the other two contacts may or may not be powered. This is not a new concept. Many VME integrators have invested time debugging an inoperative plug-in module only to find that an ancillary voltage rail, such as +12V, is not provided by the system PSU or backplane. If the VPX Vs1 and Vs2 voltages are provided they will be within the tolerances stated in the standard. beware though not all system designs will actually provide them! VPX Vs1 and Vs2 primary power definitions vary by form factor: 6 3U implementations employ a Vs1 of +12 Volts and a Vs2 of 3.3 Volts. 6 6U implementations use voltage levels of 48 Volts or 12 Volts, but not both. If not required a power input may also not be driven. As a result there are Vs1/Vs2 options: 48V power input, Vs1 shall be 48V and Vs2 48V Return 12V power input, both Vs1 and Vs2 shall be 12V Thus 6U form factor VPX plug-in modules must generate 3.3 Volts on board if they need it locally or for PMC/XMC supply. In addition the fact that the same connector contacts are used for different voltages means that keying options must protect plug-in modules. This in turn places a restriction on 3U/6U interoperability, the 3U form factor supports less keying options and 3U modules should not be installed in 6U systems. Auxiliary power VPX defines three auxiliary power inputs, 3.3V_AUX, +12V_AUX and -12V_AUX. These are of lower capacity than the primary power supplies, rated at only 1A per slot. In use the auxiliary power supplies are provided to accommodate system management functionality which might need to be operational even if the primary power rails are not available System Functions System Controller (SYS_CON) VPX supports the concept of a system controller responsible for the generation of several important system wide signals: REF_CLK+/-, SYSRESET*, NVMRO and potentially the System Management bus. This can be likened to the VMEbus slot 1 controller function although in practice it is somewhat less rigorous. Remember VPX communication tends to be by means of a network of point to point serial fabrics. As a result the system controller does not need to provide a centralised arbitration or interrupt control function. In mil/aero applications the concept of a system controller is important because it is the system controller that is normally responsible for managing system integrity. As such the system controller will normally be the BIT master responsible for the collection of system wide diagnostic data. A module is identified as the System Controller when its SYS_CON* pin is connected to ground on the backplane. SYS_CON* is located on the P1 connector. 50 gefanuc.com VPX 51

27 Reference Clock (REF_CLK+/-) The Reference Clock is a bussed differential pair that can be used to synchronise plug-in modules. Normally this signal will be generated by the System Controller. The most important use of the Reference Clock is to allow individual plug-in modules to implement Spread Spectrum Clocking (SSC). This is a technique that is used in many modern computing elements in to reduce their EMI signature. Put simply Spread Spectrum Clocking, or clock dithering, introduces a random function designed to spread the energy of clock harmonics into a band several megahertz wide. Thus, ordinarily, a system based upon a 2 Megahertz processor will tend to exhibit an EMI signature with a sharp peak centralised on 2 Megahertz. Spread Spectrum Clocking can be used to distribute these emissions over a wider frequency range, reducing their amplitude and therefore potentially bringing them below a critical limit. Without SSC the system may fail EMI compliance testing, with SSC the same system may pass Spread Spectrum Clocking is defined within the PCI Express environment. Looking more widely then the technique is also used in memory controllers and similar interfaces where large synchronous loads might exist. JTAG Pin Allocation (Optional) JTAG pin allocations illustrate the pragmatic approach taken by VPX designers. At the time no suitable open market standard existed for a multi-drop implementation of the Test Access Port and Boundary Scan Architecture, also known as JTAG, specified in IEEE or IEEE As a result the VPX standard allocates pins but no more. This leaves manufacturers open as to how they implement JTAG on plug-in modules but constrains them to a particular set of interface pins. As a result the standalone test fixtures that will be developed will at least show a degree of consistency. System Management connections (Optional feature) System Management functions are not included in ANSI/VITA but a set of four interface signal pins, SM[3:0], are reserved on the P0 connector for future use. Potentially these pins could be used for an Intelligent Platform Management Interface (IPMI) although in practice the market is making its own decision on this. Many boards currently implement a system management bus that is geared to supporting a system wide Built In Test (BIT) environment, a very useful role. Non-Volatile Memory Read Only (Optional feature) This optional system wide signal can be used to prevent non-volatile memory from being updated. Such a signal was not provided as part of the VMEbus standard and it is designed to serve two purposes: (i) event accidental, or destructive, updates to BOOT ROMS or similar precious local resources. (ii) By asserting NVMRO a designer can guarantee that any classified or sensitive data loaded into local memory is not copied to a non-volatile storage location. As a result the data will be lost when power is removed. SYSRESET* An open-collector signal driven by the system controller or another plug-in module in order to guarantee a clean start up. Note that VPX defines a minimum period of 10 milliseconds. VMEbus specified a 200 millisecond period and as a result hybrid VPX/VME backplanes have to incorporate a SYSRESET* pulse stretching function. 52 gefanuc.com VPX 53

28 Slot Type Indication Recognising that the use of VPX backplane connectors is under the control of separate protocol specifications, and the fact that regardless of use all connectors look the same, the VPX standard suggests the use of human readable slot indicators. The VPX standard also recommends that keying is used to differentiate slots where potentially destructive voltages or functions are present. 2.4 Common requirements Overview Section 4 of ANSI/VITA defines requirements that are common to both the 3U and 6U form factors. This includes the P0/P1 connectors, keying, Two Level Maintenance and the electrical characteristics of signals found on P0/P Connectors Wafer Type Row G Row F Row E Row D Row C Row B Row A 1 Power Vs1 Vs1 Vs1 No pad Vs2 Vs2 Vs2 2 Power Vs1 Vs1 Vs1 No pad Vs2 Vs2 Vs2 3 Power Vs3 Vs3 Vs3 No pad Vs3 Vs3 Vs3 4 Single-ended SM2 SM3 GND -12V_AUX GND SYSRE- NVMRO SET* 5 Single-ended GAP* GA4* GND 3.3V_AUX GND SM0 SM1 6 Single-ended GA3* GA2* GND +12V_AUX GND GA1* GA0* 7 Differential TCK GND TD0 TD1 GND TMS TRST* 8 Differential GND REF_CLK- REF_CLK+ GND RES_BUS- RES_BUS+ GND Table 6. P0 Utility Connector Table 6 identifies the three wafer types: Power, Single-ended, differential odd (wafer 7) and differential even (wafer 8). These are illustrated in Figures 16, 17, 18 and 19 respectively. In the VPX standard plug-in module rows (for P0) are denoted by an upper case designation, for example Row A, whereas backplane rows (for J0) are denoted by a lower case designation, for example Row a. Reference should be made to Figure 6 and section for details of VPX connector positions. As stated the P0 connector shall utilize an 8 wafer construction. This is actually made up of three wafer types: 6 Three power wafers in positions one, two and three 6 Three single ended 5 signal/2 ground style wafers in positions four, five and six 6 Two differential wafers in positions seven and eight 54 gefanuc.com VPX 55

29 Power Single-ended Figure 16 (single design) Figure 17 (single design, routine housekeeping functions) Differential Figure 18 Note how between figures 18 and 19 differential pairs and grounds alternate in order to isolate signal traces Differential Figure 19 Note how between figures 18 and 19 differential pairs and grounds alternate in order to isolate signal traces Table 7. VPX connector wafers Backpane Row i h g f e d c b a Backpane PWB GND hx gx GND ex GND cx bx GND Connector Wafer ix GND hx sig5 gx sig4 fx GND ex sig3 dx GND cx sig2 bx sig1 ax GND to bx to cx to ex to gx to hx A B C D E F G Plug-in Row Plug-in Module PWB Backpane Row i h g f e d c b a Backpane PWB ix hx gx fx ex dx cx bx ax Connector Wafer ix hx gx fx dx cx bx ax Pwr1 Pwr2 to a, b, dx to f, g, h, ix A B C D E F G Plug-in Row Plug-in Module PWB Figure 16. Power wafer to backplane pin mappings Row D on the plug-in module is designated as No pad. This simply means that the construction of the connector wafer is such that there is no circuit pad in this location. Figure 17. Single ended wafer mappings Backpane Row i h g f e d c b a Backpane PWB ix GND GND fx ex GND GND bx ax Connector Wafer ix Single Ended 1 hx GND gx GND fx Pair 2 ex dx GND cx GND bx Pair 1 ax A B C D E F G Plug-in Row Plug-in Module PWB to ax to bx to ex to fx Figure 18. Odd differential wafer mappings to hx Note how the odd differential wafer provides 2 differential pairs and one single ended connection. 56 gefanuc.com VPX 57

30 Backpane Row i h g f e d c b a Backpane PWB GND hx gx GND GND dx cx GND GND Connector Wafer ix GND hx Pair 2 gx fx GND ex GND dx Pair 1 cx bx GND ax GND A B C D E F G Plug-in Row Plug-in Module PWB to cx to d x to gx to hx Figure 19. Even differential wafer mappings Note how the even differential wafer provides two differential pairs but NO single ended connection, the G to i connection being a GND. As previously stated the plug-in module P1 connector is made up of 16 differential wafers and this is again common to both 3U and 6U form factors. The 16 wafers provide 32 differential pairs and 8 single ended connections as can be determined from Figures 18 and 19. For guidance Figure 20 provides Tyco part numbering for a 6U VPX assembly. 3U constitutes a sub-set of this. Note: being proprietary this data is not included in the VPX standard. Figure 20. VPX connector definitions (source: Tyco Electronics) 58 gefanuc.com VPX 59

31 2.4.3 Form Factors For mechanical outlines the VPX base specification points to IEEE and IEEE These standards provide both 3U and 6U plug-in module PCB dimensions but by definition can not detail VPX connectors or alignment block positions. Appendices to the VPX standard dimension 3U and 6U plug-in modules and all board level furniture Alignment and Keying As illustrated in Figure 20 the VPX alignment and keying methodology consists of a guide pin, located on the system backplane, and a receptacle, located on the plug-in module. For keying purposes the guide pin and inside hole of the receptacle can have a flat face that needs to be lined up. By adjusting the angle of this flat face it is possible to gain multiple keying options as illustrated in figure 21. Note that when the plug-in module mounted keying socket has no key, or in other words no restrictive internal flat edge, then it will slot over any backplane keying pin. Plug-in module mounted keying socket X 0o Keying socket, TYCO part number o Keying socket, TYCO part number o Keying socket, TYCO part number o Keying socket, TYCO part number o Keying socket, TYCO part number No key Keying socket, TYCO part number Backplane mounted alignment and keying pin X (9mm) O o 45 o 90 o 270 o 315 o No Key Figure 21. VITA 46 Keying system There are five allowed backplane keying pins: 0, 45, 90, 270 and 315 degrees. There are six allowed plug-in module keying socket options: No key, 0, 45, 90, 270 and 315 degrees. 60 gefanuc.com VPX 61

32 As previously noted a 3U form factor supports two alignment keys providing 25 unique key settings. A 6U form factor supports three alignment keys providing 125 unique key settings. In practice the number of key settings available is nowhere near large enough to cope with all possible fabric types, daughter card types and connector types. As a result ANSI/VITA defines only essential keying needed to prevent damage. A good example is keying to prevent a 12V Vs1/Vs2 plug-in module being inserted into a 48V Vs1/Vs2 backplane. Such a strategy leaves many keying options available for system integrators to use in order to differentiate slots in their system. The keying position adjacent to the P0 connector on both 6U and 3U form factors is referred to as position 1. The keying position adjacent to the P2 connector on both 6U and 3U form factors is referred to as position 2. The keying position adjacent to the P6 connector on the 6U form factor is referred to as position 3. To simplify system integration the VPX standard recommends that normal build, catalogue, 6U plug-in modules should be delivered with un-keyed sockets fitted at position 2 and position 3. Normal build, catalogue, 3U plug-in modules should be delivered with un-keyed sockets fitted in position 1 and position 2. The alignment key also provides a safety ground path between the plug-in module and an appropriate chassis ground Two Level Maintenance (optional feature) Two Level Maintenance (TLM) is a relatively new concept introduced by the US army to replace the 60 year old Four Level Maintenance process. Thus far Force XXI and Stryker Brigade Combat Team units have tested and proven the TLM concept effective. With TLM, field level engineers perform inspections, diagnose faults, and replace components on end platforms. Failed components are returned to a higher Sustainment level entity for repair. With a VPX product then this Sustainment level authority will normally include the original manufacturer able to complete an upgrade or repair. Adding a TLM capability to VPX requires both the ability to isolate faults and the ability to replace faulty modules in the field. Fault isolation is largely a module dependent function and it is very much up to individual manufacturers to provide adequate testability. Typically this will be achieved through a combination of Built In Test (BIT), detailed technical manuals and where appropriate supporting test gear perhaps making use of JTAG connectivity. Module replacement in the field implies both mechanical and ESD protection for plug-in modules. ANSI/VITA makes recommendations for meeting these requirements but points to VITA 48 (REDI) for full details of covers and ESD protection. Readers are also encouraged to reference VITA 47 for a definition of levels of electrostatic discharge resistance. It should be noted that the MultiGig RT2 connectors include an ESD protection. The VPX standard also recommends that plug-in modules include a red status indicator that can be illuminated by the module if a fault is detected. 62 gefanuc.com VPX 63

33 2.4.6 Geographical Addressing The P0 connector includes a definition of five Geographical Addressing signals GA[4:0]* that can be used for system wide slot identification. GA0* shall be the Least Significant Bit (LSB) and plug-in modules must be designed to use 3.3V signalling on these pins. There is also a parity signal (GAP*). The sum of grounded Geographical Addressing pins GA0*, GA1*, GA2*, GA3*, GA4* and GAP* shall be odd, equivalent to odd parity assuming that each grounded pin represents a logic 1. Slot 1 is defined as the leftmost slot when viewed from the plug in module insertion side with P0 at the top. Note that Geographical Addressing is a mandatory feature for both pure VITA 46 backplanes and hybrid backplanes including VME64 or CompactPCI slots. Table 8 provides Geographical Address pin assignments. Figure 22. Mechanical and ESD protection covers Figure 22 illustrates covers defined in VITA 48. Note that the inclusion of normally necessitates a move to a 0.85 slot spacing rather than 0.8. Slot GAP* GA4* GA3* GA2* GA1* GA0* 1 Open Open Open Open Open GND 2 Open Open Open Open GND Open 3 GND Open Open Open GND GND 4 Open Open Open GND Open Open 5 GND Open Open GND Open GND 6 GND Open Open GND GND Open 7 Open Open Open GND GND GND 64 gefanuc.com VPX 65

34 8 Open Open GND Open Open Open 9 GND Open GND Open Open GND 10 GND Open GND Open GND Open 11 Open Open GND Open GND GND 12 GND Open GND GND Open Open 13 Open Open GND GND Open GND 14 Open Open GND GND GND Open 15 GND Open GND GND GND GND 16 Open GND Open Open Open Open 17 GND GND Open Open Open GND 18 GND GND Open Open GND Open 19 Open GND Open Open GND GND 20 GND GND Open GND Open Open 21 Open GND Open Open GND GND Table 8. Geographical Address pin assignments P1 connector signals The P1 connector is loaded with sixteen differential wafers. As with the P0 connector (Table 6, wafers 7 and 8) these comprise of odd/even pairs building to provide 32 differential signal pairs and 8 single ended contacts. Table 9 defines the signal set identified by the VPX baseline standard. Figure 23 provides a block diagram of the SBC340. Figure 24, taken from the SBC340 product manual, provides an example of a genuine P1 connector pin out. This is a 3U implementation and it is important to note how differential pairs are used for serial fabric connectivity, SATA interfaces, Gigabit Ethernet and a number of other more general purpose connections. Signal Quantity Description P1-DP[31:0] 32 differential pairs Numbered P1-DP0-, P1-DP0+ and so on, typically to be used for fabric connections P1-RES_BUS_SE 1 single ended Reserved Future Use by VITA 46.0 Base Specification, Bussed P1-VBAT 1 single ended Battery Voltage, Bussed SYS_CON* 1 single ended Connected to ground on the backplane slot designated as the system controller P1-REF_CLK_SE 1 single ended Single Ended Reference clock to be used by subsidiary VITA 46 specifications P1-SE[7:4] 4 single ended Single-ended signals (user defined) Table 9. P1 connector signal set 66 gefanuc.com VPX 67

35 Core 2 Duo 2.16 GHz T7400 Figure 23 SBC340 block diagram A B C D E F G PCIE_ GND PCIE_ PCIE_ GND RXN1 TXP1 TXN1 1 PCIE_ RXP1 2 GND PCIE_ RXP2 3 PCIE_ RXP3 PCIE_ RXN3 4 GND PCIE_ RXP4 5 PEG_ RXP0 DDR2 SDRAM 1 Gb FlASH Disk BIoS 945GM (GMA 950) PEG_ RXN0 DDR2 SDRAM IDE ( ATA) FWH PCIE_ RXN2 GND PCIE_ RXN4 ICH7M GND PCIE_ TXP3 GND lpc x1 PCIe AUDIo SUPER I/o GIgEnet CoDEC PCIE_ TXP2 PCIE_ TXN3 PCIE_ TXP4 GND PEG_TXP0 PEG_ TXN0 PCIE_ TXN2 GND PCIE_ TXN4 GND x4 PCIe CoM 1,2 GPIo PS2 KBD & MoUSE SATA (2) USB2(4) 10/100/1000 BaseT x1 PCIe STEREo line out STEREo line IN RGB x16 PCIe No connection GND Back Plane No connection GND SYSCON~ 6 GND PEG_ RXP1 7 PEG_ RXP2 PEG_ RXN2 8 GND PEG_ RXP3 9 SATA0_ RXP SATA0_ RXN PEG_ RXN1 GND PEG_TXP1 PEG_ TXN1 GND PEG_TXP2 PEG_ TXN2 PEG_ RXN3 GND GND GND PEG_TXP3 PEG_ TXN3 SATA0_ TXP SATA0_ TXN GND GND No connection GND COM1_ TXD 10 GND USB_P0P USB_P0N GND USB_P1P USB_P1N GN 11 P5V_ USBP0 P5V_ USBP1 GND P5V_ USBP2 P5V_ USB3 GND COM1_ RXD 12 GND KDAT KCL GND MDAT MCLK GND 13 LPT0 LPT1 GND LPT2 LPT3 GND COM2_ TXD 14 GND LPT4 LPT5 GND LPT6 LPT7 GND 15 ETH_0P ETH_0N GND ETH_1P ETH_1N GND COM2_ RXD 16 GND ETH_2P ETH_2N GND ETH_3P ETH_3N GND Mnemonic GND PCIE_TXxx PCIE_RXxx PEG_TXxx PEG_RXxx SATAx_TXx Signal Description The DC voltage reference for the system PCIe lanes from the ICH7 - can be configured as 1x4 or 4x1 PCIe lanes to the ICH7 can be configured as 1x4 or 4x1 X16 PCIe transmit lines from 945 dedicated graphics interface X16 PCIe receive lines to 945 dedicated graphics interface SATA interface from SBC340 to external SATA device 68 gefanuc.com VPX 69

36 SATAx_RXx USB_Pxx P5V_USBPx KDAT KCLK MDAT MCLK LPT0 LPT7 ETH_xx COMx_TXD COMx_RXD SATA interface from external SATA device to SBC340 USB interface USB port power individually controlled PS2 keyboard data PS2 Keyboard clock PS2 mouse data PS2 mouse clock GPIO (not configurable as interrupts) Gigabit Ethernet connection Serial COM port Transmit Data Serial COM port Receive Data SYSCON~ System controller. When this signal is active low, this SBC340 generates the SYSRESET~ and NVMRO signals Figure 24 SBC340 P1 connector signal designations Both air cooled and conduction cooled formats define a PCB thickness of 1.6 mm with a primary side maximum component height of mm and a secondary side maximum component height of 4.06 mm. Figure 25. 3U air cooled module key dimensions 2.5 3U modules As previously stated VPX 3U modules preserve the 3U by 160 mm by 4HP dimensions used by IEEE , IEEE and VME64. Figure 25 provides key dimensions for an air cooled 3U module and Figure 26 key dimensions for a conduction cooled module. Full mechanical dimensions are given in the ANSI/VITA 46.0 VPX Baseline standard. Figure 26. 3U conduction cooled module key dimensions 70 gefanuc.com VPX 71

37 Table 10 highlights connectors utilised on a 3U module. Note that P2 provides options depending upon the protocol specification in use. P2 can be ALL differential or ALL single ended. Connector Description Capability P0 P1 P2 OR Table 10. 3U module connectors Left end module 8 wafers (mixed technology) right angle Centre module 16 differential wafers right angle Centre module 16 differential wafers right angle Centre module 16 single ended wafers right angle Power connections 2 differential pairs 17 single ended signals Use defined by ANSI/VITA differential pairs P1-DP0+, P1-DP0- etc 8 single ended signals 32 differential pairs P2-DP0+, P2-DP0- etc 8 single ended P2-SE0, P2-SE1 etc Typically used for high speed I/O, serial fabric connections or PMC/XMC I/O as defined in VITA single ended P2-SE00, P2-SE01 etc Typically used for parallel busses or general purpose I/O 2.6 6U modules As previously stated VPX 6U modules preserve the 6U by 160 mm by 4HP dimensions used by IEEE , IEEE and VME64. Figure 27 provides key dimensions for a 6U conduction cooled module. Full mechanical dimensions are given in the ANSI/VITA 46.0 VPX Baseline standard. The 3U module definition allows the possibility of fitting an application specific connector in position P2. This connector can be something other than the standard 7 row RT2. Figure 27. 6U conduction cooled module key dimensions 72 gefanuc.com VPX 73

38 Both air cooled and conduction cooled formats define a PCB thickness of 1.6 mm with a primary side maximum component height of mm and a secondary side maximum component height of 4.06 mm. Table 11 outlines 6U connector definitions. P2, P3, P4, P5 and P6 allow options depending upon the protocol specification in use. Connector Description Capability P0 P1 P2 OR Left end module 8 wafers (mixed technology) right angle Centre module 16 differential wafers right angle Centre module 16 differential wafers right angle Centre module 16 single ended wafers right angle Power connections 2 differential pairs 17 single ended signals Use defined by ANSI/VITA differential pairs P1-DP0+, P1-DP0- etc 8 single ended signals 32 differential pairs P2-DP0+, P2-DP0- etc 8 single ended P2-SE0, P2-SE1 etc Typically used for high speed I/O, serial fabric connections or PMC/XMC I/O as defined in VITA single ended P2-SE00, P2-SE01 etc Typically used for parallel busses or general purpose I/O P3 16 differential wafers See P2 definition Numbered P3-XXXX OR 16 single ended wafers See P2 definition Numbered P3-SE00, P3-SE01 etc P4 16 differential wafers See P2 definition Numbered P4-XXXX 16 single ended wafers See P2 definition Numbered P4-SE00, P4-SE01 etc P5 16 differential wafers See P2 definition Numbered P5-XXXX 16 single ended wafers See P2 definition Numbered P5-SE00, P5-SE01 etc P6 16 differential wafers See P2 definition Numbered P6-XXXX 16 single ended wafers See P2 definition Numbered P6-SE00, P6-SE01 etc Table 11. 6U module connectors The 6U module definition allows the possibility of fitting an application specific connector in position P6 or in positions P5 and P6. Connectors can be something other than the standard 7 row RT2. 74 gefanuc.com VPX 75

39 U Backplane Keying For 3U modules all backplane derived input voltages have dedicated pins. This is not so in the 6U case because Vs1 and Vs2 can be either 12V or 48V. Obviously the application of 48V to a 12V module is undesirable and potentially destructive! Key 1 (Figure 27) is referred to as the voltage keying pin on the 6U form factor. Table 12 defines the options. Please refer to Figure 21 for angle definitions. High Voltage Power Input Key 1 48V Angular position 45 or 90 12V Angular position 315 or 0 Table 12. High Voltage Power Input Key 1 options For the 6U case angular position 45 is the preferred option for 48V and 315 is the preferred option for 12V. Note that dedicating Key 1 to voltage keying means that for the 6U case standard slot keying can only use Key 2 and Key 3. Key 2 acts as the least significant bit. It is recommended that for slot 1 Key 2 is set to angle 270 and key 3 is also set to angle 270. The sequence of angles is 270, 315, 0, 45, 90 as defined in Table 13. Note that the sequence identified in Table 13 will only continue for as many slots as there are in the backplane. SLOT Key 3 angle Key 2 angle Table 13. 6U case slot keying 76 gefanuc.com VPX 77

40 2.7 VPX backplanes Hybrid Backplanes The ANSI/VITA 46.0 VPX Baseline Standard provides mechanical dimensions for both 3U and 6U backplanes. Note that backplane connectors are numbered J0, J1, J2 and so on. All VPX backplanes implement geographic addressing slots are numbered with SLOT 1 being defined as the leftmost slot when viewed from the plug in module insertion side with P0 at the top. The six geographical addressing pins (GA0*, GA1*, GA2*, GA3*, GA4* and GAP*) on the J0 connector are either tied to ground on the backplane or left open (floating). With regard to the parity signal (GAP*) then the sum of grounded Geographical Addressing pins GA0*, GA1*, GA2*, GA3*, GA4* and GAP* shall be odd, equivalent to odd parity assuming that each grounded pin represents a logic 1. Table 8 provides Geographical Address pin assignments. The ANSI/VITA 46.0 VPX Baseline Standard does not require that all slots in the backplane be compliant. A hybrid backplane is defined as a backplane which has slots that are VPX compliant and slots which are compliant with another standard such as VME64. One implication of combining technologies is that this could result in multiple system controllers. For example, in the case of a VPX/VME64 hybrid backplane there will be a VPX system controller and a separate system controller for the VME64 segment(s). Key signals may also have to translate between each backplane technology. An example of this is the open collector SYSRESET* signal that must be bussed across all slots. As the VMEbus system reset has a minimum period that is longer than the VPX signal it must be recognised that a VPX module inserted into a hybrid VPX/VME64 backplane may be held in reset for a longer period after power up than it would in a pure VPX backplane Geographical addressing applies to ALL VPX backplanes: Figure 29 illustrates a potential hybrid backplane configuration. 6 VPX backplanes with only VITA46 slots 6 Hybrid backplanes with either VME64 or CompactPCI legacy segments 6 Hybrid backplanes with legacy slots on either side of VITA46 slots or interspersed amongst them V M E64 VXS VPX Figure 28. A 9 slot 3U VPX backplane Figure 29. A conceptual VPX/VXS/VME64 hybrid backplane 78 gefanuc.com VPX 79

41 Practically it is reasonable to expect that hybrid architectures will have a role for many years to come due to the vast quantity of legacy VME64 and CompactPCI boards currently in use. Indeed hybrid backplanes are a fundamental part of the VPX philosophy so that designers and integrators are not forced to re-invent the wheel by migrating a perfectly viable design from a VME to a VPX form factor, for example. It is perfectly acceptable to stay with an existing, qualified, interface card and simply to bridge to it from a suitable VPX module. Board 1 Legacy VME Card Board 2 PEX440 Carrier Card Board 3 SBC610 SBC Board 4 DSP230 Multiprocessor Figure 30 illustrates the SBC610 which can be used in such a VPX/VME configuration. Figure 31suggests how this might be used in an Axis MultiComputer. VME srio PCIe Express SRIO Switch PCI/PCIe Switch FABRIC MUX COM 1,2 (P4) P0 P1 Power & Utility I/O 4x4 Fabric (PCI Express or srio) x8 XMC Front IO NVRAM Flash PCIe Switch PCI/PCIe Bridge FPGA VME SATAx2 (P4) SATA USBx2 (P4) USB RS232/422/485x4 (P6) P2 P3 VME PMC/XMC I/O 2 XMC/PMC sites Figure 31. VPX bridging to VME in an Axis MultiComputer 1 Processor 2 XMC/PMC sites 4 Processors 1 XMC site 8641 PCI/PCIe Bridge AFIX I/O (P6) AFIX Site GPIO (P6) Gig Ethernet x2 (P4) P4 XMC I/O, Gigabit Ethernet, Board I/O Up to 1GByte DDR2 SDRAM Up to 1GByte DDR2 SDRAM PCI/PCIe Bridge PCI/PCIe Bridge XMC/PMC Site XMC/PMC Site P3/4 P5/6 P5 P6 PMC/XMC I/O XMC I/O & Board I/O Figure 30. SBC610 VPX module with VME interface 80 gefanuc.com VPX 81

42 Section Three VPX application 82 gefanuc.com VPX 83

43 VPX application 3.1 Example architectures Serial fabrics offer point to point communication. In addition the number of fabric lanes employed determines the maximum available bandwidth between two modules. Taken together these two facts mean that the way that VPX modules are connected together can largely determine the functionality and performance of the completed architecture. Figure 32 identifies an architecture optimised for graphics performance. Such an architecture is typically utilised in an embedded training or cockpit display application. Fundamental to the architecture illustrated in Figure 32 is the provision of 16 PCIe lanes between either the SBC340 Intel based SBC or the SBC330 Freescale PowerPC based SBC and the GRA110 Graphics Processing Unit. This X16 connection can support data transfer rates of up to 4 GBytes/second/direction. Of lesser importance in terms of data bandwidth is data I/O from the PEX430 PMC/XMC carrier and this is therefore allocated a X4 link. Such a X4 link supports up to 1 Gbyte/second/direction. 84 gefanuc.com VPX 85

44 x4 Backplane x4 Backplane x16 SATA x4 x4 SATA SBC GPU PMC/XMC Carrier Card & Switch SATA Disk SBC SBC SBC SATA Disk SBC340/SBC330 GRA110 PEX430 SDD910 SBC320 SBC320 SBC320 SDD910 Figure 32. A VPX graphics architecture Figure 33. A VPX processing architecture A more balanced, processing, architecture is illustrated in Figure 33. Here each SBC is able to connect to the each and every other SBCs by means of a dedicated x4 PCIe link. Note that if another SBC were to be introduced into this architecture and such dedicated linking were still to be required then this would necessitate the inclusion of a PCIe switch as each SBC only has two x4 PCIe ports available. In reality a practical VPX architecture will combine graphics, processing and other architectural elements according to application requirements. Figure 34 illustrates a genuine VPX architecture corresponding to the backplane illustrated in Figure 28. This configuration supported the needs of an embedded training application. Figure 35 shows the rugged 1/2ATR chassis used in the application. 86 gefanuc.com VPX 87

45 The architecture illustrated in Figure 34 includes a graphics element spread across slots 1, 2 and 3. Here the Graphics Processing Unit located in slot 2 needs to drive two high performance graphics screens and as a result a x16 link is required. The Graphics Processing Unit located in slot 3 drives two lower performance screens and as a result a x4 link is sufficient. I/O through slot 4 can be handled by a x1 link but needs to route to either the SBC in slot 1 or the SBC in slot 8 according to function. Figure 35. A compact, rugged, nine slot VPX chassis for 3U boards Slot 5 provides mass storage for the embedded training application. Note also that in the initial build slots 6, 7 and 9 were reserved for future growth and as a result were unpopulated. SATA x1 x4 x16 SATA x1 x4 Backplane SATA 3.2 Development environments Any deployed VPX architecture will normally be the result of a development process and will normally include an application dependent set of linked serial fabrics optimised for that particular application and embodied in a bespoke backplane. This poses the obvious question, how can the development process evaluate and benchmark different configurations in order to define the optimum configuration? Clearly financial and time constraints will normally exclude the generation of a unique backplane for each possible configuration. To counter this high speed fabrics also need the impedance matched, high quality, signal traces that can most easily be incorporated into a backplane. SDD910 SDD910 SBC340 GRA110 GRA110 PEX430 SDD910 spare spare SBC430 spare Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Figure 34. A nine slot VPX architecture One solution is to employ a patch panel arrangement with serial fabrics being routed through cables and simply swapped in order to replicate desired connectivity models. Such a technique can employ cabling appropriate to the fabric concerned, cabling that is readily available on the open market. Figure 36 illustrates a 3U VPX plug in module, the SBC320, and its associated Rear Transition module, the VPX3UX gefanuc.com VPX 89

46 The VPX3UX provides two x4 PCIe connectors in order to allow the two x4 PCIe ports from the SBC320 to be connected to external cables. Figure 37 provides a block diagram of the combination in order to illustrate this functionality. VPX3UX Serial (2) Backplane Note that the VPX3UX is actually a 6U high RTM in order to provide space for industry standard connectors. Figure 38 illustrates a development chassis that can support the VPX3UX and similar Rear Transition modules. Note that this chassis illustrates a 6U case, comparable RTM techniques can be used for both 3U and 6U VPX plug in modules. SBC 320 3U VPX Single Board Computer based upon Intel CORE 2 Duo Serial (2) SATA (2) Ethernet (2) X4 PCIe X4 PCIe USB (2) SATA (2) Ethernet (2) PMC I/O X4 PCIe PMC I/O X4 PCIe PMC USB (2) Figure 37. VPX3UX Rear Transition Module block diagram PCIe Figure 36. The SBC320 and its VPX3UX Rear Transition Module Front VPX plug in module slots Rear 6U Rear Transition Module slots Figure 38. A VPX development chassis with rear 6U RTM slots 90 gefanuc.com VPX 91

47 3.3 Dot standards VPX dot standards supplement the ANSI/VITA Baseline Standard by providing additional protocol layer standards that can be applied to the underlying VPX architecture. The rationale behind this is the fact that VPX has been designed to be flexible. It can be utilised in many different ways. Standardising protocol layer implementations from the outset provides designers with expert opinion on implementation and promotes interoperability. The objective of this chapter is to provide background information and guidance on the application of each dot specification. As such this information is intended to support intelligent reading of data sheets and product manuals. Designers are encouraged to make reference to the appropriate standard having digested this introductory text ANSI/VITA , VMEbus signal mapping Ratified in 2007 this dot standard maps the VMEbus signal set onto VITA 46 connectors and defines appropriate nomenclature. Power Single Ended Ground Differental Pair PO P1 Differential P2 Single Ended VMEbus signals mapped as defined ANSI/VITA Both 3U and 6U form factors are considered. For the 3U case then VMEbus A24:D16 operation is supported through a single ended P2 connector. The P0 Utility connector is of mixed technology as defined in Table 6 while a differential P1 connector is mandated. This is illustrated in Figure 39. Figure 39. 3U form factor VMEbus signal mapping For the 6U case there are two options. VMEbus A24:D16 operation can be supported through a single ended P2 connector as it was for the 3U case. Again Figure 39 applies although for the 6U case additional connectors must be considered. P1, P3, P4, P5 and P6 are defined as using differential connectors even though they are not used for VMEbus signalling. VMEbus A32:D32 operation can be supported through the use of multiple connectors 92 gefanuc.com VPX 93

48 as identified in Figure 11, VPX and VMEbus. Again a single ended P2 connector provides fundamental A24:D16 support. P3, P4 and P5 use a differential connector and map the remaining VMEbus signals required to support 32 bit working. P6 is again defined as using a differential connector although it does not carry any VMEbus signals. ANSI/VITA 46.1 introduces the concept of a homogenous backplane defined as a backplane in which all slots connect to the VMEbus. In other words all slots are ANSI/VITA 46.1 compliant. The standard also identifies a naming convention: O46.1-<n>S-<z>U Where: <n> is the number of slots in the backplane <z> is either 3 for 3U or 6 for 6U For example: S-6U identifies a 6U backplane with 8 slots each connected as defined in ANSI/VITA 46.1 For example: Y46.1-8S-3:2-6U identifies a 6U backplane with 8 slots of which 3 are pure VMEbus, 2 are VITA46.1 slots and 3 slots have no VITA46.1 connections. Figure 40 illustrates the Y46.1-8S-3:2-6U backplane. VMEbus VITA46.1 } }VME64X ANSI/VITA 46.1 also considers hybrid VME64x/VITA46.1 backplanes and defines a naming convention: Y46.1-<n>S-<x>:<y>-<z>U Where: <n> is the number of slots in the backplane <x> is the number of VMEbus slots <y> is the number of ANSI/VITA46.1 slots <z> is either 3 for 3U or 6 for 6U Figure 40. Y46.1-8S-3:2-6U hybrid backplane 94 gefanuc.com VPX 95

49 VITA46.1 application In the Mil/COTS arena VMEbus has been the dominant standard for many years. As a result it is likely that hybrid VPX/VME architectures will be relatively common because of the need to incorporate legacy modules and sub-systems. To support this VPX/VME enabled Single Board Computers will form the backbone of many product ranges. The SBC610 illustrated in Figure 41 is one such example providing VMEbus support alongside VPX. It should also be appreciated that manufacturers such as GE Fanuc Intelligent Platforms have committed to long term support of the VMEbus architecture. As a result it is likely that for many years to come parallel developments will result in comparable VMEbus and VPX products. Figure 41 illustrates the PPC9A (VMEbus) alongside the SBC610 (VPX). These two products share a similar on board architecture with the exception of VPX interfacing. Such a parallel product strategy offers two benefits: 6 Integrators can deploy the latest technology into new or upgraded VMEbus applications. Remember VPX provides new COTS capabilities; it has not been designed to replace VMEbus (Figure 12). 6 At a suitable point, and if appropriate, it becomes easier to transition from VMEbus to VPX because there will be few software implications. Sil3152 SATA NVRAM FLASH 4x RS232/422/485 33M GPIO AFIX VME (Tsi148) Bus Ctrl FPGA I/O FPGA Register FPGA 2eSST VMEbus USB 133M PEX8114 PLX E-X Br PEX8114 PLX E-X Br 2x USB2 2x RS232 SODIMM 2x 10/100/1000BASE-T 4X 4X 8641D PEX8548 PCI-e Switch 48 Lanes SODIMM 8X 8X 8X AFIX I/O 2x SATA-150 PMC/ XMC 1 133M Max PEX8114 PLX E-X Br 4X 4X PEX8114 PLX E-X Br 133M Max PMC/ XMC 2 Figure 41 PPC9A and SBC610 Single Board Computer architectures 96 gefanuc.com VPX 97

50 3.3.2 VITA 46.3 Serial RapidIO on VPX Fabric Connector At the time of writing this standard was at an advanced draft stage - Working group Draft release 0.5. This overview provides an insight into the current draft. Sil3152 SATA NVRAM FLASH 4x RS232/422/485 33M GPIO AFIX VME (Tsi148) Bus Ctrl FPGA I/O FPGA Register FPGA 2eSST VMEbus USB 133M PEX8114 PLX E-X Br PEX8114 PLX E-X Br 2x USB2 2x RS232 SODIMM 2x 10/100/1000BASE-T 4X 4X 8641D PEX8548 PCI-e Switch 48 Lanes SODIMM 8X 8X 4X Tsi578 SRIO Switch PEX lane Switch 2 off 4x SRIO VPX Fabric Mux 2 off 4x SRIO / PCIe The intention is for the VITA 46.3 standard to define Serial RapidIO protocol pin mappings to a differential ANSI/VITA P1 connector. The mappings will be the same for 3U and 6U plug in modules. VITA 46.3 will allow for up to four Serial RapidIO links to be assigned to the P1 connector. These will be termed Port A (PA), Port B (PB), Port C (PC) and Port D (PD). The draft standard defines the order in which Links are populated and this is given in Table 14. Number of Plug-In Ports Used Module Supported Links 1 Port A 2 Port A and Port B 3 Port A, Port B, and Port C AFIX I/O 2x SATA-150 PMC/ XMC 1 133M Max 8X PEX8114 PLX E-X Br 4X 4X 8X PEX8114 PLX E-X Br 133M Max PMC/ XMC 2 4 Port A, Port B, Port C, and Port D Table 14. Serial RapidIO P1 connector link population Four ports allow five payload slots to be directly connected to each other. This is illustrated in Figure 42. A greater number of plug in module payload slots will require the use of a Serial RapidIO switch. By VITA 46.3 allowed Serial RapidIO transmission rates are 1.25, 2.5, or Gbaud, corresponding to data rates of 1.0, 2.0, or 2.5 Gbps per lane. Each serial link supports interface modes of 1x or 1x/4x. 98 gefanuc.com VPX 99

51 Payload Slot 1 Payload Slot 2 Payload Slot 3 Payload Slot 4 Payload Slot 5 Payload Slot VITA46.3 application Serial RapidIO terminology defines the source or receiving port on a payload slot as an END POINT. Switches are used to pass packets between ports without interpreting them. This architectural form is illustrated in Figure 43. Payload Slot 5 Payload Slot 2 DRAM CPU End point End point port 2 port 2 P1 P1 P1 P1 P1 Payload Slot 4 Payload Slot 3 Backplate view MESH connectivity End point Switch Switch port 3 port 3 port 1 End point Figure 42. Five payload slots connected together port 0 port 0 End point End point ROM Figure 43. Generic Serial RapidIO architecture Source gefanuc.com VPX 101

52 Serial RapidIO supports several key operational features: 6 High performance. 8B/10B encoded data on 3.125Gbps serial fabric lanes giving a data bandwidth of 2.5Gb/s per lane (aggregated bandwidth of up to 10Gbps in a x4 srio link) 6 Small packet capability. Big-endian, 8 to 256 bytes, smaller packets decrease latency 6 Memory mapping 6 Mailbox queues 6 Doorbell interrupts 6 Device synchronization 6 Support for multiple transaction types such as NREAD (read operation data returned is the response), NWRITE (write operation, no response), NWRITE_R (robust write with response from the target end-point), SWRITE (streaming write), ATOMIC (atomic readmodify-write), MAINTENANCE (system discovery, exploration, initialization, configuration and maintenance operations) 6 ardware Multicast capabilities for improved distributed processing performance (note replication of a single packet so that it can be received by multiple end points is performed by switches rather than end points themselves) 6 Efficient, scalable protocol. Chip to chip, card to card, chassis to chassis Figure 44 illustrates the DSP230, a 6U VPX module incorporating extensive Serial RapidIO connectivity. Figure 45 provides a block diagram of the DSP230 and this should be considered in conjunction with Figure 44. As might be expected the DSP230 employs a number of interfaces other than the core signal processing Serial RapidIO based infrastructure. Most notable of these are PCIe (typically used for data acquisition) and Ethernet (data acquisition and command line interchanges). In order to enable signal processing environments to be put together quickly the DSP230 is fully supported by AXIS, a performance-optimized software environment designed to accelerate the development of complex signal processing applications requiring implementation across multiple processors. In addition to the math libraries that might be expected AXIS also provides full fabric connectivity models allowing the simulation of candidate topologies. In order to connect multiple DSP230 modules together GE Fanuc Intelligent Platforms provides the CRX800. This is a 22 port Serial RapidIO switch that includes a fibre optic connection capability. These features make Serial RapidIO ideally suited for use in a multiprocessing environment where each processor works in conjunction with other nodes to achieve a specific task. A good example of this is a multiprocessor array tasked with radar signal processing. Serial RapidIO provides the end to end connectivity associated with a genuine communications architecture. Previously designs were forced to use multiple data transport mechanisms to route data through a system and in such asymmetric environments a different software driver was normally required for each leg of the journey. This was a complex and less efficient process. 102 gefanuc.com VPX 103

53 1 x8 PCIe Port P0 P1 Power, Utility & I2C 4 x4 Serial RapidIO SDRAM SDRAM Processor XMC Processor SDRAM SDRAM P2 1 x8 or 2 x4 PCIe ports XMC Front I/O P3 VITA46 XMC Pn6 /O Flash Flash Switch FPGA, GbE, PCIe, srio, I 2 C P4 XMC Pn6 & Pn4 I/O & 2 x GbE ports SDRAM SDRAM P5 P6 XMC Pn4 I/O & 16 GPIO to FPGA Multi-board sync & 4 xrs xrs232/422 SDRAM Processor Processor SDRAM Figure 44. DSP230, a 6U VPX module with Serial RapidIO Serial, GbE & XMC I/O P6 XMC I/O P5 GbE, XMC & GPIO P4 XMC I/O P3 PCIe P2 srio & AXIS P1 Power & Utility P0 Figure 45. DSP230 block diagram 104 gefanuc.com VPX 105

54 3.3.3 VITA 46.4 PCI Express on VPX Fabric Connector At the time of writing this standard was at an advanced draft stage - Working group Draft release This overview provides an insight into the current draft. The objective of VITA 46.4 is to assign mappings for 16 PCI Express Lanes over a differential P1 connector as defined in VITA This is similar to the VITA 46.3 Serial RapidiIO objective stated in section which also used P1 for fabric connections. Power Single Ended Ground Differental Pair PO VITA 46.4 uses the same mappings for both 3U and 6U plug in module form factors. In addition the 16 PCI Express lanes can be utilised as sixteen x1 links, four x4 links, two x8 links or one x16 link. Note the distinction between Links and Lanes. By VITA 46.4 a Link can take 1, 4, 8 or 16 Lanes. This is illustrated in Figure 46. There are two special conditions which detail options when not all PCI Express lanes are used: (i) On 3U or 6U plug in modules unused PCI Express Links mapped onto P1 wafers 9 to 16 may be replaced with an alternative Link as defined in another VITA46 substandard. (ii) On 3U plug in modules unused PCI Express Links mapped onto P1 wafers 9 to 16 may be replaced by user I/O signals. P1 Differental Pair 16 PCIe lanes L0, L1, L2...L15 P2, P3, P4, P5 and P6 mapped as VITA 46.0 Figure 46. VITA 46.4 PCI Express through the VPX P1 connector x1 or x4 0r x8 or x gefanuc.com VPX 107

55 VITA46.4 application In role PCI Express is often utilised for I/O connectivity, it is a very effective data pipe able to stream data peripheral to host. The SBC310 3U VPX Single Board Computer illustrated in Figure 47 provides two x4 PCIe links specifically for I/O. 256 MB Flash 128 KB NVRAM EPLD To understand the benefits of using PCI Express consider a high speed data acquisition card linked to a host processor and used in a Software Defined Radio (SDR) application. Previous architectures tended to use PCI to transport data between the acquisition card and the host. Such solutions have been deployed but need careful implementation for two key reason: 6 Firstly PCI bandwidth limits throughput and often requires Digital Down Conversion to be done at the receiver. Due to this frequency bands of interest often have to be preselected in order to reduce the volume of data that needs to be transported. 6 Secondly PCI block transfers used to transport data require data to be split into 32 or 64 bit elements and then further encapsulated into blocks. These blocks may not then arrive at the host contiguously as the shared PCI bus may be required to interleave data samples with other traffic. 512 MB DDR2 512 MB DDR2 8641D PowerPC PCIe Switch SATA GPIO COM 1, 2 10/100/1000 BaseT x2 x4 PCIe x4 PCIe SATA x1 USB x2 Switching to lanes of PCIe solves these problems. Firstly the vast data bandwidth increase means that raw SDR data can be downloaded to the host processor and this host processor can then more easily soft-select regions of interest and/or record the full data stream as required. Indeed such raw data distribution can be used to support genuine distributed processing. PCIe/PCIx Switch USB or Secondly PCIe streams data through a dedicated pipe. There is no need to resort to a packetized data transport mechanism and end-to-end data flow is consistent. Figure 47. SBC310 Single Board Computer with PCIe connection 108 gefanuc.com VPX 109

56 PCIe Endpoints and Root Complex Three types of device exist in a PCIe system, Root Complexes, PCIe switches and Endpoints. Only one Root Complex exists in a PCIe tree. A Root Complex is a processor sub-system that includes one PCIe port, one or more CPUs with associated memory and other interconnect functions. Figure 48 illustrates such a generic PCI Express architecture. By far the most common usage model for PCIe is to connect a single Root Complex to dedicated I/O devices. Figure 32 illustrated such a relationship with the SBC340 acting as the Root Complex and the GRA110 acting as the Endpoint. In this model data transfer is predominantly from CPU to I/O device or I/O device to CPU. There is little data transfer between I/O devices. Root Complex CPU Graphics Root Complex Memory Local Domain UP DP Processor Switch UP DP Endpoint processor UP DP Endpoint processor Switch UP DP Switch Switch Endpoint Endpoint DP DP DP Endpoint Endpoint UP: Upstream port DP:Downstream Endpoint Endpoint Figure 48. A generic PCI Express architecture Endpoint Figure 49. PCIe Endpoint processors In a VPX system architecture there may be a need for multiple sub-systems to co-exist. In other words there could be several CPUs and I/O devices. In this case there will still be a single system level Root Complex but there could be one or more Endpoint processors. Indeed some of these 110 gefanuc.com VPX 111

57 system domain Endpoint processors may be the Root Complex for local domains in order to isolate address space between the local and system domains. This is illustrated in Figure 49. User Flash USB EEPROM 2 kbits ETI BMM Temp Sensor Also introduced in Figure 49 is the concept of a downstream port from the device closer to Root Complex. This links to the upstream port of a device lower in the tree. Firmware Hub LPC x4 2x Gb Ethernet 10/100/1000 BaseT SATA In order to be able to use a VPX plug in module as an Endpoint processor then the plug in module must have the ability to act as an Endpoint. To illustrate this the SBC340 illustrated in Figure 32 is acting as a Root Complex. However it can t act as an Endpoint. As a result if it became necessary to for two SBC340 modules to communicate with each other through PCIe then this would have to be done through a switch. This was illustrated in Figure 34 where the SBC340 in slot 1 connected to the SBC340 in slot 8 through the PEX430 switch in slot 4. NVRAM DDR2 SDRAM Core 2 Duo 3100 x4 PCIe Switch x4 PCIe/PCIx Switch USB 1,2 GPIO COM 1, 2 x4 PCIe x4 PCIe The inclusion of a dedicated switch can be an overhead. In the case of the embedded training solution illustrated in Figure 34 this was not the case. The PEX430 provides additional functionality acting as a PMC carrier and hosting a PMC I/O module required by the application. Some plug in modules have the ability to act as a Root Complex or an Endpoint and these can be connected directly without a switch. Figure 50 provides a block diagram of the SBC320 which can act as both Root Complex or Endpoint. Figure 50. SBC320 which can act as Root Complex or Endpoint Comparing Figure 50, the SBC320, with Figure 23, the block diagram of the SBC340, then the key difference is that the SBC320 provides an on board PCIe switching element. A similar distinction can be drawn between other products that use PCIe for interconnection. It should be noted that an inability to support both Root Complex and Endpoint working is not a failure of the product. Integrators have to understand the rationale behind a products design. In the case of the SBC340 then this is optimised for performance, typically being linked to a graphics accelerator such as the GRA110 through a x16 PCIe link. The SBC 320 is a general purpose Single Board Computer designed to maximise flexibility and connectivity. The SBC320 can connect to the GRA110 through a x4 link but it can support a PMC module and many other I/O functions. 112 gefanuc.com VPX 113

58 3.3.4 VITA 46.7 Ethernet on VPX Fabric Connector At the time of writing this standard was at an advanced draft stage - Working group Draft release This overview provides an insight into the current draft. The objective of VITA 46.7 is to assign 1000Base-KX/10GBase-KX4 Ethernet links to the ANSI/VITA VPX P1 connector. VITA46.7 also provides rules and recommendations for the use of these Ethernet links. Power Single Ended Ground Differental Pair PO Ethernet A Pin assignments are the same for 3U and 6U plug in modules and channel mappings are illustrated in Figure 51. Note that the single ended connections are not part of the VITA 46.7 definition and are reserved for use by VITA Again special dispensation is given to 3U modules in that they can use wafers 9 through to 16 (Ethernet C/D) for VITA 46.9 (PMC/XMC signal mapping). A plug in module shall provide a minimum of one Ethernet link, Link A. If two Ethernet links are provided then these shall be Link A and B. Three links Ethernet A, B and C. Four links Ethernet A, B, C and D. P1 Differental Pair Up to 4 Ethernet links P2, P3, P4, P5 and P6 mapped as VITA 46.0 Ethernet B Ethernet C Ethernet D Figure 51. VITA 46.7 Ethernet mapping VITA 46.9 PMC/XMC signal mapping At the time of writing this standard was at an advanced draft stage - Working group Draft release 0.7. This overview provides an insight into the current draft. 114 gefanuc.com VPX 115

59 There are many possible combinations of 3U and 6U VITA 46 modules supporting single or dual width PMC and/or XMC mezzanines and VITA 46.9 focuses on only the combinations most likely to be implemented. As such these should be considered as the standard COTS options: 6 PMC Jn4 I/O routed to 3U VPX P2 differential or single ended connector 6 XMC Jn6 I/O routed to 3U VPX P2 differential connector 6 PMC Jn4 I/O routed to 6U VPX P3, 5 differential connectors 6 XMC Jn6 I/O routed to 6U VPX P3, 4, 5, 6 differential connectors Vita 46.9 first describes signal mapping patterns and then goes on to define instances of these patterns across the VPX connector and PMC/XMC combinations that can be found on the 3U and 6U VPX form factors. P64ss This pattern maps all 64 contacts of PMC-Jn4 to VPX single ended wafers. GEb This pattern maps 4 differential pairs into a standard mapping for bidirectional PHY gigabit ethernet (1000Base-T) or 10 gigabit ethernet (10GBase-T) signals to two wafers of the VPX plug-in connector. GEx This pattern maps 4 differential pairs into a standard mapping for two independent TX/RX PHY gigabit ethernet link (1000Base-CX, 1000Base-KX) signals to two wafers of the VPX plug-in connector. Four wafers may be combined to provide four lanes of one link for 10GBase-CX4 or 10GBase-KX4. Table 15. VITA 46.9 mapping patterns Table 15 lists the signal patterns and Figure 52 illustrates these diagrammatically Pattern P64s Pattern X12d Pattern X20d24s Pattern P64s X12d X20d24s X20d38s Description This pattern maps all 64 contacts of PMC-Jn4 to VPX differential wafers. This pattern maps 12 selected differential pairs of XMC-Jn6 to VPX differential wafers. This pattern maps all 20 differential pairs of XMC-Jn6 and 24 single ended pairs to VPX differential wafers. This pattern fits within one VPX connector. This pattern maps the entire XMC connector to VPX differential wafers. This consists of all 20 differential pairs of XMC-Jn6 and all 38 single ended signals. Note that this mapping spans 2 VPX connectors. PMC Jn4 64 single ended Pattern X20d38s XMC Jn6 38 single ended 20 diff pairs V46 -Px differential V46 -Px/y differential XMC Jn6 12 diff pairs Pattern P64ss PMC Jn4 64 single ended V46 -Px differential Figure 52. VITA 46.9 mapping patterns V46-Px single ended XMC Jn6 24 single ended 20 diff pairs Pattern GEb Gigabit Ethernet bidirectional PHY Pattern GEx V46 -Px differential Gigabit Ethernet independent TX/RX PHY odd even odd even 116 gefanuc.com VPX 117

60 Reference to VITA 46.9 will provide a complete understanding of the detailed signal mappings and how the pattern definitions simplify definitions. To illustrate the principle consider a 3U VPX card with a PMC site. 64 I/O signals are mapped between the PMC J14 connector and the host s P2 VPX connector. These are single ended, a P64s pattern. This is termed a P2-P64s mapping as illustrated in figure 53. Similarly from an XMC the mapping P2-X20d24s provides 20 differential and 24 single ended connections between J16 and P VITA Rear Transition module for VPX At the time of writing this standard is at an advanced draft stage - Working group Draft release 0.6. This overview provides an insight into the current draft. The objective of VITA is to define 6U and 3U Eurocard format Rear Transition Modules (RTM) for use in an air-cooled racking system. The standard also makes provision for power and I/O connections for RTMs. PMC P0 Figure 54 illustrates connector definitions for the 3U case. For 6U boards then backplane J3 is paired with RJ3, J4 with RJ4, J5 with RJ5 and J6 with RJ6. J11 J12 P1 J13 64 single ended P64s P2 J14 Figure 53. P2-P64s mapping Figure 54. 3U VPX Rear Transition Module connector definition 118 gefanuc.com VPX 119

61 With reference to Figure 54 then J0 is an 8 column connector, RJ0 is a 16 column connector less one column of contacts adjacent to the alignment pin. If only J0 connections are used by the RTM then RJ0 has only 7 of its 16 columns wired. If both J0 and J1 are used by the RTM then RJ0 has all of its 15 columns wired. The same applies for RJ1 with regard to its connection of J1 and J2 signals. To understand the rationale behind this two things need to be understood: (i) VPX connector spills do not pass through the backplane completely in the way that VMEbus or CompactPCI connectors do. As a result a VPX connector has to be fitted from each side of the backplane. In the case of VME, for example, an RTM simply attaches to the long spills of J1 and/or J2 connectors. (ii) VITA uses the same connector shells as VITA Contact populations are changed though to fit the rear to front fitment. The fact that wafers are not symmetrical within each shell (odd/even) cause the unusual J0 to RJ0 arrangement. Section Four Future Enhancements The user is prompted to take extra care with RTM connector pin numbering. Because the Jx and RJx use the same connector shell, one inserted from the front of the backplane the other from the rear, then column 1 on the front connects to column 16 on the rear. VPX RTMs use the IEEE outline but with a depth of 81.5mm for both 3U and 6U formats. IEEE defines an 80mm standard depth. Signal mapping between the main VPX card and the VPX RTM is complex. Appendix B highlights pin assignments for the Px, Jx, RJ, RPx transistion for a 3U core. 120 gefanuc.com VPX 121

62 Future Enhancements The VPX electrical specification will form the baseline for a number of future standards efforts. Of these the Mechanical Specifications for Microcomputers Using Ruggedized Enhanced Design Implementation (REDI) VITA 48.0 standard is the most advanced. The VITA 48.0 REDI standard will define form factors and the infrastructure for enhanced thermal management required to support higher power densities. Table 16 lists the current standardisation efforts. 6 VITA 48.0 REDI 6 VITA 48.1 REDI Air Cooling Applied to VITA 46 6 VITA 48.2 REDI Conduction Cooling Applied to VITA 46 6 VITA 48.3 REDI Liquid Cooling Applied to VITA 46 6 Table 16 REDI standards under development There is a growing need for REDI. Increased levels of integration coupled with higher clock rates are forcing board level powers up. As an example consider a typical 6U VME processor card that might have dissipated 20 to 25 watts. Today integration coupled with advanced PCB layout tools allow a designer to put together a quad dual core signal processing solution in the same form factor. Using the latest devices tuned for performance this design could easily reach 125 watts+. What s more this figure could go much higher with forecast device roadmaps. The move to faster data communications further compounds the problem in that to a first approximation a Gigabit Ethernet PHY dissipates one watt. All this heat needs to go somewhere! REDI and its subsidiary standards propose a range of solutions for both 3U and 6U form factors. Fundamental to these is the definition of three slot pitches: 0.8 inch, 0.85 inch and 122 gefanuc.com VPX 123

63 1 inch. For reference VMEbus only employed the 0.8 inch slot pitch. The wider slot pitches enable better cooling and therefore higher slot powers to be supported: Air cooled. A greater slot pitch allows for greater airflow and for a given temperature rise the removal of more heat energy. This assumes that mechanisms, such as fins, are provided to ensure that the cooling air comes into contact with hot components. Conduction cooled. The advantage here doesn t lie at the board level in that the area allocated for heat transfer is the same for each slot pitch. The advantage lies at the chassis level. Conduction cooled boards normally bleed heat into a chassis sidewall heat exchanger. With a greater distance between slots the heat exchanger size increases and therefore more heat can be dissipated. Type 1 plug in units are compatible with 2 level maintenance requirements. Note that the 0.85 inch slot pitch derives from a standard 0.8 inch pitch card with additional clearance for covers. Type 2 plug in units have one or more covers absent and as a result are NOT fully compatible with 2 level maintenance requirements Two logos, or Glyphs, are currently associated with REDI products and these are illustrated in Figure 55 Liquid cooled. Liquid cooling components, particularly those required for Liquid Flow Through (LFT) cooling are large and can t be accommodated in the 0.8 inch slot pitch. For liquid cooled chassis that support conduction cooled cards then again a larger slot pitch enables a larger heat exchanger to be incorporated supporting higher slot powers. Greater separation between slots does of course allow the use of taller components and this is considered in the REDI standard. REDI also defines two types of plug in unit. Figure 55. REDI Glyphs For full details of the REDI standard please refer to gefanuc.com VPX 125

64 Appendix A Sources of further information VPX standards and draft standards All standards are available from VITA: VITA 46.0 VPX Base Standard ANSI Ratified VITA 46.1 VMEbus Signal Mapping on VPX ANSI Ratified VITA 46.2 PCI on VITA 46 inactive VITA 46.3 Serial RapidIO(tm) on VPX Fabric Connector draft VITA 46.4 PCI Express on VPX Fabric Connector draft VITA 46.5 Hypertransport on VPX inactive VITA 46.6 Gbit Ethernet on VITA 46 see 46.7 VITA 46.7 Ethernet on VPX Fabric Connector draft VITA 46.8 Infiniband on VITA 46 inactive VITA 46.9 PMC/XMC/Ethernet Signal Mapping to 3U/6U draft on VPX User IO VITA Rear Transition Module for VPX draft VITA System Mgmt on VPX planned VITA Fibre Optic Interface on VPX planned VITA Fibre Channel on VPX planned VITA VPX Switch Slot Definition planned Approved ANSI/VITA standards All standards available from VITA: ANSI/VITA (R2002) ANSI/VITA (R2003) ANSI/VITA ANSI/VITA ANSI/VITA (R2005) ANSI/VITA ANSI/VITA (R2002) ANSI/VITA (R2002) VME64 Standard - This standard covers the main body of the VMEbus specification. It includes both 32 bit and 64 bit usage. Reaffirmed in VME64 Extensions - This standard covers extensions to the VME64 specification including the 160 pin connector, geographical addressing, and added power pins. Reaffirmed in (R2003) VME64x 9U x 400 mm Format - This standard defines a 9U x 400 mm board layout for use within the VMEbus framework. Reaffirmed in eSST - This standard defines a new VME protocol that allows data transfers of up to 320 Mbytes/second. Keying for Conduction Cooled VME64x. Reaffirmed in Increased Current DIN Connector- This standard describes increased current levels, test methods, test data and compliance criteria for 3 row DIN and 5 row DIN connectors when used in VME, VME64 and VME64 Extension P1/J1 and P2/J2 pin out arrangements. Board Level Live Insertion - This standard defines several methodologies for using VMEbus modules in a live insertion framework. Reaffirmed in IP Module - This standard defines the requirements for a business card sized mezzanine module printed circuit board. Reaffirmed in gefanuc.com VPX 127

65 ANSI/VITA (R2003) IP I/O Mapping to VME64x - This standard defines the pin assignments from IP Modules to the VME64x P0 and P2 connectors. Reaffirmed in RACEway Interlink - This standard defines a high speed circuit switched point to point interconnect for use between VMEbus modules via the P2 connector. Reaffirmed in SCSA - This standard defines an isochronous backplane bus for telephony applications on the VMEbus P2 connector. Reaffirmed in SCSA Extensions - This standard provides feature extensions to the ANSI/VITA 6 standard. Reaffirmed in SKYchannel - This standard defines a packet switched cross bar interconnect that runs on the VMEbus P2 connector. Reaffirmed in M-Module - This standard defines a mezzanine module specification for small sized printed circuit boards. Reaffirmed in VMEbus Pin Assignment Standard for ISO/IEC (IEEE Std (H.I.C.)) - Historical Standard. This standard was withdrawn in 2006 and is provided for historical reference only. This standard defines a pin assignment on VME for the Heterogeneous Interconnect protocol defined in IEEE 1355 Front Panel Data Port - This standard defines a point to point data interconnect for use on front panel Eurocard modules. Reaffirmed in Serial Front Panel Data Port - This standard defines Serial FPDP, a high-speed low-latency serial communications protocol for use in high-speed data transfer applications, typically using a fiber optic link. VITA 19 BusNet Overview - This document is not a recognized ANSI standard and will not be submitted for standardization. It is provided here for completeness with the ANSI/VITA 19.1 and 19.2 standards. BusNet Media Access Control - Historical Standard. This standard was withdrawn in 2006 and is provided for historical reference only.this standard defines the media access control layer for the BusNet backplane software protocol. BusNet Link Layer Control - Historical Standard. This standard was withdrawn in 2006 and is provided for historical reference only. This standard defines the link layer control layer for the Busnet backplane software protocol. CCPMC - Conduction Cooled PMC - This standard defines the mechanical requirements for compliance with conduction cooled PMC modules. Revised in VME64 Extensions for Physics - This standard defines a series of recommended practices for the use of VMEbus in the physics community. Reaffirmed in VISION - Historical Standard. This standard was withdrawn in 2006 and is provided for historical reference only. This standard defines a software application interface for VMEbus modules. Myrinet - This standard defines a packet switched interconnect protocol for implementation in a VMEbus environment. Reaffirmed in PC MIP - Historical Standard. This standard was withdrawn in 2006 and is provided for historical reference only. This standard defines the mechanical form factor and the pin assignments for a small form factor mezzanine module based on the PCI bus. ANSI/VITA (R2004) ANSI/VITA (R2002) ANSI/VITA (R2003) ANSI/VITA (R2002) ANSI/VITA (R2002) ANSI/VITA (W2006) ANSI/VITA (R2004) ANSI/VITA ANSI/VITA (W2006) ANSI/VITA (W2006) ANSI/VITA (R2005) ANSI/VITA (R2004) ANSI/VITA (W2006) ANSI/VITA (R2003) ANSI/VITA (W2006) 128 gefanuc.com VPX 129

66 ANSI/VITA (R2005) 2mm Connector Practice for Euroboard Systems - This standards provides the dimensions for Euroboard systems that use 2mm connectors. Reaffirmed in mm Connector Practice for Conduction Cooled Euroboard Systems - This standard defines the dimensions for conduction cooled Euroboards when used with 2mm connectors. Gigabit Ethernet on VME64x Backplanes - This standard defines a pin assignment and interconnection methodology for implementing a 10/100/1000BASE-T Ethernet switched network on a ANSI/ VITA 1.1 VME64x backplane. Processor PMC - This standard incorporates a set of extensions to the IEEE PMC ( PCI Mezzanine Card ) standard which creates a new class of CPU based PMC cards referred to in this standard as Processor PMC cards. The standard retains electrical signaling compatibility with existing PMC cards. Provides pin assignments for PMC P4 connector to VME P0 and P2 connectors. Reaffirmed in This standard describes a methodology for using IPMI for System Management of VME systems. PCI-X for PMC and Processor PMC - This standard integrates the PCI-X capability from PCI to PMC based products, including standard PMCs as well as Processor PMCs. Status Indicator Standard. This standard defines the colors, behaviors, placement, and labeling of service indicator lamps for boards, field replaceable units, and enclosures. VXS VMEbus Switched Serial Standard - This standard defines a method for using switched serial fabrics within the VMEbus framework. ANSI/VITA VXS 4X InfiniBand Protocol Layer Standard - This standard describes a method for using the InfiniBand protocol on ANSI/VITA 41.0, VXS. VXS 4X Serial RapidIO Protocol Layer Standard - This standard describes a method for implementing Serial Rapid I/O on ANSI/VITA 41.0, VXS. XMC Switched Mezzanine Card: Parallel RapidIO 8/16 LP-LVDS Protocol Layer Standard - This standard defines the implementation of Parallel RIO on VITA 42.0, XMC. XMC Serial RapidIO Protocol Layer Standard - This standard defines the implementation of Serial RIO on VITA 42.0, XMC. XMC PCI Express Protocol Layer Standard - This standard defines the implementation of PCI Express on VITA 42.0, XMC. VPX Baseline Standard - This standard defines requirements for VPX. ANSI/VITA ANSI/VITA ANSI/VITA ANSI/VITA ANSI/VITA (R2005) ANSI/VITA ANSI/VITA ANSI/VITA ANSI/VITA ANSI/VITA ANSI/VITA ANSI/VITA ANSI/VITA (R2007) VMEbus Signal Mapping on VPX - This standard defines signal mapping for VMEbus signals on VPX. This standard defines environmental, design and construction, safety, and quality requirements for commercial-off-the-shelf (COTS) plug-in units (cards, modules, etc) intended for mobile applications. ANSI/VITA ANSI/VITA gefanuc.com VPX 131

67 Appendix B Signal mapping for a 3U VPX Rear Transition Module For connector assignments reference should be made to Figure 54. Row G P0 G 1 J0 F1 G1 H1 I1 RJ0 RP0 G 2 F2 G2 H2 I2 F15 G15 H15 I15 G 15 G 3 F3 G3 H3 I3 F14 G14 H14 I14 G 14 G 4 H4 I13 G 13 G 5 H5 I12 G 12 G 6 H6 I11 G 11 G 7 I7 I10 G 10 G 8 I8 I9 G 9 P1 G 1 J1 I1 I8 G 8 G 2 I2 I7 G 7 G 3 I3 I6 G 6 G 4 I4 I5 G 5 G 5 I5 I4 G 4 G 6 I6 I3 G 3 G 7 I7 I2 G 2 G 8 I8 I1 G 1 G 9 I9 RJ1 I16 RP1 G 16 G 10 I10 I15 G 15 G 11 I11 I14 G 13 G 12 I12 I13 G 13 G 13 I13 I12 G 12 G 14 I14 I11 G 11 G 15 I15 I10 G 10 G 16 I16 I9 G 9 P2 G 1 J2 I1 I8 G 8 G 2 I2 I7 G 7 G 3 I3 I6 G 6 G 4 I4 I5 G 5 G 5 I5 I4 G 4 G 6 I6 I3 G 3 G 7 I7 I2 G 2 G 8 I8 I1 G 1 G 9 I9 RJ2 I8 RP2 G 8 G 10 I10 I7 G 7 G 11 I11 I6 G 6 G 12 I12 I5 G 5 G 13 I13 I4 G 4 G 14 I14 I3 G 3 G 15 I15 I2 G 2 G 16 I16 I1 G gefanuc.com VPX 133

68 Row P0 F F 1 J0 F1 G1 H1 I1 RJ0 RP0 F 4 H4 H5 F 5 F 2 F2 G2 H2 I2 F15 G15 H15 I15 F 15 F 5 G5 H5 G4 H4 F 4 F 3 F3 G3 H3 I3 F14 G14 H14 I14 F 14 F 6 H6 H3 F 3 F 4 G4 G13 F 13 F 7 G7 H7 G2 H2 F 2 F 5 G5 G12 F 12 F 8 H8 H1 F 1 F 6 G6 G11 F 11 F 9 G9 H9 RJ2 G8 H8 RP2 F 8 F 7 G7 H7 G10 H10 F 10 F 10 H10 H7 F 7 F 8 H8 H9 F 9 F 11 G11 H11 G6 H6 F 6 P1 F 1 J1 G1 H1 G8 H8 F 8 F 12 H12 H5 F 5 F 2 H2 H7 F 7 F 13 G13 H13 G4 H4 F 4 F 3 G3 H3 G6 H6 F 6 F 14 H14 H3 F 3 F 4 H4 H5 F 5 F 15 G15 H16 G2 H2 F 2 F 5 G5 H5 G4 H4 F 4 F 16 H16 H1 F 1 F 6 H6 H3 F 3 F 7 G7 H7 G2 H2 F 2 Row E F 8 H8 H1 F 1 P0 E 1 J0 F1 G1 H1 I1 RJ0 RP0 F 9 G9 H9 RJ1 G16 H16 RP1 F 16 E 2 F2 G2 H2 I2 F15 G15 H15 I15 E 15 F 10 H10 H15 F 15 E 3 F3 G3 H3 I3 F14 G14 H14 I14 E 14 F 11 G11 H11 G14 H14 F 13 E 4 A4 D4 F4 I4 A13 D13 F13 I13 E 13 F 12 H12 H13 F 13 E 5 A5 D5 F5 I5 A12 D12 F12 I12 E 12 F 13 G13 H13 G12 H12 F 12 E 6 A6 D6 F6 I6 A11 D11 F11 I11 E 11 F 14 H14 H11 F 11 E 7 F7 F10 E 10 F 15 G15 H16 G10 H10 F 10 E 8 G8 G9 E 9 F 16 H16 H9 F 9 P1 E 1 J1 F1 F8 E 8 P2 F 1 J2 G1 H1 G8 H8 F 8 E 2 G2 G7 E 7 F 2 H2 H7 F 7 E 3 F3 F6 E 6 F 3 G3 H3 G6 H6 F 6 E 4 G4 G5 E gefanuc.com VPX 135

69 E 5 F5 F4 E 4 E 16 G16 G1 E 1 E 6 G6 G3 E 3 E 7 F7 F2 E 2 Row D E 8 G8 G1 E 1 P0 D 1 J0 N/C RJ0 RP0 E 9 F9 RJ1 F16 RP1 E 16 D 2 N/C N/C D 15 E 10 G10 G15 E 15 D 3 N/C N/C D 14 E 11 F11 F14 E 13 D 4 E4 E13 D 13 E 12 G12 G13 E 13 D 5 E5 E12 D 12 E 13 F13 F12 E 12 D 6 E6 E11 D 11 E 14 G14 G11 E 11 D 7 E7 E10 D 10 E 15 F15 F10 E 10 D 8 E8 F8 E9 F9 D 9 E 16 G16 G9 E 9 P1 D 1 J1 E1 E8 D 8 P2 E 1 J2 F1 F8 E 8 D 2 E2 F2 E7 F7 D 7 E 2 G2 G7 E 7 D 3 E3 E6 D 6 E 3 F3 F6 E 6 D 4 E4 F4 E5 F5 D 5 E 4 G4 G5 E 5 D 5 E5 E4 D 4 E 5 F5 F4 E 4 D 6 E6 F6 E3 F3 D 3 E 6 G6 G3 E 3 D 7 E7 E2 D 2 E 7 F7 F2 E 2 D 8 E8 F8 E1 F1 D 1 E 8 G8 G1 E 1 D 9 E9 RJ1 E16 RP1 D 16 E 9 F9 RJ2 F8 RP2 E 8 D 10 E10 F10 E15 F15 D 15 E 10 G10 G7 E 7 D 11 E11 E14 D 13 E 11 F11 F6 E 6 D 12 E12 F12 E13 F13 D 13 E 12 G12 G5 E 5 D 13 E13 E12 D 12 E 13 F13 F4 E 4 D 14 E14 F14 E11 F11 D 11 E 14 G14 G3 E 3 D 15 E15 E10 D 10 E 15 F15 F2 E 2 D 16 E16 F16 E9 F9 D gefanuc.com VPX 137

70 P2 D 1 J2 E1 E8 D 8 C 2 D2 D7 C 7 D 2 E2 F2 E7 F7 D 7 C 3 C3 D3 C6 D6 C 6 D 3 E3 E6 D 6 C 4 D4 D5 C 5 D 4 E4 F4 E5 F5 D 5 C 5 C5 D5 C4 D4 C 4 D 5 E5 E4 D 4 C 6 D6 D3 C 3 D 6 E6 F6 E3 F3 D 3 C 7 C7 D7 C2 D2 C 2 D 7 E7 E2 D 2 C 8 D8 D1 C 1 D 8 E8 F8 E1 F1 D 1 C 9 C9 D9 RJ1 C16 D16 RP1 C 16 D 9 E9 RJ2 E8 RP2 D 8 C 10 D10 D15 C 15 D 10 E10 F10 E7 F7 D 7 C 11 C11 D11 C14 D14 C 13 D 11 E11 E6 D 6 C 12 D12 D13 C 13 D 12 E12 F12 E5 F5 D 5 C 13 C13 D13 C12 D12 C 12 D 13 E13 E4 D 4 C 14 D14 D11 C 11 D 14 E14 F14 E3 F3 D 3 C 15 C15 D15 C10 D10 C 10 D 15 E15 E2 D 2 C 16 D16 D9 C 9 D 16 E16 F16 E16 F1 D 1 P2 C 1 J2 C1 D1 C8 D8 C 8 C 2 D2 D7 C 7 Row C C 3 C3 D3 C6 D6 C 6 P0 C 1 J0 A1 B1 C1 D1 RJ0 RP0 C 4 D4 D5 C 5 C 2 A2 B2 C2 D2 A15 B15 C15 D15 C 15 C 5 C5 D5 C4 D4 C 4 C 3 A3 B3 C3 D3 A14 B14 C14 D14 C 14 C 6 D6 D3 C 3 C 4 A4 D4 F4 I4 A13 D13 F13 I13 C 13 C 7 C7 D7 C2 D2 C 2 C 5 A5 D5 F5 I5 A12 D12 F12 I12 C 12 C 8 D8 D1 C 1 C 6 A6 D6 F6 I6 A11 D11 F11 I11 C 11 C 9 C9 D9 RJ2 C8 D8 RP2 C 8 C 7 C7 D7 C10 D10 C 10 C 10 D10 D7 C 7 C 8 D8 D9 C 9 C 11 C11 D11 C6 D6 C 6 P1 C 1 J1 C1 D1 C8 D8 C 8 C 12 D12 D5 C gefanuc.com VPX 139

71 C 13 C13 D13 C4 D4 C 4 B 14 C14 C11 B 11 C 14 D14 D3 C 3 B 15 B15 B10 B 10 C 15 C15 D15 C2 D2 C 2 B 16 C16 C9 B 9 C 16 D16 D1 C 1 P2 B 1 J2 B1 B8 B 8 B 2 C2 C7 B 7 Row B B 3 B3 B6 B 6 P0 B 1 J0 A1 B1 C1 D1 RJ0 RP0 B 4 C4 C5 B 5 B 2 A2 B2 C2 D2 A15 B15 C15 D15 B 15 B 5 B5 B4 B 4 B 3 A3 B3 C3 D3 A14 B14 C14 D14 B 14 B 6 C6 C3 B 3 B 4 C4 C13 B 13 B 7 B7 B2 B 2 B 5 C5 C12 B 12 B 8 C8 C1 B 1 B 6 C6 C11 B 11 B 9 B9 RJ2 B8 RP2 B 8 B 7 B7 B10 B 10 B 10 C10 C7 B 7 B 8 C8 C9 B 9 B 11 B11 B6 B 6 P1 B 1 J1 B1 B8 B 8 B 12 C12 C5 B 5 B 2 C2 C7 B 7 B 13 B13 B4 B 4 B 3 B3 B6 B 6 B 14 C14 C3 B 3 B 4 C4 C5 B 5 B 15 B15 B2 B 2 B 5 B5 B4 B 4 B 16 C16 C1 B 1 B 6 C6 C3 B 3 B 7 B7 B2 B 2 Row A B 8 C8 C1 B 1 P0 A 1 J0 A1 B1 C1 D1 RJ0 RP0 B 9 B9 RJ1 B16 RP1 B 16 A 2 A2 B2 C2 D2 A15 B15 C15 D15 A 15 B 10 C10 C15 B 15 A 3 A3 B3 C3 D3 A14 B14 C14 D14 A 14 B 11 B11 B14 B 13 A 4 B4 B13 A 13 B 12 C12 C13 B 13 A 5 B5 B12 A 12 B 13 B13 B12 B 12 A 6 B6 B11 A gefanuc.com VPX 141

72 A 7 A7 A10 A 10 A 10 A10 B10 A7 B7 A 7 A 8 A8 B8 A9 B9 A 9 A 11 A11 A6 A 6 P1 A 1 J1 A1 A8 A 8 A 12 A12 B12 A5 B5 A 5 A 2 A2 B2 A7 B7 A 7 A 13 A13 A4 A 4 A 3 A3 A6 A 6 A 14 A14 B14 A3 B3 A 3 A 4 A4 B4 A5 B5 A 5 A 15 A15 A2 A 2 A 5 A5 A4 A 4 A 16 A16 B16 A16 B1 A 1 A 6 A6 B6 A3 B3 A 3 A 7 A7 A2 A 2 A 8 A8 B8 A1 B1 A 1 A 9 A9 RJ1 A16 RP1 A 16 A 10 A10 B10 A15 B15 A 15 A 11 A11 A14 A 13 A 12 A12 B12 A13 B13 A 13 A 13 A13 A12 A 12 A 14 A14 B14 A11 B11 A 11 A 15 A15 A10 A 10 A 16 A16 B16 A9 B9 A 9 P2 A 1 J2 A1 A8 A 8 A 2 A2 B2 A7 B7 A 7 A 3 A3 A6 A 6 A 4 A4 B4 A5 B5 A 5 A 5 A5 A4 A 4 A 6 A6 B6 A3 B3 A 3 A 7 A7 A2 A 2 A 8 A8 B8 A1 B1 A 1 A 9 A9 RJ2 A8 RP2 A gefanuc.com VPX 143

73 GE Fanuc Intelligent Platforms Information Centers Americas: or Asia Pacific: Additional Resources For more information, please visit the GE Fanuc Intelligent Platforms web site at: Europe, Middle East and Africa: Germany: UK: GE Fanuc Intelligent Platforms, Inc. All rights reserved. All other brands or names are property of their respective holders. Specifications are subject to change without notice GFA-1123