Reverse engineering hardware for software reversers: studying an encrypted external HDD
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1 Reverse engineering hardware for software reversers: studying an encrypted external HDD Joffrey Czarny & Raphaël Rigo / AGI / TX5IT / Hardwear.io
2 / Hardwear.io 2
3 Introduction Why study encrypted hard drives? Initially: audit need inside Airbus Group Previous work revealed vulnerabilities Discover how to analyze hardware based on microcontrollers Previous epic fails on this type of HW Kingston/SanDisk FIPS 140-2: magic unlocking packet (2010) Corsair Padlock: data not encrypted, reachable without PIN (2008) Corsair Padlock 2: brute-forceable PIN (2010) WD Passport (yesterday s talk by Gunnar Alendal and Christian Kison) End goal Analyze the actual level of protection of user data = Validate security and cryptography implementations inside the enclosure / Hardwear.io 3
4 Introduction This talk s objectives: Describe the study of an external encrypted HDD: Explain the methodology in details Show our various failures Give leads to continue the analysis Case study: Zalman ZM-VE400 Enclosure: HDD is replaceable Optional AES-256 XTS encryption (physical keyboard) Can mount ISO as USB optical drive Really a rebranded iodd / Hardwear.io 4
5 Context, first results General security checks Verify basic crypto properties: ECB mode? statistical tests OK? Fixed key? More tests, to verify the key is not derived directly from the PIN: The same PIN, on 2 different enclosures, must lead to different encryption The same PIN, on the same enclosure, must lead to different encryption Secret material (keys, hashes) should be stored in tamper resistant hardware VE400 results Basic crypto properties: OK Encryption does not depend on enclosure: an encrypted HDD put in a new Zalman enclosure can be accessed with the right PIN Activating encryption uses 10 sectors at the end of the HDD: Not usable anymore Contain a blob of 768 bytes, of high entropy, twice / Hardwear.io 5
6 Going forward Important result: design failure Everything needed to decrypt data is stored on the HDD itself. = Efficient attacks are possible (bruteforce, key recovery) New end goal Understand the blob stored at the end of the disk: its data and its format, to implement an offline attack How? First by trying to access the firmware and/or by analyzing communications Firmware updates are encrypted, so we need to attack the hardware / Hardwear.io 6
7 Hardware analysis PCB analysis Components identification Traces and vias identification = Logical view Flash memories study Identify communication buses Flash content recovery = Flash content analysis (hopefully cleartext code) / Hardwear.io 7
8 PCB: component identification 1/2 PCB: front side System on Chip (SoC) Fujitsu MB86C311 USB3-SATA SPI flash EN25F80 PIC32MX 150F128D microcontroller / Hardwear.io 8
9 PCB: component identification 2/2 PCB: back size SPI flash EN25F / Hardwear.io 9
10 SoC and microcontroller Fujitsu MB86C311 USB3 SATA controller AES-256 XTS encryption ARM core Internal ROM and external SPI firmware support (encrypted?) PIC32MX 150F128D MIPS32 CPU (with MIPS16e support) 128 Ki of internal flash 32 Ki of RAM Supports ICSP and EJTAG Protection bits to disable external access / Hardwear.io 10
11 PCB: traces analysis (1/5): Hobo mode with GIMP / Hardwear.io 11
12 PCB: traces analysis (2/5): getting real with PCBRE [5] / Hardwear.io 12
![with PCBRE [5]](/docs-images/41/9512002/images/page_12.jpg "2015-10-02 /")
13 PCB: traces analysis (3/5): leveling up: optical microscope / Hardwear.io 13
14 PCB: traces analysis (4/5): level cap: X-rays / Hardwear.io 14
15 PCB: traces analysis (5/5) In the end One flash dedicated to the USB-SATA controller (SoC) One flash dedicated to the PIC32 One link between the SoC and the PIC, (partially) shared with the SoC flash / Hardwear.io 15
16 PCB: logic view What s inside the flash chips? Maybe the code is in cleartext? = Let s get their contents! / Hardwear.io 16
17 Flash content recovery (1/2) Reading flash content SPI Chip desoldering needed to avoid interferences Interface using a SOIC DIP adapter to keep the board working / Hardwear.io 17
18 Flash content recovery (2/2) SPI tools GoodFET with goodfet.spiflash (recommended) Bus Pirate Raspberry Pi with spidev Results: flashes content USB-SATA controller: Plaintext configuration data (USB descriptors, etc.) Code, encrypted PIC32 microcontroller: A font, for the LCD screen Code, encrypted / Hardwear.io 18
19 Results Code access: fail All the code is encrypted, so we cannot reverse engineer the firmware What can we do now? As in network reversing, we will analyze communications (black box) How? By using a logic analyzer to capture communications / Hardwear.io 19
20 Hardware and probe placement Saleae Logic Pro 16 logic analyzer / Hardwear.io 20
21 PCB traces and components pinout / Hardwear.io 21
22 Probe placement / Hardwear.io 22
23 Screenshot / Hardwear.io 23
24 Analyzing flash SPI communications USB-SATA/PIC to flash Placing the 4 probes: simply on flash pins SPI decoding parameters: standard (cf. datasheet) Sampling speed: 50MS/s min, 100MS/s recommended (25MHz quartz) Post-treatment CSV export of decoded SPI data Ruby script to interpret flash commands: Text display Binary dump rebuilding Results PIC never writes to its external flash USB-SATA controller writes data when the PIN is validated / Hardwear.io 24
25 Analyzing SoC PIC communications USB-SATA controller PIC Probes placement: on the SOC flash pins (cf. PCB traces) Sampling speed: 50MS/s min, 100MS/s recommended Protocol: unknown Post-treatment SPI based protocol: Low level decoding with Saleae, then CSV export Application-layer data must be reversed engineered / Hardwear.io 25
26 Custom protocol Reverse engineering Preambles: AA AA AA AA 55 (SoC PIC) and A5 A5 A5 5A (PIC SoC) Type, Length, Value Frames are numbered and acknowledged Unknown 16bits checksum = Ruby script to decode data from the CSV produced by Saleae Decoded example: PIN request SoC->PIC T: 0x33, ID: 0x14 01,01,10, PIC->SoC RESP: 0x14 06,00,01,00,09,4d,01,cb, 0e,00,00,00,89,0f,3a,7a / Hardwear.io 26
27 Summary: communication sequence / Hardwear.io 27
28 Summary: communication sequence / Hardwear.io 27
29 Summary: communication sequence / Hardwear.io 27
30 Summary: communication sequence / Hardwear.io 27
31 Summary: communication sequence / Hardwear.io 27
32 Summary: communication sequence / Hardwear.io 27
33 Summary: communication sequence / Hardwear.io 27
34 Summary: communication sequence / Hardwear.io 27
35 Summary: communication sequence / Hardwear.io 27
36 Summary: communication sequence / Hardwear.io 27
37 Summary: communication sequence / Hardwear.io 27
38 Summary: communication sequence / Hardwear.io 27
39 And now? Remaining questions Can we do a hardware bruteforcer? (PIC+Keyboard emulator) No, because the hash algorithm is unknown What is inside the block at 0x1000 in the SoC flash? Flash block at 0x1000 Properties: Written when: Enabling encryption Entering a valid PIN Erased when encryption is disabled Contains 3 different blocks of data of high entropy: bits, AES-256-XTS key 1, encrypted? bits, AES-256-XTS key 2, encrypted? 3. SHA256 of previous data (1 and 2) / Hardwear.io 28
40 Designing an attack Hypothesis The block at 0x1000 seems to contain AES-XTS encryption keys, in an encrypted or obfuscated form Implications? Can we use this block to mount an attack? The idea Assuming the block at 0x1000 contains decryption keys: We will try to keep the one of the target drive intact, in the flash... while validating the PIN against a chosen blob, stored on the HDD / Hardwear.io 29
41 Theoretical steps / Hardwear.io 30
42 Theoretical steps / Hardwear.io 30
43 Theoretical steps / Hardwear.io 30
44 Theoretical steps / Hardwear.io 30
45 Theoretical steps / Hardwear.io 30
46 Theoretical steps / Hardwear.io 30
47 Theoretical steps / Hardwear.io 30
48 Theoretical steps / Hardwear.io 30
49 Theoretical steps / Hardwear.io 30
50 Theoretical steps / Hardwear.io 30
51 In practice First fail The flash status register is reset to 0 during startup Attack, second version The flash is put in read only after startup: 1. Connect the enclosure 2. Unplug flash 3. Put it in read only using GoodFET 4. Plug it back 5. Continue the attack: enter the known PIN Final result Fail. PIN code is not valid (Not match on screen) = There s probably an unidentified check / Hardwear.io 31
52 Final attack: demo / Hardwear.io 32
53 Conclusion Encrypted data security The whole security relies on: The security of the blob at the end of the disk The security of the block at 0x1000 in the flash = Everything relies on the fact that the Fujitsu firmware is secret iodd s feedback (original board dev) Firmware evolution (version 077): PIN hash is now non-deterministic The rest is not fixable: Customer support choice: data can survive broken enclosure Opaque handling of the blob at the end of the HDD: binary code provided by Fujitsu / Hardwear.io 33
54 Conclusion: going further Access the code of the USB-SATA controller Find a JTAG? (unlikely) The firmware encryption is the same on all chips: Buy the SDK? (probable NDA) Find someone generous ;) Emulate the SoC SPI flash Allows subtle modifications of block 0x1000 Try blind ARM code modifications Dump PIC32 code Use semi-invasive attack to reset protection fuse = Hardware bruteforcer by emulating the whole keyboard/screen part / Hardwear.io 34
55 End Questions? / Hardwear.io 35
56 References [1] [2] USB-stick-with-PIN-code html [3] [4] [5] [6] [7] / Hardwear.io 36
57 Blob comparison / Hardwear.io 37
58 Firmware comparison: Zalman vs PS / Hardwear.io 38
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