PNX85500 Single Chip LCD TV System with integrated 120Hz HD Frame Rate Converter

Transcription

1 PNX85500 Single Chip LCD TV System with integrated 120Hz HD Frame ate Converter Colin Osborne / alf Karge PNX85500 Single Chip LCD TV System Hot Chips 2009 August, 25, 2009

2 Presentation Outline Introduction System Integration More TV System on a Chip PNX85500 TV Solution Design Challenges Architecture Memory Bandwidth and Latency Verification and Emulation High-lighted Features Conclusions PNX85500 / HotChips / C.Osborne,. Karge 2

3 Introducing the TV550 System TV550 System comprises the world s first Digital TV SoC in C045: PNX85500 Extremely high level of functional integration Channel demodulators, networking (USB, HDMI, Ethernet, SD card reader), 120 Hz, H.264 HD decoding, advanced Picture Quality Algorithms, etc. Smallest memory requirement for the total system Full application (networking, H.264 HD decoding, advanced gfx, FC, ) all on 2x16-bit DD2 footprint! Drives industry s lowest cost-of-ownership/bill-of-material Avoid expensive EMI protection with built-in spread-spectrum on both LVDS as well as DD interfaces Enables development for global chassis roll out thanks to low system costs Minimize upfront development costs and time-to-market for global rollout One development, one PCB line, one test set up PNX85500 / HotChips / C.Osborne,. Karge 3

4 Introduction System Integration More TV System on a Chip PNX85500 TV Solution Design Challenges Architecture Memory Bandwidth and Latency Verification and Emulation High-lighted Features Conclusions PNX85500 / HotChips / C.Osborne,. Karge 4

5 TV550 System Integration Tuner TDA18272 Silicon Tuner CVBS,Y/C, GB L/ YCbCr SPDIF GB, HV L/ PNX85500 Analog IF IP TDA8296 DVB-C Channel Decoder TDA10024 DVB-T Channel Decoder TDA10048 Low-IF CVBS/SIF TS PCMCIA CI+ Ethernet MAC DD2 256MB NXP PNX8543 MHz Pixel OSD, TV Control, HDMI,USB,PC-AVI PNX bit DD2-666 L/ LVDS-2 CVBS SPDIF L, L, 32 bit DD2-666 DD2 128MB NXP PNX5120 Frame ate Conversion NXP TFA9810 Audio Amplifier HD 1080p 100/120Hz 50/60Hz Switch TDA9996 HDMI Switch FLASH 128 MB PNX85500 / HotChips / C.Osborne,. Karge 5

6 TV550 System Integration Tuner TDA18272 Silicon Tuner CVBS,Y/C, GB L/ YCbCr SPDIF GB, HV L/ PNX85500 Analog IF IP TDA8296 DVB-C Channel Decoder TDA10024 DVB-T Channel Decoder TDA10048 Low-IF CVBS/SIF TS PCMCIA CI+ Ethernet MAC DD2 256MB NXP NXP PNX8543 PNX85500 MHz Pixel OSD, TV Control, HDMI,USB,PC-AVI PNX bit DD2-666 L/ LVDS-2 CVBS SPDIF L, L, 32 bit DD2-666 DD2 128MB NXP PNX5120 Frame ate Conversion NXP TFA9810 Audio Amplifier HD 1080p 100/120Hz 50/60Hz Switch TDA9996 HDMI Switch FLASH 128 MB PNX85500 / HotChips / C.Osborne,. Karge 6

7 TV550 FC 120Hz FULL HD DVB-T, CI+, PAL/SECAM, IP TV550 DD2 128 DD2 MB 128 MB FLASH 64 MB TDA18272 Si Tuner PNX8550x CI+ TFA9810 TDA9996 switch DIGITAL AUDIO IN HDMI HDMI PHY HDMI HDMI DIGITAL AUDIO OUT USB Ethernet PNX85500 / HotChips / C.Osborne,. Karge 7

8 TV550 FC 120Hz FULL HD DMB-T/ATSC/ISDB-T, PAL/SECAM/NTSC, IP TV550 DD2 128 DD2 MB 128 MB FLASH 64 MB TDA18272 Si Tuner Channel Demod PNX8550x TFA9810 TDA9996 switch DIGITAL AUDIO IN HDMI HDMI PHY HDMI HDMI DIGITAL AUDIO OUT USB Ethernet Optional China CI+ PNX85500 / HotChips / C.Osborne,. Karge 8

9 PNX85500 Block Diagram MCU_DD (32bit) SYS_CTL Interrupts CLOCKS ESET JTAG UAT PC_AVI Channel Decode HDMI_X Audio Decoding Audio Processor TC MIPS24K Control Network FLASH_CTL MIPS24K I2C PC_AVI Transport Stream Input CAI USB 2D Drawing GFX_SCALE ETHENET SPI SD Card A MEM_AB A DMA Network / Digital Video Decoder AV-DSP Frame ate Converter MPEG Demux Scatter/Gather DMA Video Scaler (1) Video Composition Pipe (1) Video Input Processor Video Scaler (2) Video Composition Pipe (2) PC_AVI SPDIF I2S AVDSP Control Network Interrupts GPIO LVDS_TX DENC Key Control Network DMA Network DMA ead DMA rite BIDGE Digital Video Generic Processing Broadcast Audio Control Processing / and Transport Interconnect Graphics Stream PNX85500 / HotChips / C.Osborne,. Karge 9

10 Introduction System Integration More TV System on a Chip PNX85500 TV Solution Design Challenges Architecture Memory Bandwidth and Latency Verification and Emulation High-lighted Features Conclusions PNX85500 / HotChips / C.Osborne,. Karge 10

11 Organizational Complexity orld-wide multi-site project UK, Netherlands, Germany, France, India, Israel, USA Chicago Southampton Caen Hamburg Number of IPs Approx 100 IP blocks (85% NXP-internal) Compute infra metrics 15 TBytes of disk space 3 TBytes of AM for SoC Integration San Jose Eindhoven Haifa Bangalore PNX85500 / HotChips / C.Osborne,. Karge 11

12 Integrating many different functions Function Established H functions High performance H functions Control processing Flexible DSP High performance DSP Examples Analogue audio/video decoding Video scaling & composition Generic operating system Audio & video feature processing Motion Accurate Picture Processing MIPS24K Analogue Standards Decoder MPEG Demux & Descrambler Picture Quality Processing Digital Audio Decoder MPEG/H.264 Video Decoder Frame ate Conversion Audio and Video Capture Audio Post-Processing Flexible Video Decoder Auto Picture Control Connectivity Interfaces Audio Presentation Graphics endering Video Presentation PNX85500 / HotChips / C.Osborne,. Karge 12

13 Challenging Bandwidth and Latency Needs Cost pressure only allows 2 x 16 DD Limiting gross bandwidth to 4.2 Gbytes/sec Originally the TV550 system was expected to need 64-bit DD interface equiring high-bandwidth and low-latency Processors for flexible processing: requiring low-latency to minimise cache miss penalty Hardware traffic mostly predictable: requiring high-bandwidth Innovative solutions Processors supported by specific arbitration settings in infrastructure Hardware units and VLI pre-fetch memory accesses Local caches/buffers Video streaming between IP functions Memory Subsystem with Arbitration and Buffering Critical Critical Tolerant Critical Tolerant Critical Tolerant Tolerant Tolorant MIPS24K Embedded Control CPU Digital Video Decoder FC Processor FC Coprocessor AVDSP Processor Audio Processor Video Comp. Pipe(s) Video Scaler(s) PNX85500 / HotChips / C.Osborne,. Karge 13

14 Assuring fast Silicon Bring-Up Extensive suite of verification methods Various abstraction levels in simulation of IP functionality and connectivity SoC infrastructure performance Emulation of representative Software and Hardware 300 million gates of IC emulation capacity System tuning and performance sign-off k frames of HD video before tape out Advance system software development Emulation All main use-cases had been brought up on the emulator before silicon Software was ready when silicon arrived Arbitration and tuning settings had been verified => Very rapid silicon bring-up PNX85500 / HotChips / C.Osborne,. Karge 14

15 PNX85500 Silicon TSMC's 45nm Low Power (LP) process technology 27 mm Flip Chip BGA Package Power Consumption < 7 att No active cooling required PNX85500 / HotChips / C.Osborne,. Karge 15

16 Introduction System Integration More TV System on a Chip PNX85500 TV Solution Design Challenges Architecture Memory Bandwidth and Latency Verification and Emulation High-lighted Features Conclusions PNX85500 / HotChips / C.Osborne,. Karge 16

17 Complex SoC made up by Complex IPs Example: Video Scaler STDI De-interlacer VCA MPEG Artefact eduction AHSC Horizontal scaler TN Temporal Noise eduction PCO Projection data for film detector PNX85500 / HotChips / C.Osborne,. Karge 17

18 Complex SoC made up by Complex IPs Example: Video Composition Pipe PCTI Peaking-based Color Transient Improvement SKC Skin-tone Control VSH Video Sharpening BSKY Blue-Sky Enhancement DI2D 2-Dimensional Backlight Dimming PNX85500 / HotChips / C.Osborne,. Karge 18

19 Motion Accurate Picture Processing Film Judder Cancellation + Motion Blur eduction A B Original Movie 24 frames per second Typical TV at 50 or 60 frames per second (with movie judder ) PNX85500 output at 120 frames per second; after movie judder removal A 24 Hz film A A A B B B High quality smooth, natural-looking motion - analysed and created - in real-time, for HD video content - at 120 frames per second PNX85500 / HotChips / C.Osborne,. Karge 19

20 Improved Picture Quality at educed Power 2D Local Dimming Processing Histogram Video input PNX85500 Backlight output FC Processor Image Analysis Backlight calculation Video output Video Gain + = Perceived output Video on backlight educe LCD TV s backlight power by about 50% Significant increase of contrast and black level Histogram measurement and pixel processing done in H-IP Flexible processing of VLI processor for image analysis and backlight calculation PNX85500 / HotChips / C.Osborne,. Karge 20

21 Introduction System Integration More TV System on a Chip PNX85500 TV Solution Design Challenges Architecture Memory Bandwidth and Latency Verification and Emulation High-lighted Features Conclusions PNX85500 / HotChips / C.Osborne,. Karge 21

22 Conclusions PNX85500: the world s first DTV SoC in 45nm Very high level of integration Award-winning 120 Hz processing in front-end TV SoC Enabling global chassis, single platform Performance critical Iterative analysis and optimisation through design cycle Solving challenging demands on memory latency Verification challenge Very high level of integration creates challenges in interdependency and complexity Extensive use of prototyping using emulation and FPGA First silicon arrived in Q Successful customer demonstrations within 2 weeks of first silicon! hat s next? Higher integration levels, lower system cost Improved picture quality, increased frame rates and resolution New video features 22 PNX85500 / HotChips / C.Osborne,. Karge

23 Questions PNX85500 / HotChips / C.Osborne,. Karge 23

24 PNX85500 / HotChips / C.Osborne,. Karge 24