High Performance Processor Architecture

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1 High Performance Processor Architecture Neeraj Goel 2004csz8035 Embedded System Group Dept. of Computer Science and Engineering Indian Institute of Technology Delhi

2 Outline Introduction History and Future prediction Pentium 4 features Pipelining Superscalar features Hyper-Threading Conclusion and future

3 Moore s Law Intel Microprocessors(source:

4 Intel s Processors : past and Current Year of Introduction Transistors , , , ,000 Intel386 processor ,000 Intel486 processor ,180,000 Intel Pentium processor ,100,000 Intel Pentium II processor ,500,000 Intel Pentium III processor ,000,000 Intel Pentium 4 processor ,000,000 Intel Itanium processor ,000,000 Intel Itanium 2 processor ,000,000

5 How to increase performance Pipelining Breaking a large system in number of stages Instruction level parallelism Software codes are serially written Independent instructions can be executed parallel Large number of function units required Thread level parallelism Application are written with threads Operating system can have threads Different application on different thread

6 How Pentium is getting high performance Rapid execution, more pipelining stages Out of order execution Speculative execution Hyper threading Trace cache Store to load forwarding enhancements

7 Pipelining The concept of splitting a job into sub-processes in which the output of one sub-process feeds into the next. A mechanical example of a pipeline is a washer/dryer system for clothing.

8 Pipelining The concept of splitting a job into sub-processes in which the output of one sub-process feeds into the next. A mechanical example of a pipeline is a washer/dryer system for clothing. More stages means more throughput also more latency Issue : All stages should be of almost equal delay otherwise slowest stage will determine clock cycle Fetch Decode Execute Write back

9 Superscalar Architecture We can have large number if functional units but program is serial Will multiple instruction fetch solve the problem?

10 Superscalar Architecture We can have large number if functional units but program is serial Will multiple fetch solve the problem? Issues Dependencies Branches

11 Speculative Execution Situation: There is pipeline of 20 stages and all are waiting for branch to be resolved Effect: Benefits of pipelining and superscalar will vanish at branch instructions? Solution?

12 Speculative Execution Situation: There is pipeline of 20 stages and all are waiting for branch to be resolved Effect: Benefits of pipelining and superscalar will vanish on branches? Execute both if and else instructions simultaneously Discard wrong one when result of branch come

13 Thread level parallelism Multi-processors Supercomputers Chip Multi-Processing Dual core chips like Intel s Xeon Simultaneous Multi-threading One processor and multiple thread Different from multi-programing and multi-tasking

14 Hyper-threading Makes a single processor appear as multiple logical processors Each logical processor keeps a its own copy of the architecture state OS view the logical processors as physical processors Logical processors share a single set of physical resources

15 Hyper-threading Makes a single processor appear as multiple logical processors Each logical processor keeps a its own copy of the architecture state OS view the logical processors as physical processors Logical processors share a single set of physical resources

16 Conclusion and Future Future processor will need more performance - higher clock speed Not possible with shrinking device dimensions Need architectural solutions SMP and CMP will be solution More instruction level parallelism can be exploited using compiler techniques

17 Thank You Thank You

18 Backup Backup

19 Source Files neeraj/doc

20 Some Definitions Cache An on chip memory with very less access time Cost is more usually required data can be placed there Clock speed Mentioned in MHz and GHz MHz : Million instructions per second Buses Data, Address and Control Bus width -> Number of parallel bits that can be accessed

21 Block Diagram of Pentium 4 HU810 Semina

Lecture 11: Multi-Core and GPU. Multithreading. Integration of multiple processor cores on a single chip.

Lecture 11: Multi-Core and GPU Multi-core computers Multithreading GPUs General Purpose GPUs Zebo Peng, IDA, LiTH 1 Multi-Core System Integration of multiple processor cores on a single chip. To provide