Integrated Protection and Careful Layout Protect PoE Systems from EOS and ESD

Transcription

1 ISSUE: March 2010 Integrated Protection and Careful Layout Protect PoE Systems from EOS and ESD by A. Bremond and C. Appere, STMicroelectronics, Tours, France Computer-based equipment is quite often vital for today s way of life either for business or personal activities. We use computers in voice or data communication systems, gaming stations, etc., and this equipment is generally powered by ac power and connected to data networks. As a result, a multitude of small power supplies are plugged into the ac mains with cables snaking everywhere. To suppress this big mess of wires, while meeting requirements for the transfer of both power and data, the IEEE-802.3af standard defines equipment for supplying power via an Ethernet cable. But as is usually the case when electrical devices are connected by cables, those devices are subject to interference from electrostatic discharge (ESD) and electrical over stresses (EOS). This article reviews the operating principles of Power over Ethernet (PoE) systems, describes the EOS and ESD standards that PoE systems must comply with, and presents a new, more costeffective solution for PSE-side protection that reduces component count and pc board-space requirements, while also improving protection of the PSE controller. For the given solution, laboratory tests have been successfully performed and the most significant test is briefly explained. The importance of PCB layout in suppressing ESD is also discussed. IEEE-802.3af Recommendation IEEE 802.3af defines a category of equipment at the switch or hub level that is referred to as the Power Sourcing Equipment (PSE). Upon request, the PSE delivers a voltage of 44 to 56 V dc over the Ethernet cable to another type of equipment, which the IEEE standard refers to as a Powered Device (PD) (Fig.1). When the PD is plugged into the Ethernet cable, the application of power to that PD is performed in three steps. The first step is detection; the PSE learns that a PD is asking for energy. The second step is classification: the PD explains what power level it is looking for. The third and final step is when the PSE actually delivers power to PD. According to IEEE802.3af, the maximum power that can be delivered by the PSE is 15.4 W, and after possible cable losses are accounted for, a maximum of about 13 W is available to the PD. Under the recently ratified IEEE 802.3at high-power version of the PoE standard, those power levels are essentially doubled so that a maximum of 30 W will be delivered by the PSE with up to 25.5 W available to the PD How2Power. All rights reserved. Page 1 of 9

2 Figure 1. Topologies defined by IEEE802.3af standard. Figure 1 shows two methods of integrating PoE functionality within a network. To adapt the PoE to today s existing equipment, a power rack is inserted, at the switch/hub location, between the PSE and Ethernet cable by using the spare pairs of the cable (see fig.1 Midspan PSE, Alternative B). However, with newly developed equipment, this power function is incorporated directly into the switches or hubs (see fig.1 Endpoint PSE, Alternative A and B). Standards For Compliance Power supplies and plug-in peripherals are faced with overvoltage risks, and standards have to be applied to make the equipment reliable within their environments and to ensure their market qualifications. There are two standards that most PoE-equipped systems must meet to ensure their ESD and EOS robustness. The first is the ESD immunity standard, IEC standard level 4, which subjects the equipment under test to 8 kv via direct contact and 15 kv via air discharge. The second is the IEC surge immunity standard, which simulates the industrial EOS. As EOS are more energetic than ESD, the choice of protection is dictated by the EOS requirements. Although a protection circuit designed for EOS is able to handle the power generated by both kinds of overvoltage, it is mandatory to take into account the unique characteristic of ESD (high di/dt) during the printed circuit board (PCB) layout. Under the IEC standard (see figure 2), equipment is tested by applying a combination wave (a 1.2/50-µs voltage waveform in open load and a 8/20-µs current waveform in short circuit) in the cable lines within different combinations (S1 and S2 positions). (The two time periods specified for the current and voltage waveforms refer to rise and fall times.) The voltage waveform is applied through 42 Ω (40 Ω resistor+ 2 Ω of generator internal resistance) with an amplitude of 0.5 (level 1) or 1 kv (level 2) depending on the installation classification. For the security of the equipment, the 1-kV level 2 testing is mainly used as this enables the system to withstand up to 24 A peak How2Power. All rights reserved. Page 2 of 9

3 Figure 2. IEC test definition. With equipment designed for severe environments, level 3 (2-kV) testing may be used and this provides protection at currents up to 48 A. Protection solution As defined in the previous section, both PD and PSE equipment must be protected against IEC level 1 or 2 conditions, and the equipment PCB layouts have to be optimized to make them ESD safe. Figure 3 shows a schematic complying with the level 2 requirement. As power controller ICs are not able to withstand the 1-kV peak imposed during surges, protection devices have been added. This diagram shows a PSE (switch or hub) connected to four PDs (a four-port configuration is typical for PSE equipment). In both sides, the protection is assumed by Transil (clamping-effect based) protection devices How2Power. All rights reserved. Page 3 of 9

4 Figure 3: PSE and PD protection schematic. To minimize the PCB area required on the PSE side, the four protection functions have been integrated within a single device, the PEP from STMicroelectronics. The PEP combines four Transil devices in an SO-8 package. Its clamping action starts higher than the maximum PoE operating voltage of 56 V, and its leakage current remains lower than 1 µa even when ambient temperature reaches 85 C. The device has an intrinsic capacitance of 60 pf, which helps to suppress unwanted high-frequency disturbances (Figure 4). As is usually the case, it is recommended that designers include 100 nf of capacitance to filter the power rail. Another important parameter to take into account is the remaining voltage across the PoE controller IC during the surge. A preliminary study of available controller ICs has shown that the absolute max rating for such a circuit is above 100 V, and the PEP guarantees that its clamping voltage never exceeds this value even under the worst-case test conditions (IEC kv). In contrast, the standard SMAJ58A transient voltage suppressor (TVS) specifies a clamping voltage of 121 V max., which does not guarantee protection of the controller IC. Thanks to its SO-8 package, the PEP requires only half of PCB area that would be occupied by four SMAJ58A TVSs as shown in Figure How2Power. All rights reserved. Page 4 of 9

5 Figure 4: PEP main characteristics Figure 5: Space saving with PEP How2Power. All rights reserved. Page 5 of 9

6 In the cases where level 3 protection is required, the surge current is 48 A. When using the SMxJ58A TVS, there are three package sizes that offer different current ratings. The SMAJ is specified at 19 A, the larger SMBJ is specified at 33 A, and the even larger SMCJ58A is specified at 83 A. Unfortunately, the maximum clamping voltage is 121 V for all three of these devices. Clamping voltage aside, the PEP can protect two power supplies in just 31 mm² of PCB area versus 76 mm² for two SMC packages. It is mandatory to adapt the layout to get perfect current sharing between both internal PEP01 Transil devices as shown in Figure 6. IEC tests Figure 6: PCB layout for PEP to be compliant with IEC level 3. Figure 7 shows the test schematics used to quantify the behavior of the PEP when subjected to the IEC combination wave level 2 (1 kv). The attached curves give the Is current flowing through the clamping device and the remaining voltage Vr across it. Although the breakdown voltage of the tested device was V BR = 70 V at I R = 1 ma, the remaining voltage is 95 V peak for a peak surge current of 23 A. This will guarantee the safety of the PoE controller in the face of EOS surges How2Power. All rights reserved. Page 6 of 9

7 Figure 7. Voltage and current through PEP during the 1-kV surge. ESD In case of ESD surges, the remaining overvoltage seen by the PoE controller is the sum of the Transil clamping voltage and the voltage drops generated by the parasitic inductances L of the PCB traces (Figure 8). When subjected to the high di/dt of an ESD event, the track length between the protection device and the protected lines can generate up to 30 V per mm. However, laying out the PCB with a four-point connection as shown in Figure 8 causes a cancellation of these parasitic voltages How2Power. All rights reserved. Page 7 of 9

8 Figure 8: Optimization of PCB design to minimize the effect of ESD. (Refer back to Figure 4 for the internal schematic diagram of the PEP ) Conclusion In PoE systems, both the PSE and PD have to be protected against surges and must be compliant with the ESD standard IEC level 4 and the EOS standard IEC levels 2 and 3 by using 2 outputs in parallel. Clamping-based protection devices are chosen to assume this function. For the PD side, a classic SMAJ58A Transil can be used. Meanwhile, for the PSE side, STMicroelectronics s PEP provides a solution that is optimized for cost and PCB area reduction, while also satisfying the PSE controller IC s need for clamping action below 100 V during EOS. The high di/dt characteristic of ESD events must be addressed through proper layout of the PCB. To aid the equipment designer, a PSpice model is available for the PEP , which will allow designers to perform complete system simulations How2Power. All rights reserved. Page 8 of 9

9 About the Authors André Bremond was with STMicroelectronics in Tours, France from 1987 through 2009 where he served as a telecom application lab manager. André is a graduate of the Conservatoire National des Arts et Métiers. Cédric Appere joined STMicroelectronics in Tours, France in 2000 and currently serves as a telecom application engineer. Cédric is a graduate of Ecole Centrale d'electronique. For further reading on Power over Ethernet, see the How2Power Design Guide and search the Application category and select the Networking subcategory How2Power. All rights reserved. Page 9 of 9