2GB Unbuffered DDR3 SDRAM SODIMM

Transcription

1 INDÚSTRIA ELETRÔNICA S/A 2GB Unbuffered DDR3 SDRAM SODIMM HB3SU002GFM8DMA33 (256M words x 64bits, 1 Rank) Documento No. HBS-HB3SU002GFM8DMA33-1-E Publicação: Setembro de 2010 EK

2 DATA SHEET 2GB Unbuffered DDR3 SDRAM SODIMM HB3SU002GFM8DMBA33 (256M words x 64bits, 1 Rank) Features 204 pin, small-outline dual inline memory module (SODIMM) 2GB (256Mx64) V DD = 1.5V +/ V V DDSPD = 3.0V to 3.6V Nominal and dynamic on-die termination (ODT) for data, strobe, and masks signals. Dual rank On-board I 2 C temperature sensor with integrated serial presence-detect (SPD) EEPROM. 8 internal device banks Fixed burst chip (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 onthe-fly (OTF) Fly-by-topology Terminated control, command, and address bus. 8 components DDR3 FBGA PCB height: 30,0 mm Lead pitch: 0,6 mm Lead-free Rohs Compliant Operation Temperature T Case de 0 o C T A +70 o C 2

3 General Information Part Number Data Rate Mbps (max.) JEDEC components classsification (CL-tRCD-tRP) HB3SU002GFM8DMA DDR (9-9-9) Board dimentions 204-pin SODIMM (lead-free) Contacts Gold Component MT41J256M8HX-15E:D Pin Description Pin Name A0 to A14 A10 (AP) A12(/BC) BA0, BA1, BA2 DQ0 to DQ63 RAS# CAS# WE# S0#, S1# CKE0, CKE1 CK0 to CK1 CK0# to CK1# DQS0 to DQS7, DQS0# to DQS7# DM0 to DM7 SCL SA0 to SA2 VDD VDDSPD VREFCA VREFDQ VSS VTT RESET# ODT0 to ODT1 NC SDA EVENT# NU Function Address Input Row Address A0 to A14 Column Address A0 to A9 Auto Precharge Burst chop Bank select address Data input/output Row address strobe command Column address strobe command Write Enable Chip Select Clock Enable Clock input Differencial clock input Input and output data strobe Input mask Clock input for serial PD Serial address input Power for internal circuit Power for serial EEPROM Reference voltage for CA Reference voltage for DQ Ground I/O termination supply for SDRAM Set DRAM to known state ODT control No connection Serial Data Temperature event Not Used 3

4 Pin Configuration Pin Func Pin Func Pin Func Pin Func Pin Func 1 VREF 42 DQ21 83 A VDD 165 DQ49 2 VSS 43 VSS 84 A NC 166 DQ53 3 VSS 44 VSS 85 A9 126 VREFCA 167 VSS 4 DQ4 45 DQS2# 86 A7 127 VSS 168 VSS 5 DQ0 46 DM2 87 VDD 128 VSS 169 DQS6# 6 DQ5 47 DQS2 88 VDD 129 DQ DM6 7 DQ1 48 VSS 89 A8 130 DQ DQS6 8 VSS 49 VSS 90 A6 131 DQ VSS 9 VSS 50 DQ22 91 A5 132 DQ VSS 10 DQS0# 51 DQ18 92 A4 133 VSS 174 DQ54 11 DM0 52 DQ23 93 VDD 134 VSS 175 DQ50 12 DQS0 53 DQ19 94 VDD 135 DQS4# 176 DQ55 13 VSS 54 VSS 95 A3 136 DM4 177 DQ51 14 VSS 55 VSS 96 A2 137 DQS4 178 VSS 15 DQ2 56 DQ28 97 A1 138 VSS 179 VSS 16 DQ6 57 DQ24 98 A0 139 VSS 180 DQ60 17 DQ3 58 DQ29 99 VDD 140 DQ DQ56 18 DQ7 59 DQ VDD 141 DQ DQ61 19 VSS 60 VSS 101 CK0 142 DQ DQ57 20 VSS 61 VSS 102 CK1 143 DQ VSS 21 DQ8 62 DQ3# 103 CK0# 144 VSS 185 VSS 22 DQ12 63 DM3 104 CK1# 145 VSS 186 DQS7# 23 DQ9 64 DQ3 105 VDD 146 DQ DM7 24 DQ13 65 VSS 106 VDD 147 DQ DQS7 25 VSS 66 VSS 107 A DQ VSS 26 VSS 67 DQ BA1 149 DQ VSS 27 DQS1# 68 DQ BA0 150 VSS 191 DQ58 28 DM1 69 DQ RAS# 151 VSS 192 DQ62 29 DQS1 70 DQ VDD 152 DQS5# 193 DQ59 30 RESET# 71 VSS 112 VDD 153 DM5 194 DQ63 31 VSS 72 VSS 113 WE# 154 DQS5 195 VSS 32 VSS 73 CKE0 114 S0# 155 VSS 196 VSS 33 DQ10 74 NC 115 CAS# 156 VSS 197 SA0 34 DQ14 75 VDD 116 ODT0 157 DQ EVENT# 35 DQ11 76 VDD 117 VDD 158 DQ VDDSPD 36 DQ15 77 NC 118 VDD 159 DQ SDA 37 VSS 78 NC 119 A DQ SA1 38 VSS 79 BA2 120 NC 161 VSS 202 SCL 39 DQ16 80 NF/A NC 162 VSS 203 VTT 40 DQ20 81 VDD 122 NC 163 DQ VTT 41 DQ17 82 VDD 123 VDD 164 DQ52 4

5 SPD (Serial Presence Detection) Address Function Data 0 Numeber of serial PD bytes written/spd device size/crc coverage 92 1 SPD revision 10 2 Key byte/dram device type 0B 3 Key byte/module type 03 4 SDRAM density and banks 03 5 SDRAM addressing 19 6 Module nominal voltage, VDD 00 7 Module organization 01 8 Module memory bus width 03 9 Fine timebase (MTB) dividend/divisor Medium time base (FTB) dividend Medium timebase (MTB) divisor SDRAM minimum cycle time (tck(min)) 0C 13 Reserved SDRAM/ CAS latencies supported, LSB 7E 15 SDRAM/CAS latencies supported, MSB SDRAM minimum/cas latencies time (taã (min)) SDRAM write recovery time (twr(min)) SDRAM minimum/ras to /CAS delay (trcd) SDRAM minimum row active to row active delay (Trrd) SDRAM minimum row precharge time (trp) SDRAM upper nibbles for tras and trc SDRAM minimum active to precharge time (Tras), LSB SDRAM minimum active to active/ auto-refresh time (trc), LSC SDRAM minimum refresh recovery time delay (Trfc), LSB SDRAM minimum refresh recovery time delay (Trfc), MSB SDRAM minimum internal write to read command delay (Twtr) 3C 27 SDRAM minimum internal read to precharge command delay (trtp) 3C 28 Upper nibble for tfaw Minimum four activate window delay time (tfaw) F0 30 SDRAM output drivers supported SDRAM refresh options Module thermal sensor SDRAM device type to 59 Reserved Module nominal height 0F 61 Module maximum thickness Reference raw card used Address mapping from edge connecter to DRAM to 116 Module specific section Module ID: manufacturer s JEDEC ID code, LSB Module ID: manufacturer s JEDEC ID code, MSB Module ID: manufacturing location 00 5

6 Address Function Data 120 Module ID: manufacturing date Module ID: manufacturing date to 125 Module ID: module serial number FF 126 Cyclical redundancy code (CRC) AB 127 Cyclical redundancy code (CRC) Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number 4D 139 Module part number Module part number Module part number 4D 142 Module part number Module part number Module part number Module part number FF 146 Module revision code Module revision code SDRAM manufacturer s JEDEC ID code LSB SDRAM manufacturer s JEDEC ID code MSB 2C 150 to 175 Manufacturer s specific data to 254 Intel extreme memory profile FF 255 Open for customer use FF [SPD for Intel Extreme Memory Profile] 176 Intel extreme memory profile ID string FF 177 Intel extreme memory profile ID string FF 178 Intel extreme memory profile organization type FF 179 Intel extreme memory profile revision FF 180 Medium timebase (MTB) dividend for profile 1 FF 181 Medium timebase (MTB) divisor for profile 1 FF 182 Medium timebase (MTB) divisor for profile 2 FF 183 Medium timebase (MTB) divisor for profile 2 FF 184 Reserved for global byte FF [For Profile 1] 185 Module VDD voltage level FF 186 SDRAM minimum cycle time (tck(min)) FF 187 SDRAM minimum /CAS latencies time (taa (min)) FF 188 SDRAM /CAS latencies supported, LSB (CL MASK) FF 189 SDRAM /CAS latencies supported, MSB (CL MASK) FF 190 Minimum CAS write latency time (tcwl(min)) FF 191 SDRAM minimum row precharge timte (trp) FF 192 SDRAM minimum /RAS to /CAS delay (trcd) FF 193 SDRAM write recovery time (twr(min)) FF 6

7 194 SDRAM upper nibbles for tras and trc FF 195 SDRAM minimum active to precharge time (tras), LSB FF 196 SDRAM minimum active to active / auto-refresh time (trc), LSB FF 197 Maximum average periodic refresh interval (trefi), LSB FF 198 Maximum average periodic refresh interval (Trefi), MSB FF 199 SDRAM minimum refresh recovery time delay (trfc) LSB FF 200 SDRAM minimum refresh recovery time delay (trfc) MSB FF SDRAM minimum internal read to precharge command delay FF 201 (trtp) 202 SDRAM minimum row active to row active delay (trrd) FF 203 Upper nibble for Tfaw FF 204 Minimum four activate window delay time (tfaw) FF 205 SDRAM minimum internal write to read command delay (twtr) FF 206 Write ro read & read to write command turn-around time pull-in FF 207 Back to back command turn-around time pull-in FF 208 System address/ command rate (1N or 2N mode) FF 209 Auto self-refresh performance (sub 1x refresh and IDD6 impacts) FF 210 to 218 reserved FF 219 Vendor personality byte FF 220 Module VDD voltage level (extreme settings) FF 221 SDRAM minimum cycle time (tck (min)) FF 222 Minimum CAS latency time (taa (min)) FF 223 SDRAM / CAS latencies supported, LSB (CL MASK) FF 224 SDRAM /CAS latencies supported, MSB (CL MASK) FF 225 Minimum CAS write latency time (tcwl(min) FF 226 SDRAM minimum row precharge time (trp) FF 227 SDRAM minimum / RAS to /CAS delay (trcd) FF 228 SDRAM write recovery time (twr(min)) FF 229 SDRAM upper nibbles for tras and trc FF 230 SDRAM minimum active to precharge time (tras), LSB FF 231 SDRAM minimum active to active / auto-refresh time (trc), LSB FF 232 Maximum average periodic rrefresh interval (trefi), LSB FF 233 Maximum average periodic refresh interval (trefi), MSB FF 234 SDRAM minimum refresh recovery time delay (trfc), LSB FF 235 SDRAM minimum refresh recovery time delay (trfc) MSB FF SDRAM minimum internal read to precharge command delay FF 236 (trtp) 237 SDRAM minimum row active to row active dealy (trrd) FF 238 Upper nibble for tfaw FF 239 Minimum four activate window delay time (tfaw) FF 240 SDRAM minimum internal write to read command delay (twtr) FF 241 Write to read & read to write command turn-around time pul-in FF 242 Back to back command turn-around time pull-in FF 243 System address/ command rate (1N or 2N mode) FF 244 Auto self-refresh performance (sub 1x refresh and IDD6 inpacts) FF 245 to 253 Reserved FF 254 Vendor personality byte FF 7

8 Block Diagram 8

9 Operating Conditions Symbol Parameter min Nom Max Unit Notes V DD VDD supply voltage V I VTT Termination reference current fro VTT ma VTT Termination reference voltage (DC) - command/address bus I I I VREF Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 0.95V (All other pins not under test = 0V) VREF supply leakage current; VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) 0.49 VDD - 20mV 0.5 VDD 0.51 VDD + 20mV Address inputs, RAS#, CAS#, WE#, S#, CKE, ODT, BA, CK, CK# DM V 1 ua ua TA TC Module ambient operating temperature DDR3 SDRAM component case operating temperature commercial ºC 2 commercial ºC 3 NOTES 1 VTT termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins. 2 TA and TC are simultaneous requirements. 3 The refresh rate is required to double when 85 C < TC 95 C. Temperature Sensor with Serial Presence-Detect EEPROM The temperature from the integrated thermal sensor is monitored and converts into a digital word via the I2C bus. System designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC standard No. 21-C page 4.7-1, Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor. 9

10 Physical Dimention 10