Recent Advances in Electrical Engineering

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1 Wide Load Range High Efficiency Design Consideration of a Self- Driven Synchronous Rectified Phase-Shifted Full-Bridge Converter for Data Center Application SEILAY CETIN Technology Faculty Pamukkale University 0070 Kinikli Denizli TURKEY scetin@pau.edu.tr Abstract: - This paper proposes a high frequency design consideration to obtain high efficiency over wide load range in the self driven phase-shifted full-bridge converter for data center application. In the proposed approach, soft switching analysis of lagging leg in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is presented. In addition, optimum dead time and appropriate operation mode determination taking into consideration the load condition is presented. Finally, optimum design key parameters is extracted and a saber simulation operating at 80 khz and rated 1 kw (1-83 A) is carried out to verify proposed theoretical analysis and evaluations. Key-Words: -Phase shifted full bridge converter, soft switching, CCM and DCM operation, high efficiency. 1 Introduction Recently, research in power converters used in data center has focused on high efficiency over wide load range due to consuming energy sources in the world. Besides, in data center or server power system, increasing energy demand and rising energy price require high efficiency power conversion. In order to obtain more reliable system, data center or server power systems used in information technology usually uses parallel structure sharing total load in case of any failure. Thus, high efficiency power conversion over wide load range is the important key parameter in converter design to save energy and reduce cooling size of the overall power systems [1]-[6]. Phase shifted full bridge (PSFB) converter is widely used for server power systems or data center applications due to its high conversion efficiency, high power density, simple control structure and low electromagnetic interface (EMI) []-[0]. In general, PSFB converter is used as second stage DC-DC conversion with low output voltage and high output current of a two stage AC-DC converter. In these systems, total conversion losses are dominated by rectifier conduction losses under heavy load conditions so optimum design taking into consideration the secondary side conduction losses will help to achieve the high conversion efficiency [4]. However, under the light load conditions, switching and core losses are the main part of the total losses [5]-[7]. Because zero voltage switching (ZS) turn-on of the primary switches depends on load condition and lagging leg switches are turned on with hard switching under the light load conditions. In order to improve light load efficiency, different methods are proposed in the literature [7]- [11]. However, these methods require additional circuit components and complex control circuit design to achieve extended ZS turn-on for the lagging leg switches. However, as given in [5] and [1], the operation in DCM under light load condition is the simple and another option to maintain ZS turn-on of the lagging leg switches and reduce core loss by extended dead time. Using synchronous rectifier (SR) is common way to cope with high conduction losses especially in the low output voltage applications. In [4], a design evaluation which uses parallel connected SRs in order to obtain best efficiency has been proposed and 99% efficiency has been achieved at 5 khz operation frequency. However, active gate driver design for parallel connected SRs increases complexity and makes system heavy because of the need of large PCB surface to place SRs drivers and their isolated power supply. Obviously, self-driving method seems more attractive compared to active gate drive method due to its simplicity and easy implementation especially when SRs are connected in parallel. arious self-driving methods using current driven or voltage driven technique for low output voltage and high output current applications ISBN:

2 have been proposed [14],[17]-[0]. The voltage driven method uses directly power transformer or an auxiliary winding to generate driving signals and so it results in cheap and simple solution. In [0], a method using an auxiliary winding to drive SR has been proposed; proposed technique provides conduction of both SRs when primary voltage is zero during dead time compared to conventional self-driver method using directly secondary voltage of the power transformer. In this paper, a self-driven synchronous rectified PSFB converter design approach in order to obtain high efficiency over wide load range for data center application is presented. Detailed ZS analysis of lagging leg in CCM and DCM is presented to determine the appropriate operation mode and optimum dead time taking into consideration the load conditions. Parallel connected SRs are used for center taped rectifier on the secondary side to reduce high conduction losses. A self-driven circuit is considered to avoid the need for an additional active control circuitry on the secondary. The self-driver method proposed in [0] is applied to generate control signals for the parallel connected SRs. Finally, a simulation with 1kW (1-83A) output power and operating at 80 khz has been carried out to validate theoretical performance analysis and evaluations. Soft Switching Analysis of Lagging Leg Switches in CCM and DCM Figure 1. The power stage circuit diagram of PSFB PWM DC-DC converter. In the analysis, semiconductor devices, inductors and capacitors are accepted as ideal. It is also assumed that output inductance is high enough and its current is constant for one switching cycle. The equivalent circuit diagrams and also related key waveforms achieving ZS transition of the lagging leg switches in CCM and DCM are shown in Figure and Figure 3, respectively. a) The general operation principle of PSFB converter with center tapped rectifier is well known and proposed in many papers in the literature [3], [4] so the analysis given here is focused on the interval achieving ZS turn-on of the lagging leg switches. The power stage circuit diagram of synchronous rectified PSFB PWM DC-DC converter is shown in Figure 1. Here, S 1 -S 4 are the primary side switches and they include antiparallel diodes and parasitic capacitors. SR 1 and SR represent the parallel connected synchronous rectifier in order to reduce conduction losses. L M is the mutual inductance, L s is the equivalent inductance which sum of the total leakage inductance and additional inductance series connected to the primary side. TR is the high frequency power transformer with N turns ratio, L o and C o are output filter components, in is the input voltage source and o is the output voltage. (b) ISBN:

3 Figure. The equivalent circuit diagram (a) and related key waveforms achieving ZS transition of the lagging leg switches in CCM. (a) (b) Figure 3. The equivalent circuit diagram (a) and related key waveforms achieving ZS transition of the lagging leg switches in DCM. In CCM, before S is turned-off, S 1 is turned-off so the output capacitor of the S 1 and S 4 is charged and discharged, respectively. Then converter starts to work in freewheeling mode; primary side of transformer is short circuited by conduction S 4 MOSFET and antiparallel diode of opposite side S MOSFET. Therefore, there is no power transfer from the input to the output. After the S is turned off, primary current charges and discharges the output capacitor of S and S 3, respectively. The antiparallel diode of S 3 conducts after the output capacitor of S 3 discharges completely and ZS turnon for S 3 can be achieved. However, during this stage both SR1 and SR are turned on for output current commutation so secondary side of transformer is short circuited and there is no power transfer from the input to the output in this interval. Therefore primary current decreases fastly and only the stored energy in the L s should be sufficient to completely charges/discharges the output capacitor of the lagging leg switches. 1 1 LI s p Claggin (1) In above equations, I p and C lagg defines the critical primary current, I p-cr, and equivalent output capacitance during the resonance, respectively. Thus, required critical current value, I p-cr, or load condition to charge/discharge the output capacitors of the switches can be determined by Clagg Ip cr =. () in Ls In order to achieve ZS turn-on, dead time should be least one quarter of the resonance period as follows Tr π δ = = LC (3) R CCM s lagg 4 During the output current commutation, there is no power transfer from the input to the output due to both SRs conduction at the same time and this time is defined as lost duty ratio time interval. Therefore voltage gain can be written as in o = (D D). (4) N Where, ΔD is the lost duty ratio including δ R-CCM, difference between total duty ratio, D, and ΔD gives the effective duty ratio, D eff. LsIp3fs Deff = D δ R CCM (5) in Where I p3 is the primary current value when capacitor charges/discharges completely and it can be defined as ip3 = Ip Ip cos ω(t t ). (6) In DCM, the current flowing through the SRs flows discontinuously so both SRs should be turned off to prevent the discharge of output filter capacitor with the conduction of SRs. Therefore, the magnetizing inductance of the transformer participates to the resonance between L S and the output capacitors of the primary switches and also SRs. The output capacitor of SRs also has to be charged/discharged while the output capacitor of the lagging leg switches charges/discharges in order to provide ZS turn-on of the lagging leg switches since SRs are off during freewheeling interval and their output capacitors are reflected to the primary side in DCM operation as shown in Figure 3 (a). In this operation, the interval for the output current commutation between SRs doesn t occur and the ISBN:

4 secondary of the transformer is not short-circuited compared to CCM operation principle. Therefore the current stored in magnetizing inductance is enough to charges/discharges the output capacitors easily compared to conventional CCM operation. However, the charge/discharge time of the capacitors is larger than the CCM operation due to the small current value in L m so extended delay time can be achieved the ZS of the lagging leg switches in DCM operation [5]. Required energy to achieve ZS of lagging leg switches can be written as 1 1 CSR L I (C + ). (7) M LM cr lagg in n Where I LM-cr represents the critical magnetizing current value to achieve ZS and it can defined as I C + C / n la g g SR LM cr =. (8) in LM In the above equations, L s is neglected because it is very small near L M. The delay time to be extended should be least one quarter of the resonance period as defined by Tr π δ = = L (C + C / n ). R DCM M lagg SR 4 (9) III. Dead Time Optimization and Appropriate Mode Selection Under heavy load conditions, ZS turn-on can be achieved easily. However, if primary current reaches zero or change its direction before dead time completes, primary current with inverse direction recharges the output capacitors as shown in Figure 4(a). In similar way, when the load gets smaller, output capacitors cannot be charged/discharged completely before primary current reaches zero as shown in the Figure 4(b). Therefore lagging leg switches are turned on with hard switching under light load conditions and with no optimized dead time. This load dependence problem is the well known disadvantage of PSFB DC-DC converter. Some conventional solutions are usually applied to solve this problem like increasing L s and adding additional capacitors to the output capacitors. However, these solutions change the conduction and switching losses in a different way. Therefore, detailed dead time optimization taking into consideration overall efficiency and wide load range can help to cope with the load dependent ZS turnon operation of lagging leg switches at the design stage. (a) (b) Figure 4. ZS turn-on of S3 with the large dead time (a) and under the light load condition (b). A. CCM Operation: In the conventional design procedure, high efficiency is optimized according to the constant dead time giving desired voltage gain to regulate output voltage under the heavy load conditions. In this approach, ZS turn-on of the lagging leg switches can be achieved by suitable L s inductor determined for desired soft switching load range. Therefore ZS turn-on of the lagging leg switches depends on the dead time and L s inductance very strongly. Required dead time is also determined by the switch characteristics. In this study, SiC MOSFET and Cool MOSFET are evaluated as switch component due to their high frequency operation capability compared to IGBT. In these switches, dead time between S and S 3, t dead-lagg, can be defined by tdead lagg td off + trv. (10) In the formula, t d-off defines the turn-off delay time and t rv is the rising time of the switch voltage. The dead time, t dead-lagg, should also be larger than ZS time interval and should be ended before ISBN:

5 primary current reaches zero. The time interval, primary current reaches zero, can be defined as total of the ZS time interval and linear region shown in Figure (b). This time interval can be defined as follows LI s p3 tlinear = (11) in Table 1 shows the calculated performance comparison of Cool MOSFET and SiC MOSFET based on dead time requirement and loss. Each switch is selected for 400 DC input voltage, 1 kw output power and 80 khz switching frequency. In the calculations, transformer turns ratio is selected as N:5 and snubber inductance L s =10 μh. The graphic given in Figure 5 shows the calculated maximum dead time variation as the function of L s and the critical primary current required for ZS of the lagging leg switches. The maximum dead time increases while L s increases and the critical primary current I p-cr decreases as shown in Figure 5. If desired ZS range of the lagging leg switches is determined until 60 % load condition, L s should be selected as 10 µh. increases slightly while L s decreases due to reducing critical load conditions. Under the critical load condition, MOSFETs are turned on with hard switching. However, SiC MOSFETs have small output capacitance so turn-on switching loss is not dominated so much compared to over wide L s range. However, under the 0% load condition, increasing switching loss seems more dominant than 60% and %100 load conditions. Figure 7 shows the conduction loss variation as function of L s, conduction loss changes very slightly, almost constant, over wide L s range because lost duty ratio changing is very small due to the small output capacitance of SiC MOSFETs. SiC MOSFETs presents the advantage of small lost duty ratio and low switching loss as well. Figure 6. The switching loss variation as the function of L s and the load condition. Figure 5. The maximum dead time variation as the function of L s and the critical primary current. According to calculation results dead time for lagging leg switches can be selected as 160 ns to achieve ZS turn-on until the 60% load condition. L s inductance variation effects on conduction and switching loss over wide load range should be taken into account to obtain best efficiency for all load conditions. Figure 6 shows the switching loss over wide load range as function of L s, switching loss Figure 7. The conduction loss variation as the function of L s and the load condition. B. DCM Operation: ISBN:

6 In DCM operation, ZS of lagging leg can be achieved by extended dead time for lighter than 1% load condition as proposed in [5]. In this approach, effective duty ratio should be reduced according to voltage gain and necessary dead time should be determined to charge/discharge the output capacitors of the lagging leg switches and SRs. The voltage conversion ratio can be found by the voltage-sec balance on the output inductor as follows: o D = 4I L f n(d + D + ) in o o s o (1) If solving (1) for D, it can be obtained as D = n o in fil s o o o o (1 n ) in. (13) Stored energy increases while L m and output capacitors of the lagging leg switches and SRs decrease. Thus SiC MOSFETs which have small output capacitors can help to reduce the need of the large energy stored in L m to achieve ZS turn-on transition compared to Cool MOSFETs. The required dead time for DCM operation can be calculated by (9). Figure 8 shows switching loss variation according to load condition in CCM and CCM+DCM operation. DCM operation maintains the ZS operation under the 60% critical load condition and switching loss is lower compared to CCM operation condition. However, In DCM operation, SRs should be turned off to prevent discharge of the output filter capacitor through the SRs. This results in high conduction losses due to the conduction of the body diodes. Therefore DCM operation under 60% load condition is not possible to obtain high efficiency. Figure 8 Switching loss comparison of CCM and CCM+DCM operation over wide load range. Because both SR are off state, there is no output current commutation interval on the secondary side in DCM. The absence of output current commutation can compensate the body diode s conduction losses but it is still not enough compared to the parallel connected SRs implemented in this study. Figure 9 shows the conduction loss variation in CCM and CCM+DCM operations. DCM operation is applied under the 5% load condition and conduction loss suddenly increases when body diodes starts to conduct. However reducing core loss and the switching loss are dominated in overall loss and the efficiency under the 5% load condition is higher than CCM operation as shown in the Figure 10. Figure 9. Conduction loss comparison of CCM and CCM+DCM operation over wide load range. ISBN:

7 Figure 10. Efficiency comparisons of CCM and CCM+DCM operation over wide load range. According to the theoretical evaluation given above, synchronous rectified PSFB DC-DC converter designed to operate in CCM up to 5% and in DCM under %5 load condition to obtain best efficiency over wide load range. 3 Self-Driver Scheme The self-driven method uses directly power transformer to generate the control signals so its implementation is very simple, cheap and it has an advantage where power density/weight is important like electric vehicle and data centers applications. In this study, a self-driver proposed in [0] is used for parallel connected SRs. The circuit schematic of the self-driven circuit and its operational waveforms are given in Figure 14. Here, L e represents the sum of the leakage inductance of the auxiliary winding and stray inductance on the gate line. R g is the series resistor, R p is the parallel resistor to the gate terminal of SR, C GS is the equivalent gate-source capacitance of each SR. D 1 and D diodes provide for low conduction loss during turn-off. G 1 and G are the gate terminal of the parallel connected SRs and S point is the source terminal. Figure 14 The self driven circuit proposed in [0] and its operational waveforms. The auxiliary winding is implemented directly on the power transformer and reflected primary voltage to the auxiliary winding is used for the driving voltage. Here, it is supposed that auxiliary winding voltage is constant and equal to the g or - g to keep analysis simple. When auxiliary voltage is positive, upper side capacitor is charged and lower side one is discharged. When the lower side capacitor voltage is about zero, upper side SR1 is turned on and lower side SR is clamped to the negative drop voltage of D, D. When there is a voltage transition of the transformer, same current charges the lower side capacitor and discharges the other one. Thus SR is turned on and gate of SR1 is clamped to the negative drop voltage of D 1, D1. During the dead time, discharge of one capacitor charges the other capacitor and both capacitor voltage level can be kept at the same voltage level by using equal parallel balance resistors. Thus gate voltage of both SRs can be kept above the threshold voltage with a proper design while transformer voltage is zero. However, SRs should be turned-off under light load condition to operate in DCM and maintain ZS of the lagging leg switches. Therefore load current is sensed and compared a reference signal, if load current is lower than the reference current, control signals of SRs are removed so body diodes conduct the output current. 4 Simulation Results A server adapter with 1 output voltage and rated 1kW was simulated by Saber to validate the theoretical analysis given above. The simulated circuit diagram is shown in Figure 15. The components used in the simulation are listed in Table DC input voltage is applied to the ISBN:

8 input of self-driven synchronous rectified PSFB converter. Figure 15. Simulated circuit schematic of selfdriven synchronous rectified PSFB converter. Table 1. The Components used in server adapter prototype. SiC CMF010D Primary Switches 100, 4 A Secondary 5xIRFP4110Pbf Switches E65/3/7, n:5 Transformer N p =5, N s =1, N aux =1 1.1 μh, AMCC-30 Cut L o legs 10 μh L s L M C o 5.6mH 1xμF Ceramic Capacitor ΔI o 0.0 ZS turn on of S switch, in lagging leg, operating in CCM is shown in Figure 15. In the simulation results, dead time is fixed as 150ns to achieve ZS turn-on under full load condition. Switch is turned on while its body diode is conducting and ZS turn on is achieved. In Figure 17, ZS turn on of S switch in DCM operation is given. Due to both SRs are off in DCM, L M attends the resonance between L s and output capacitors of the primary MOSFETs and SRs. Thus ZS turn on can be achieved easily by the stored energy in L M. In DCM operation dead time of lagging leg is extended to 1.8μs by (9). Thus, the output capacitor of MOSFET is discharged completely and S is turned on while its body diode is conducting. The discontinuous current flowing through antiparallel diode of SRs when SRs are off and primary current under 5% load condition are shown in Figure 17. Simulation results are good match with the theoretical analysis. Figure 15 ZS turn-on of S switch under full load condition. ISBN:

9 Figure 16 ZS turn-on of S switch at 5% load condition. Figure 17 The current waveforms flowing through the primary winding and the antiparallel diode of SRs. The efficiency comparison of self-driven synchronous rectified PSFB converter operating in CCM+DCM and diode rectified conventional PSFB converter operating in CCM is given in Figure 18. In the conventional design, DSSx schottky diode with 0.77 voltage drop is used at secondary side instead of parallel connected SRs. Proposed design approach shows better performance over wide load range. Figure 18. Efficiency Comparison over wide load range ISBN:

10 5 Conclusion A self-driven synchronous rectified PSFB converter design approach to obtain high efficiency over wide load range is proposed. In the proposed approach, CCM and DCM operations are analyzed based on ZS turn on of the lagging leg switches. Dead time optimization in each operation mode is discussed based on high efficiency and load condition. In addition, to reduce conduction loss, parallel connected SRs for the center tapped rectifier on the secondary side is discussed and self-driver is used to drive SRs. Finally, analysis is verified by Saber simulation for 1kW output power, 1 output voltage and 400 DC input voltage. The calculated efficiency of the self-driven synchronous rectified PSFB converter is 5,% higher than diode rectified conventional PSFB converter at full load condition. Optimization of dead time according to load condition can help to improve efficiency in low voltage and high power applications like data center or server power systems. Self driven SR also reduces the total cost, the volume and the weight of the overall converter system. Acknowledgement This paper is supported by Tubitak under grant number of 114E010. References: [1] J. W. Kolar, U. Drofenik, J. Biela, M. Heldwein, H. Ertl, T. Friedli, S. Round, PWM Converter Power Density Barriers, IEEJ Trans. Industrial Application, ol.18, No.4, pp. 1-14, 008. [] C. Zhao, X. Wu, P. Meng, and Z. Qian, Optimum Design Consideration and Implementation of a Novel Synchronous Rectified Soft-Switched Phase-Shift Full- Bridge Converter for Low-Output-oltage High-Output-Current Applications, IEEE Trans. On Power Electronics, ol.4, No., pp , February 009. [3] U. Badstuebner, J. Biela, D. Christen, J. W. Kolar, Optimization of a 5-kW Telecom Phase-Shift DC DC Converter With Magnetically Integrated Current Doubler, IEEE Trans. On Power Electronics, ol. 58, No.10, pp , October 011. [4] U. Badstuebner, J. Biela, and J.W. Kolar, An Optimized, 99 % Efficient, 5kW, Phase-Shift PWM DC-DC Converter for Data Centers and Telecom Applications, Applied Power Electronics Conference and Exposition (APEC), 010 Twenty-Fifth Annual IEEE, pp , 1-5 February 010, Palm Springs, California. [5] [5] J.W. Kim, D.Y. Kim, C.E. Kim, and G.W. Moon, A Simple Switching Control Technique for Improving Light Load Efficiency in a Phase-Shifted Full-Bridge Converter with a Server Power System, IEEE Trans. On Power Electronics, ol. 9, No.4, pp , April 014. [6] [6] D.Y. Kim, C.E. Kim, G.W. Moon, ariable Delay Time Method in the Phase- Shifted Full-Bridge Converter for Reduced Power Consumption Under Light Load Conditions, IEEE Trans. On Power Electronics, ol. 8, No.11, pp , November 013. [7] [7] Y. Jang, M. M. Jovanovic, Light-Load Efficiency Optimization Method, IEEE Trans. On Power Electronics, ol. 5, No.1, pp.67-74, January 010. [8] [8] B.Y. Chen and Y.S. Lai, Switching control technique of phase-shiftcontrolled full-bridge converter to improve efficiency under lightload and standby conditions without additional auxiliary components, IEEE Trans. On Power Electron., vol. 5, no. 4, pp , 010. [9] M. Pahlevaninezhad, S. Eren, P. Jain, and A. Bakhshai, Self-sustained oscillating control technique for current-driven full-bridge DC/DC converter, IEEE Trans. Power Electron., vol. 8, no. 11, Nov [10] B.Gu, C.-Y. Lin, J.Dominic, and J.-S. Lai, Zero-voltage-switching PWM resonant fullbridge converter with minimized circulating losses and minimal voltage stresses of bridge rectifiers for electric vehicle battery chargers, IEEE Trans. Power Electron., vol. 8, no. 10, pp , Oct [11] A. F. Bakan, N. Altintas, and I. Aksoy, An Improved PSFB PWM DC DC Converter for High-Power and Frequency Applications, IEEE Trans. On Power Electronics, ol. 8, No.1, pp.64-74, January 013. [1] Y.. Singh, K. iswanathan, R. Naik, J.A. Sabate, R. Lai, Analysis and Control of Phaseshifted Series Resonant Converter Operating in Discontinuous Mode, Applied Power Electronics Conference and Exposition (APEC), 17-1 March 013, Long Beach, CA. [13] B. Gu, C.Y. Lin, B. Chen, J. Dominic, and J.S. Lai, Zero-oltage-Switching PWM Resonant Full-Bridge Converter With Minimized Circulating Losses and Minimal oltage Stresses of Bridge Rectifiers for Electric ISBN:

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