nrf24lu1+ Product Specification v1.0 Single Chip 2.4GHz Transceiver with USB Microcontroller and Flash Memory Applications Key Features

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1 nrf24lu1+ Single Chip 2.4GHz Transceiver with USB Microcontroller and Flash Memory Product Specification v1.0 Key Features Applications nrf24l01+ compatible RF transceiver Worldwide 2.4GHz ISM band operation Up to 2Mbps on air data rate Enhanced ShockBurst hardware link layer Air compatible with nrf24lu1, nrf24le1, nrf24l01+, nrf24l01, nrf2401a, nrf2402, nrf24e1 and nrf24e2 Low cost external ±60ppm 16MHz crystal Full speed USB 2.0 compliant device controller Up to 12 Mbps USB transfer rate 2 control, 10 bulk/interrupt and 2 ISO endpoints Dedicated 512 bytes endpoint buffer RAM Software controlled pull-up resistor for D+ PLL for full-speed USB operation Voltage regulator, 4.0 to 5.25V supply range Enhanced 8-bit 8051 compatible microcontroller Drop-in compatibility with nrf24lu1 Reduced instruction cycle time 32-bit multiplication-division unit 16 or 32 kbytes of on-chip flash memory 2 kbytes of on-chip SRAM 6 general purpose digital input/output pins Hardware SPI slave and master, UART 3 16-bit timers/counters AES encryption/decryption co-processor Supports firmware upgrade over USB Supports FS2 hardware debugger Compact 32-pin 5x5mm QFN package Compact USB dongles for wireless peripherals USB dongles for mouse, keyboards and remotes USB dongle 3-in-1 desktop bundles USB dongle for advanced media center remote controls USB dongle for game controllers Toys All rights reserved. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. January 2009

2 Liability disclaimer Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out of the application or use of any product or circuits described herein. All application information is advisory and does not form part of the specification. Limiting values Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the specifications are not implied. Exposure to limiting values for extended periods may affect device reliability. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale. Data sheet status Objective product specification Preliminary product specification Product specification This product specification contains target specifications for product development. This product specification contains preliminary data; supplementary data may be published from Nordic Semiconductor ASA later. This product specification contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Contact details For your nearest dealer, please see Main office: Otto Nielsens vei Trondheim Phone: Fax: Revision 1.0 Page 2 of 189

3 Revision History Date Version Description January Attention! Observe precaution for handling Electrostatic Sensitive Device. HBM (Human Body Model): Class 1C CDM (Charged Device Model): Class IV Revision 1.0 Page 3 of 189

4 Contents 1 Introduction Prerequisites Writing conventions Features Block diagram Typical system usage Pin Information Pin Assignments Pin Functions Antenna pins USB pins Power supply pins PROG pin Reference current pin Port pins External RESET Pin Crystal oscillator pins Absolute Maximum Ratings Operating Conditions Electrical Specifications Power consumption and timing characteristics RF transceiver characteristics USB interface Flash memory Crystal specifications DC Electrical Characteristics RF Transceiver Features Block diagram Functional description Operational Modes State diagram Power down mode Standby modes RX mode TX mode Operational modes configuration Timing information Air data rate RF channel frequency Received Power Detector measurements PA control RX/TX control Enhanced ShockBurst Revision 1.0 Page 4 of 189

5 6.4.1 Features Enhanced ShockBurst overview Enhanced Shockburst packet format Preamble Address Packet Control Field Payload CRC (Cyclic Redundancy Check) Automatic packet assembly Automatic packet disassembly Automatic packet transaction handling Auto Acknowledgement Auto Retransmission (ART) Enhanced ShockBurst flowcharts PTX operation PRX operation MultiCeiver Enhanced ShockBurst timing Enhanced ShockBurst transaction diagram Single transaction with ACK packet and interrupts Single transaction with a lost packet Single transaction with a lost ACK packet Single transaction with ACK payload packet Single transaction with ACK payload packet and lost packet Two transactions with ACK payload packet and the first ACK packet lost Two transactions where max retransmissions is reached Compatibility with ShockBurst ShockBurst packet format Data and control interface SFR registers SPI operation SPI commands Data FIFO Interrupt Register map Register map table USB Interface Features Block diagram Functional description Control endpoints Control endpoint 0 implementation Endpoint 0 registers Control transfer examples Control write transfer example Revision 1.0 Page 5 of 189

6 Control read transfer example No-data control transfer example Bulk/Interrupt endpoints Bulk/Interrupt endpoints implementation Bulk/Interrupt endpoints registers Bulk and interrupt endpoints initialization Bulk and interrupt transfers Data packet synchronization Endpoint pairing Paired IN endpoint status Paired OUT endpoint status Isochronous endpoints Isochronous endpoints implementation Isochronous endpoints registers ISO endpoints initialization ISO transfers ISO IN transfers ISO OUT transfers Memory configuration On-chip memory map Setting ISO FIFO size Setting Bulk OUT size Setting Bulk IN size The USB controller interrupts Wakeup interrupt request USB interrupt request USB interrupt vectors The USB controller registers Bulk IN data buffers (inxbuf) Bulk OUT data buffers (outxbuf) Isochronous OUT endpoint data FIFO (out8dat) Isochronous IN endpoint data FIFOs (in8dat) Isochronous data bytes counter (out8bch/out8bcl) Isochronous transfer error register (isoerr) The zero byte count for ISO OUT endpoints (zbcout) Endpoints 0 to 5 IN interrupt request register (in_irq) Endpoints 0 to 5 OUT interrupt request register (out_irq) The USB interrupt request register (usbirq) Endpoint 0 to 5 IN interrupt enables (In_ien) Endpoint 0 to 5 OUT interrupt enables (out_ien) USB interrupt enable (usbien) Endpoint 0 control and status register (ep0cs) Endpoint 0 to 5 IN byte count registers (inxbc) Endpoint 1 to 5 IN control and status registers (inxcs) Endpoint 0 to 5 OUT byte count registers (outxbc) Endpoint 1 to 5 OUT control and status registers (outxcs) Revision 1.0 Page 6 of 189

7 USB control and status register (usbcs) Data toggle control register (togctl) USB frame count low (usbframel/usbframeh) Function address register (fnaddr) USB endpoint pairing register (usbpair) Endpoints 0 to 5 IN valid bits (Inbulkval) Endpoints 0 to 5 OUT valid bits (outbulkval) Isochronous IN endpoint valid bits (inisoval) Isochronous OUT endpoint valid bits (outisoval) SETUP data buffer (setupbuf) ISO OUT endpoint start address (out8addr) ISO IN endpoint start address (in8addr) Encryption/Decryption Unit Features ECB Electronic Code Book CBC Cipher Block Chaining CFB Cipher FeedBack OFB Output FeedBack mode CTR Counter mode Functional description SPI master Block diagram Functional description SPI operation SPI slave Block diagram Functional description SPI timing Timer/Counters Features Block diagram Functional description Timer 0 and Timer Mode 0 and Mode Mode Mode Timer Timer 2 description Timer mode Event counter mode Gated timer mode Timer 2 reload SFR registers Timer/Counter control register TCON Timer mode register - TMOD Timer0 TH0, TL Revision 1.0 Page 7 of 189

8 Timer1 TH1, TL Timer 2 control register T2CON Timer 2 TH2, TL Compare/Capture enable register CCEN Capture registers CC1, CC2, CC Compare/Reload/Capture register CRCH, CRCL Serial Port (UART) Features Block diagram Functional description SFR registers Serial Port 0 control register S0CON Serial port 0 data buffer S0BUF Serial port 0 reload register S0RELH, S0RELL Serial Port 0 baud rate select register - WDCON Input/Output port (GPIO) Normal IO Expanded IO MCU Features Block diagram Arithmetic Logic Unit (ALU) Instruction set summary Opcode map Memory and I/O organization Special function registers Special function registers locations Special function registers reset values Accumulator - ACC B register B Program Status Word register - PSW Stack Pointer SP Data Pointer DPH, DPL Data Pointer 1 DPH1, DPL Data Pointer Select register DPS Random Access Memory (RAM) Cycle control Flash Memory Features Block diagram Functional description Flash memory configuration InfoPage content Protected pages and data pages kb Flash memory size option Software compatibility with nrf24lu Revision 1.0 Page 8 of 189

9 SFR registers for flash memory operations Brown-out Flash programming from the MCU MCU write and erase of the MainBlock Hardware support for firmware upgrade Flash programming through USB Flash Layout USB Protocol Firmware Version (cmd id 0x01) Flash Write Init (cmd 0x02) Read Flash (cmd 0x03) Flash Page Erase (cmd 0x04) Turn on flash MainBlock readback disable (cmd 0x05) Select flash half (cmd 0x06) Flash programming through SPI SPI commands WREN/WRDIS RDSR WRSR READ PROGRAM ERASE PAGE ERASE ALL RDFPCR RDISIP RDISMB ENDEBUG SPI Readback disable Standalone programming requirements Clock requirements Power supply requirements Signal pin requirements In circuit programming over SPI SPI programming sequences Erasing and programming the InfoPage MDU Multiply Divide Unit Features Block diagram Functional description SFR registers a) Loading the MDx registers b) Executing calculation c) Reading the result from the MDx registers d) Normalizing e) Shifting f) The mdef flag Revision 1.0 Page 9 of 189

10 g) The mdov flag Watchdog and wakeup functions Features Block diagram Functional description The Low Frequency Clock (CKLF) Tick calibration RTC wakeup timer Programmable GPIO wakeup function Watchdog Programming interface to watchdog and wakeup functions Power management Features Block diagram Modes of operation Functional description Clock control CLKCTL Power down control PWRDWN Reset result RSTRES Wakeup configuration register WUCONF Power control register - PCON Power supply supervisor Features Functional description Power-on reset Brown-out detection Interrupts Features Block diagram Functional description SFR registers Interrupt enable 0 register IEN Interrupt enable 1 register IEN Interrupt priority registers IP0, IP Interrupt request control registers IRCON HW debugger support Features Functional description Peripheral information Antenna output Crystal oscillator PCB layout and decoupling guidelines Application example Schematics Layout Bill Of Materials (BOM) Revision 1.0 Page 10 of 189

11 26 Mechanical specifications Ordering information Package marking Abbreviations Product options RF silicon Development tools Glossary of terms Appendix A - (USB memory configurations) Configuration Configuration Configuration Configuration Appendix B - Configuration for compatibility with nrf24xx Revision 1.0 Page 11 of 189

12 1 Introduction The nrf24lu1+ is a unique single chip solution for compact USB dongles. The internal nrf24l GHz RF transceiver supports a wide range of applications including PC peripherals, sports accessories and game peripherals. With an air data rate of 2 Mbps combined with full speed USB, supporting up to 12 Mbps, the nrf24lu1+ meets the stringent performance requirements of applications such as wireless mouse, game controllers and media center remote controls with displays. The nrf24lu1+ integrates: A nrf24l GHz RF transceiver A full speed USB 2.0 compliant device controller An 8-bit microcontroller 16 or 32 kbytes of flash memory All this is packaged on a compact 5x5mm package, low cost external BOM. With an internal voltage regulator that enables the chip to be powered directly from the USB bus, it does not require an external voltage regulator, saving cost and board space. With a fully integrated RF synthesizer and PLL for the USB no external loop filters, resonators or VCO varactor diodes are required. All that is needed is a low cost ±60ppm 16MHz crystal, matching circuitry and the antenna. The main benefits of nrf24lu1+ are: Very compact USB dongle Low cost external BOM No need for an external voltage regulator Single low cost ±60ppm 16MHz crystal Flash memory for firmware upgrades 1.1 Prerequisites In order to fully understand the product specification, a good knowledge of electronic and software engineering is necessary. 1.2 Writing conventions This product specification follows a set of typographic rules that makes the document consistent and easy to read. The following writing conventions are used: Commands, bit state conditions, and register names are written in Courier. Pin names and pin signal conditions are written in Courier bold. Cross references are underlined and highlighted in blue. Revision 1.0 Page 12 of 189

13 1.3 Features Features of the nrf24lu1+ include: Fast 8-bit MCU: Intel MCS 51 compliant instruction set Reduced instruction cycle time, up to 12x compared to legacy bit multiplication division unit Memory: 16 or 32 kbytes of on-chip flash memory with security features 2 kbytes of on-chip RAM memory Pre-programmed USB bootloader in the on-chip flash memory. 6 programmable digital input/output pins configurable as: GPIO SPI master SPI slave External interrupts Timer inputs Full duplex serial port Debug interface High performance 2.4 GHz RF-transceiver True single chip GFSK transceiver Complete OSI Link Layer in hardware Enhanced ShockBurst link layer support in HW: Packet assembly/disassembly Address and CRC computation Auto ACK and retransmit On the air data rate 250 kbps, 1 Mbps or 2 Mbps Digital interface (SPI) speed 0-8 Mbps 125 RF channel operation, 79 ( GHz) channels within GHz. Short switching time enable frequency hopping Fully RF compatible with nrf24lxx RF compatible with nrf2401a, nrf2402, nrf24e1, nrf24e2 in 250 kbps and 1 Mbps mode AES encryption/decryption HW-block with 128 bits key length ECB Electronic Code Book mode CBC Cipher Block Chaining CFB Cipher FeedBack mode OFB Output FeedBack mode CTR Counter mode Full speed USB 2.0 compliant device controller supporting: Data transfer rates up to 12 Mbit/s Control, Interrupt, Bulk and ISO data transfer Endpoint 0 for control 5 input and 5 output Bulk/Interrupt endpoints 1 input and 1 output iso-synchronous endpoints Total 512 bytes of USB buffer endpoint memory sharable between endpoints On-chip USB transceiver PHY On-chip pull-up resistor on D+ line with software controlled disconnect Power management function: Low power design supporting fully static stop/ standby/ suspend modes Programmable MCU clock frequency from 64 khz to 16 MHz On-chip voltage regulators supporting low power mode (supplied from USB power) Watchdog and wakeup functionality running in low power mode Revision 1.0 Page 13 of 189

14 On-chip oscillator and PLL to obtain full speed USB operation and to reduce the need for external components On-chip power on reset generator and brown-out detector On-chip support for FS2 and nrfprobe TM HW debugger, supported by Keil development tools. Complete firmware platform available: Hardware abstraction layer (HAL) Functions USB library Functions Standard and HID specific USB Requests and Descriptors nrf24lu1+ Library functions AES HAL Application examples Device Firmware Upgrade 1.4 Block diagram USB MEM-bus IRAM 256 byte Interrupt Control Voltage regulator Power on reset FLASH 16/32 kbytes OCI MCU 8051 SRAM 2 kbytes RTC SPI Master/Slave Port Interface SFR-bus XOSC 16MHz PLL 48MHz Watch dog Slow clock bridge Wakeup AES coprocessor 2.4GHz RF Transceiver Enhanced ShockBurst SPI Master Power Management Brown-out Detector Figure 1. nrf24lu1+ block diagram To find more information on the block diagram, see Table 1. below: Name Reference USB chapter 7 on page 65 FLASH chapter 17 on page 137 SRAM chapter 15 on page GHz RF transceiver chapter 6 on page 28 XOSC section 24.2 on page 178 Enhanced ShockBurst TM section 6.4 on page 34 IRAM chapter 16 on page 136 MCU chapter 14 on page 121 RTC, Watchdog and Wakeup chapter 19 on page 162 SPI Master chapter 9 on page 101 Interrupt control chapter 21 on page 172 Revision 1.0 Page 14 of 189

15 Name Reference SPI master/slave chapter 9 on page 101 and chapter 10 on page 103 AES co-processor chapter 8 on page 96 Power management chapter 20 on page 167 Brown-out detector section 17.4 on page Typical system usage Table 1. Block diagram cross references USB Connector ESD nrf24lu1+ Antenna Matching Xtal Figure 2. Typical system usage Revision 1.0 Page 15 of 189

16 2 Pin Information 2.1 Pin Assignments VDD VDD VBUS VSS VDD ANT2 D+ ANT1 D- VDD_PA VSS VDD PROG VSS RESET VSS VDD P0.0 P0.1 VSS P0.2 P0.3 P0.4 P0.5 XC1 XC2 VSS DEC2 DEC1 VDD VSS IREF nrf24lu QFN32 5X Exposed die pad Figure 3. nrf24lu1+ pin assignment (top view) for a QFN32 5x5 mm package. Revision 1.0 Page 16 of 189

17 2.2 Pin Functions Pin Name Type Description 21, 22 ANT1, ANT2 RF Antenna connection 5, 4 D-, D+ Digital I/O USB data 28, 29 DEC1, DEC2 Power Positive Digital Supply output for de-coupling purposes 25 IREF Analog Input Reference current 10, 11, 13, 14, 15, Antenna pins Table 2. nrf24lu1+ pin functions ANT1 and ANT2 are connections for the external antenna (both receive and transmit) USB pins D- and D+ are the connections to the USB data lines. External ESD protection is recommended Power supply pins VBUS and VSS are the power supply and ground pins. The nrf24lu1+ can operate from a single power supply. The nrf24lu1+ contains an on-chip regulator that produces +3.3V on the VDD pins, from the VBUS supply line ( V). Alternatively, the VBUS pin can be left open and the VDD pins may be fed from an external 3.3V supply. In this case, the on-chip 3.3V regulator is switched off. Additional on-chip regulators produce voltages for internal analog and digital functions blocks. External decoupling capacitors are required on DEC1 and DEC2. VDD_PA is a 1.8V output that is used to switch on an external RF Power Amplifier PROG pin P0.0 P0.5 Digital I/O General purpose data Port 0, bit 0-5. See Table 99. on page 120 for alternative pin functions. 7 PROG Digital Input Reserved for programming the flash 8 RESET Digital Input Reset for MCU, active low 2 VBUS Power USB power connection 1, 3, 9, 19, 24, 27 VDD Power Alternative power supply pins. The VDD pins must always be connected and de-coupled externally. 20 VDD_PA Power Output Power Supply (+1.8V) to Power Amplifier 6, 12, 17, 18, VSS Power Ground (0V) 23, 26, 30 32, 31 XC1, XC2 Analog Input Crystal connection Exposed die pad Power/heat relief Not connected When set high this pin enables external flash programming and Port 0 is configured as a slave SPI port. The PROG pin needs an external pull-down resistor. Revision 1.0 Page 17 of 189

18 2.2.5 Reference current pin IREF pin must be connected to an external resistor Port pins P0.0 P0.5 are six general purpose I/O pins. Their functions are described in chapter 13 on page External RESET Pin A logic 0 on the RESET pin forces the nrf24lu1+ to a known start-up state Crystal oscillator pins XC1 and XC2 are connections to an external crystal. Revision 1.0 Page 18 of 189

19 3 Absolute Maximum Ratings Maximum ratings are the extreme limits that you can expose the nrf24lu1+ to without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating conditions Minimum Maximum Units Supply voltages VBUS V VSS 0 V VDD V Input voltage VI V Total Power Dissipation PD (TA=85 C) 180 mw Temperatures Operating Temperature C Storage Temperature C Table 3. Absolute maximum ratings Revision 1.0 Page 19 of 189

20 4 Operating Conditions Symbol Parameter (condition) Notes Min. Typ. Max. Units VBUS Supply voltage V VDD Alternative supply voltage V TEMP Operating Temperature ºC Table 4. Operating conditions Revision 1.0 Page 20 of 189

21 5 Electrical Specifications This section contains electrical and timing specifications. 5.1 Power consumption and timing characteristics Symbol Parameter (condition) Notes Min. Typ. Max. Units I OP Average supply current in operating mode a 24 ma I STANDBY Supply current in standby mode b 480 µa MCU I MCU16MPLL 16MHz, generated from PLL 6.3 ma I MCU12MPLL 12MHz, generated from PLL 5 ma I MCU8MPLL 8MHz, generated from PLL 4 ma I MCU4MPLL 4MHz, generated from PLL 3 ma I MCU1.6MPLL 1.6MHz, generated from 2 ma PLL I MCU4MXO 4MHz, generated from XO 2.4 ma I MCU1.6MXO 1.6MHz, generated from XO 1.75 ma I MCU.32MXO 0.32MHz, generated from 1.1 ma XO I MCU64KXO 0.064MHz, generated from 1 ma XO Trst_act From RESET to MCU active 2 ms Tint_act From INTERRUPT to MCU active 300 µs Tact_stby MCU from active to standby c 32 µs RF Transceiver I TX RF Transceiver TX output 11.1 ma power RF Transceiver RX 2Mbps 13.3 ma I RX RF Transceiver RX 1Mbps 12.9 ma Tstby2a RF Transceiver from standby to active c 130 µs Trst_radio From RESET to RF Transceiver power 50 ms down USB I USB USB active current 4.4 ma Tusb_wh USB wakeup from host 500 µs Tusb_wmcu USB wakeup from MCU 300 µs Tusbact_susp USB from active to suspend c 32 µs PLL Tplloff_on PLL from off to on time c d 250 µs Tpllon_off PLL from on to off time c d 32 µs a. MCU running radio receive at 2Mbps and USB transmit b. When MCU is in standby, USB is suspended and the RF Transceiver is in standby c. Measured from start of the software instruction which executes the change of mode, see also Table 15. d. Only possible when USB is in suspend mode Table 5. Power consumption and timing characteristics Revision 1.0 Page 21 of 189

22 5.2 RF transceiver characteristics Symbol Parameter (condition) Notes Min. Typ. Max. Units General RF conditions f OP Operating frequency a MHz PLL res PLL Programming resolution 1 MHz f XTAL Crystal frequency 16 MHz Δf 250 Frequency 250kbps ±160 khz Δf 1M Frequency 1Mbps ±160 khz Δf 2M Frequency 2Mbps ±320 khz R GFSK Air data rate b kbps F CHANNEL 1M Non-overlapping channel c 1 MHz 250kbps/1 Mbps) F CHANNEL 2M Non-overlapping channel 2 2 MHz Mbps Transmitter operation P RF Maximum output power d 0 +4 dbm P RFC RF power control range db P RFCR RF power accuracy ±4 db P BW2 20dB bandwidth for modulated carrier khz (2 Mbps) P BW1 20dB bandwidth for modulated carrier khz (1 Mbps) P BW250 20dB bandwidth for modulated carrier khz (250 kbps) P RF1.2 1 st Adjacent Channel Transmit Power -20 dbc 2MHz (2Mbps) P RF2.2 2 nd Adjacent Channel Transmit Power -45 dbc 4MHz (2Mbps) P RF1.1 1 st Adjacent Channel Transmit Power -20 dbc 1MHz (1Mbps) P RF2.1 2 nd Adjacent Channel Transmit Power -40 dbc 2MHz (1Mbps) P RF st Adjacent Channel Transmit Power -25 dbc 1MHz (250kbps) P RF nd Adjacent Channel Transmit Power -40 dbc 2MHz (250kbps) Receiver operation RX MAX Maximum received signal at < 0.1% 0 dbm BER RX SENS Sensitivity (0.1% 2 Mbps -82 dbm RX SENS Sensitivity (0.1% 1 Mbps -85 dbm RX SENS Sensitivity (0.1% 250 kbps e -94 dbm RX selectivity according to ETSI EN V1.3.1 ( ) page 27 C/I CO C/I co-channel (2 Mbps) 7 dbc C/I 1ST 1 st ACS (Adjacent Channel Selectivity), 3 dbc C/I 2MHz (2 Mbps) C/I 2ND 2 nd ACS, C/I 4MHz (2 Mbps) -17 dbc Revision 1.0 Page 22 of 189

23 Symbol Parameter (condition) Notes Min. Typ. Max. Units C/I 3RD 3 rd ACS, C/I 6MHz (2 Mbps) -21 dbc C/I Nth N th ACS, C/I f i > 12MHz (2 Mbps) f -40 dbc C/I Nth N th ACS, C/I f i > 36MHz (2 Mbps) -48 dbc C/I CO C/I co-channel (1 Mbps) 9 dbc C/I 1ST 1 st ACS, C/I 1MHz (1 Mbps) 8 dbc C/I 2ND 2 nd ACS, C/I 2MHz (1 Mbps) -20 dbc C/I 3RD 3 rd ACS, C/I 3MHz (1 Mbps) -30 dbc C/I Nth N th ACS, C/I f i > 6MHz (1 Mbps) -40 dbc C/I Nth N th ACS, C/I f i > 25MHz (1 Mbps) f -47 dbc C/I CO C/I co-channel (250 kbps) 12 dbc C/I 1ST 1 st ACS, C/I 1MHz (250 kbps) -12 dbc C/I 2ND 2 nd ACS, C/I 2MHz (250 kbps) -33 dbc C/I 3RD 3 rd ACS, C/I 3MHz (250 kbps) -38 dbc C/I Nth N th ACS, C/I f i > 6MHz (250 kbps) -50 dbc C/I Nth N th ACS, C/I f i > 25MHz (250 kbps) f -60 dbc RX selectivity with nrf24l01 equal modulation on interfering signal (Pin = -67dBm for wanted signal) C/I CO C/I co-channel (2 Mbps) (modulated 11 dbc carrier) C/I 1ST 1 st ACS (Adjacent Channel Selectivity), 4 dbc C/I 2MHz (2 Mbps) C/I 2ND 2 nd ACS, C/I 4MHz (2 Mbps) -18 dbc C/I 3RD 3 rd ACS, C/I 6MHz (2 Mbps) -24 dbc C/I Nth N th ACS, C/I f i > 12MHz (2 Mbps) -40 dbc C/I Nth N th ACS, C/I f i > 36MHz (2 Mbps) -48 dbc C/I CO C/I co-channel (1 Mbps) 12 dbc C/I 1ST 1 st ACS, C/I 1MHz (1 Mbps) 8 dbc C/I 2ND 2 nd ACS, C/I 2MHz (1 Mbps) -21 dbc C/I 3RD 3 rd ACS, C/I 3MHz (1 Mbps) -30 dbc C/I Nth N th ACS, C/I f i > 6MHz (1 Mbps) -40 dbc C/I Nth N th ACS, C/I f i > 25MHz (1 Mbps) -50 dbc C/I CO C/I co-channel (250 kbps) 7 dbc C/I 1ST 1 st ACS, C/I 1MHz (250 kbps) -12 dbc C/I 2ND 2 nd ACS, C/I 2MHz (250 kbps) -34 dbc C/I 3RD 3 rd ACS, C/I 3MHz (250 kbps) -39 dbc C/I Nth N th ACS, C/I f i > 6MHz (250 kbps) -50 dbc C/I Nth N th ACS, C/I f i > 25MHz (250 kbps) -60 dbc RX intermodulation performance according to Bluetooth specification version 2.0, 4 th November 2004, page 42 P_IM(6) Input power of IM interferers at 6 and g -42 2Mbps 12MHz distance from wanted signal 2Mbps Input power of IM interferers at 8 and 16MHz distance from wanted signal g -38 dbm Revision 1.0 Page 23 of 189

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