LP NF590 SLI-M2R/G BIOS Setting Guideline

Transcription

1 LP NF590 SLI-M2R/G BIOS Setting Guideline (BIOS version: BIOS 12/ ) V001 Pressing DEL at DFI NF590 SLI-M2R/G LOG screen to login BIOS setup screen BIOS setup screen L Genie BIOS settings: This setup thread is combined all needed settings for over clocking (CPU speed setting, CPU features, DRAM timings, Voltage settings and PCI speed etc.)

2 Genie BIOS : Main setup screen PCI Device Control : RAID Config: Via this page, user can define NVRAID mode or native IDE mode for SATA 1~6 ports. HD Audio: onboard audio controller, default AUTO (enabled) MAC Lan: Rear LAN1port controller, default AUTO (enabled) MAC Lan: Rear LAN1port controller, default AUTO (enabled) Sil3132 SATA RAID Control: SATA7/8 RAID mode controller

3 Voltage Control : CPU VID Control range: 1.000V~1.600V, Default AUTO by detecting CPU. CPU VID Special Add: %~121.25% plus on CPU voltage. C51 NB Core Voltage range: 1.20V~1.50V, North bridge working voltage. MCP55 SB Core voltage range: 1.50V~1.80V, South bridge working voltage. MCP55 SB Standby voltage: 1.5V~1.8V, South bridge S3/S1 voltage level. CPU/C51 HT Drive Strength: Low/Low, Low/High, High/Low and High/High CPU/C51 HT Voltage: 1.30V~1.50V, CPU to NB bus voltage C51/MCP55 HT Voltage: 1.30V~1.50V, CPU to SB bus voltage DRAM Voltage range: 1.70V~3.00V DRAM Configuration :

4 Memory Drive Strength : This page is defining the DRAM signal strength for each Clock and Data bus, in order to work on higher working speed for tight DRAM timing. DRAM Drive Strength: Level 1~31, level 31 is maximum; default is 23 by BIOS optimized. DRAM Drive Weak/Normal mode: Weak and Normal; Memories data bus drive mode. CLK Enable Drive Strength:1.0 ~2.0x ; Clock available signal strength Chip Select Drive Strength: 1.0 ~2.0x ; Memory modules BANK selection signals strength MEM Address Drive Strength: 1.0 ~2.0x ; DRAM address signal strength MEM Clock Drive Strength: 0.75 ~1.50x ; DRAM working clock signal strength Memory Data Drive Strength: 0.75 ~1.50x ; Memory data bus signal strength Data Strobe Drive Strength: 0.75 ~1.50x ; Memory data ready signal strength CS/ODT Pin fine Delay: DRAM terminal impedance/voltage optimized

5 Memory Timings : SLI-Ready Memory: CPUOC 0~13 and MAX 15% to support SLI-Ready memory modules Timing mode: Manual to control Memory Clock Value/Limit item or AUTO by SPD detecting Memory Clock Value/Limit item: 200~533MHz(DDR400~DDR1066); DRAM working ratio Command Per Clock: command rate mode 1T and 2T (Tcl): 2~6 clock; CAS (Column signal) latency time (Tras): 4~18 Minimum timing of a command working cycle. (TRCD+CL+ 2 clock) (Trcd): 3~6 clock; RAS (Row signal) to CAS (Column signal) delay for read/write command (Trp) : 3~6 clock; Precharge timing for memory data by each command cycle

6 (Trrd): 2~5 clock; Command rate of memory's banks (Trc): 11~26 clock; Minimum timing of a command to next command. (trc) = (tras)+ (trp) (Trfc0): 75~327ns; Minimum timing to reflash a ROW at same storage block(trfc > trc)-dimm1 slot (Trfc1): DIMM 2 slot (Trfc2): DIMM 3 slot (Trfc3): DIMM 4 slot (Trtp): 2~5 clock; Precharge period for read action (Twr): 3~6 clock; Write recovery timing (Trtw): 2~9 clock; delay read to write command for memory chips (Twtr): 1~3 clock; delay write to read command for memory chips (Tref): 15.6/7.8/3.9 us; DRAM chip reflash cycle Max Async Latency: 1~15 ns; maximum asynchronous delay, default AUTO by SPD. Bank Interleave: Enable and Disable; Enable to let Data interleave to save on DRAM bank DRAM On-Die Termination: 50/70/150 ohm ODT impedance Read Delay From Rx FIFO: 0.5~4 clock; Data read buffer delay Read/Write Queue by Pass: 2/4/8/16 time; Data queue line bandwidth ByPass Maximum: 0~15 time; Dependence Chain Queue(DCQ) definition 32byte Granularity: 64byte is 8 burst mode, 32byte is 4burst mode. Idle Cycle Limit: 4~256 clocks; precharge time definition for read data page Dynamic Conuter: Enable/Disable; to define Idle Cycle Limit status Read DQS Skew: -1/096~-10/096; to adjust DQS strength for data output Genie BIOS items : CPU Clock Multiplier: X4~X25 (base on CPU to NB bus working FSB), Default AUTO by detecting CPU K8 Cool n Quiet Support: AMD advance power controller, default AUTO (enabled) CPU/C51 HTT Frequency range: 100~500MHz, CPU to NB bus working FSB CPU/C51 HTT Multiplier range: 1X~5X, CPU to NB bus hyper transfer speed

7 CPU/C51 HTT Width range: 16bit/8bit mode, CPU to NB bus hyper transfer bandwidth CPU/MCP55 HTT Frequency range: 200~500MHz, CPU to SB bus working FSB CPU/MCP55 HTT Multiplier range: 1X~5X, CPU to SB bus hyper transfer speed CPU/MCP55 HTT Width range: 16bit/8bit mode, CPU to SB bus hyper transfer bandwidth PCI-E Slot4 Clock: 100~200MHz. PCI-E Slot1 Clock: 100~200MHz. BIOS Reloaded function: DFI Lan Party series are providing 1last fine status + 4 user s profile space for doing BIOS setting saving and recovery. Auto Save bootable setting: Enable / Disable For saving last fine/ bootable parameters by BIOS itself every time Load last bootable: For loading last BIOS parameters. Save setting to bank with: Current settings or last saved CMOS settings. To define the resource of parameters for bank saving. User define setting bank #1 ~ #4: 1. Bank Description: There are 4 rows for writing a short description. Double click on row when this row is empty, it will erase pervious data.

8 2. Save to this bank: Press Y to save data to this bank 3. Load from this bank: Press Y to load data of this bank to be current BIOS setup settings. 4. Hotkey =>: define the hotkey for a quick change BIOS settings to boot. Please press Hotkey after power on system immediately. EZ Clear CMOS methods:

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