RESUME INTRODUCTION QUALIFICATION. Alpana Agarwal. Designation:- Assistant Professor. Specialization:- VLSI Design, Design Automation, ASIC Design

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1 RESUME INTRODUCTION Alpana Agarwal M.Sc., M.Tech. Designation:- Assistant Professor Specialization:- VLSI Design, Design Automation, ASIC Design Contact Information:- Department of Electronics and Communication Engineering, Thapar University, Patiala , Punjab, India - Contact No. : (Mb.) Permanent Address:- 25 Doctor s Colony, Bhadson Road PATIALA , Punjab, India QUALIFICATION 2002 Ph.D. (To Be Submitted Shortly) Under the supervision of Dr. Chandra Shekhar, Director, CEERI Pilani Thapar University, Patiala , Punjab, India.

2 M.Tech. Solid State Materials with GATE Fellowship Indian Institute of Technology Delhi, Hauz Khas, NEW DELHI , India M.Sc. Physics Indian Institute of Technology Delhi, Hauz Khas, NEW DELHI , India B.Sc., M D University with 8 th Position in University Merit List All India Senior Secondary Certificate Examination (12 th ), CBSE with 3 th Position in school Birla Balika Vidya Peeth, Pilani , (Raj.) India All India Secondary School Examination (10 th ), CBSE Birla Balika Vidya Peeth, Pilani , (Raj.) India Dissertation Topics:- Ph.D. Synthesis of Analog IC Building Blocks WORK EXPERIENCE August 1, 1996 to till date Assistant Professor, EEED/ECED, Thapar University, Patiala, Punjab, India. March 25, 1992 to July 30, 1996 Scientist C, Central Electronics Engineering Research Institute, Pilani , (Raj.) India March 25, 1988 to March 24, 1992 Scientist B, Central Electronics Engineering Research Institute, Pilani , (Raj.) India RESEARCH AREAS ASIC Design

3 Design Automation Low Power Low Noise VLSI Circuit Design PUBLICATIONS & TEXT BOOKS International Journals:- Alpana Agarwal and Chandra Shekhar, Figure of Merit Based Area-Constrained Design of Differential Amplifiers VLSI Design, vol. 2008, Article ID , 5 pages, doi: /2008/ International Conferences:- A CAD Tool for PLA Based Finite State Machine Generation, Proceedings of the IInd International Workshop on VLSI Design, pp , (Coauthor) Design of a Serial Data Link Controller Chip for Computer Communication, Proceedings of IETE 32nd Technical Convention, pp , (Coauthor) Prediction of Subthreshold Current Problems in VLSI, Proceedings of the Vth International Workshop on Physics of Semiconductor Devices, pp. 3 6, (Coauthor) A Novel Electrical Test Structure for Measuring Misalignment between Polysilicon and Active Area in MOS VLSI Technologies, Proceeding of the IVth International Conference on VLSI Design, pp , (Coauthor) An ASIC for high performance Stepper Motor Control, Proceedings of the Vth International Conference on VLSI Design, pp., (Coauthor) Evolution of Architectural Concepts and Design Methods of Microprocessors, Proceedings of the XIth International Conference on VLSI Design, pp , (Coauthor) Carry Circuitry for LUT-Based FPGA, Proceedings of the 17th International Conference on VLSI Design 2004 and ICES 3, Jan. 7 9, 2004, Mumbai. (Coauthor) A Voltage controlled CMOS VGA with 40 db Dynamic range for MEMS Applications, Symposium H: MEMS Technology and Devices in International Conference on Materials for Advanced Technologies 2007, July 1 6, 2007, Singapore. (Author) National Conferences:- About 30 papers.

4 Course Material Developed:- Prepared course material for the UG program entitled VLSI Design Concepts under the funding from AICTE-CEP program, March Prepared Self Instruction Materials on Digital Electronic Circuits and Electronic Devices & Circuits for Department of Distance Education, Thapar University, WORKSHOPS & COURSES ATTENDED Participated in more than 40 Workshops/Courses/Seminars. EXPERT TALKS & GUEST LECTURES Delivered Invited Talks/Expert Lectures at IIT Delhi, BITS Pilani, Kurukshetra University, PEC Chandigarh, NIT Kurukshetra, SLIET Longowal, Technology Education & Research Institute, Kurukshetra etc. MOS Models for Analog IC Design, IMS Pre-Conference Tutorial, Feb 16, 2006, Kurukshetra. RESEARCH PROJECTS & PATENTS As Project Coordinator completed project entitled Special Manpower Development Program for VLSI Design and Related CAD (Phase I) sponsored by Ministry of Communication and Information Technology, Government of India, Project Cost ~ 75 lakhs. As Principal Investigator completed project entitled Establishing a Center of Excellence in VLSI Design & CAD, sponsored by TU, As Project Coordinator having a the project entitled Special Manpower Development Program for VLSI Design and Related CAD (Phase II) sponsored by Ministry of Communication and Information Technology, Government of India, Project Cost ~ 1.09 Crores. (Ongoing) ACHIEVEMENTS & AWARDS Received INSA Visiting Scientist Fellowship for the year for six months to carry out research at Central Electronics Engineering Research Institute, Pilani , (Raj.), India. ADMINISTRATIVE & OTHER ACTIVITIES Departmental Student Counselor, EEED, , Thapar University, Patiala, Punjab, India

5 Faculty-Incharge, Student Counseling and Development Cell, 2002 till date, Thapar University, Patiala, Punjab, India UG Academic Coordinator, ECED, Thapar University, Patiala, Punjab, India, PG Academic Coordinator, ECED, Thapar University, Patiala, Punjab, India, since Lab Incharge, VLSI Design & CAD, ECED, Thapar University, Patiala, Punjab, India Member, Board of Governors, 2008 & 2009, Thapar University, Patiala, Punjab, India Member, Staff Affairs Committee, 2008 & 2009, Thapar University, Patiala, Punjab, India Member Senate, Thapar University, Patiala, Punjab, India, for 1997, 2000, 2004, 2007, 2008, M.E./M.Tech. THESES GUIDED Guided about 40 M.E./M.Tech. thesis.

THAPAR UNIVERSITY. (Declared under section 3 of UGC Act, 1956 vide notification # F.9-12/84-U.3 of GOI) PATIALA-147004, PUNJAB http:// www.thapar.

THAPAR UNIVERSITY. (Declared under section 3 of UGC Act, 1956 vide notification # F.9-12/84-U.3 of GOI) PATIALA-147004, PUNJAB http:// www.thapar. THAPAR UNIVERSITY (Declared under section 3 of UGC Act, 1956 vide notification # F.9-12/84-U.3 of GOI) PATIALA-147004, PUNJAB http:// www.thapar.edu FACULTY OPENINGS: Information & Instruction Sheet ---------------------------------------------------------------------------------------------------------------------------