Mobile Low-Power DDR SDRAM

Transcription

1 Mobile Low-Power DDR SDRAM MT46H32M6LF 8 Meg x 6 x 4 banks MT46H6M32LF 4 Meg x 32 x 4 banks MT46H6M32LG 4 Meg x 32 x 4 banks 52Mb: x6, x32 Mobile LPDDR SDRAM Features Features V DD /V DDQ =.7.95V Bidirectional data strobe per byte of data DQS Internal, pipelined double data rate DDR architecture; two data accesses per clock cycle Differential clock inputs and # Commands entered on each positive edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs 4 internal banks for concurrent operation Data masks DM for masking write data; one mask per byte Programmable burst lengths BL: 2, 4, 8, or 6 Concurrent auto precharge option is supported Auto refresh and self refresh modes.8v LVCMOS-compatible inputs Temperature-compensated self refresh TCSR Partial-array self refresh PASR Deep power-down DPD Status read register SRR Selectable output drive strength DS Clock stop capability 64ms refresh, 32ms for automotive temperature Table : Key Timing Parameters CL = 3 Options Marking V DD /V DDQ.8V/.8V H Configuration 32 Meg x 6 8 Meg x 6 x 4 banks 32M6 6 Meg x 32 4 Meg x 32 x 4 banks 6M32 Addressing JEDEC-standard addressing LF Reduced page size LG Plastic "green" package 6-ball VFBGA 8mm x 9mm 2 BF 9-ball VFBGA 8mm x 3mm 3 B5 Timing cycle time CL = 3 2 MHz -5 CL = 3 85 MHz -54 CL = 3 66 MHz -6 CL = 3 33 MHz -75 Power Standard I DD2 /I DD6 None Operating temperature range Commercial to +7 C None Industrial 4 C to +85 C IT Automotive 4 C to +5 C AT Design revision :C Notes:. Contact factory for availability. 2. Only available for x6 configuration. 3. Only available for x32 configuration. Speed Grade Clock Rate Access Time -5 2 MHz 5.ns MHz 5.ns MHz 5.ns MHz 6.ns Products and specifications discussed herein are subject to change by Micron without notice.

2 Features Table 2: Configuration Addressing Architecture 32 Meg x 6 6 Meg x 32 Reduced Page Size 6 Meg x 32 Configuration 8 Meg x 6 x 4 banks 4 Meg x 32 x 4 banks 4 Meg x 32 x 4 banks Refresh count 8K 8K 8K Row addressing 8K A[2:] 8K A[2:] 6K A[3:] Column addressing K A[9:] 52 A[8:] 256 A[7:] Figure : 52Mb Mobile LPDDR Part Numbering MT 46 H 32M6 LF BF -6 IT :C Micron Technology Product Family 46 = Mobile LPDDR Operating Voltage H =.8/.8V Configuration 32 Meg x 6 6 Meg x 32 Addressing LF = JEDEC-standard LG = Reduced page size Package Codes BF = 6-ball 8mm x 9mm VFBGA, green B5 = 9-ball 8mm x 3mm VFBGA, green Design Revision :C = Third generation Operating Temperature Blank = Commercial C to +7 C IT = Industrial 4 C to +85 C AT = Automotive 4 C to +5 C Power Blank = Standard I DD2 /I DD6 Cycle Time CL = 3-5 = 5ns t -54 = 5.4ns t -6 = 6ns t -75 = 7.5ns t FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron s FBGA part marking decoder is available at 2

3 Features Contents General Description... 8 Functional Block Diagrams... 9 Ball Assignments... Ball Descriptions... 3 Package Dimensions... 5 Electrical Specifications... 7 Electrical Specifications I DD Parameters... 2 Electrical Specifications AC Operating Conditions Output Drive Characteristics... 3 Functional Description Commands DESELECT NO OPERATION LOAD MODE REGISTER ACTIVE READ WRITE PRECHARGE BURST TERMINATE... 4 AUTO REFRESH... 4 SELF REFRESH... 4 DEEP POWER-DOWN... 4 Truth Tables State Diagram Initialization Standard Mode Register... 5 Burst Length Burst Type CAS Latency Operating Mode Extended Mode Register Temperature-Compensated Self Refresh Partial-Array Self Refresh Output Drive Strength Status Read Register Bank/Row Activation READ Operation... 6 WRITE Operation... 7 PRECHARGE Operation Auto Precharge Concurrent Auto Precharge AUTO REFRESH Operation SELF REFRESH Operation... 9 Power-Down... 9 Deep Power-Down Clock Change Frequency Revision History Rev. I / Rev. H 6/ Rev. G /

4 Features Rev. F / Rev. E 6/ Rev. D 4/ Rev. C / Rev. B 2/ Rev. A /

5 Features List of Figures Figure : 52Mb Mobile LPDDR Part Numbering... 2 Figure 2: Functional Block Diagram x Figure 3: Functional Block Diagram x32... Figure 4: 6-Ball VFBGA Top View, x6 only... Figure 5: 9-Ball VFBGA Top View, x32 only... 2 Figure 6: 6-Ball VFBGA 8mm x 9mm, Package Code: BF... 5 Figure 7: 9-Ball VFBGA 8mm x 3mm, Package Code: B Figure 8: Typical Self Refresh Current vs. Temperature Figure 9: ACTIVE Command Figure : READ Command Figure : WRITE Command Figure 2: PRECHARGE Command... 4 Figure 3: DEEP POWER-DOWN Command... 4 Figure 4: Simplified State Diagram Figure 5: Initialize and Load Mode Registers Figure 6: Alternate Initialization with E LOW... 5 Figure 7: Standard Mode Register Definition... 5 Figure 8: CAS Latency Figure 9: Extended Mode Register Figure 2: Status Read Register Timing Figure 2: Status Register Definition Figure 22: READ Burst... 6 Figure 23: Consecutive READ Bursts Figure 24: Nonconsecutive READ Bursts Figure 25: Random Read Accesses Figure 26: Terminating a READ Burst Figure 27: READ-to-WRITE Figure 28: READ-to-PRECHARGE Figure 29: Data Output Timing t DQSQ, t QH, and Data Valid Window x Figure 3: Data Output Timing t DQSQ, t QH, and Data Valid Window x Figure 3: Data Output Timing t AC and t DQS... 7 Figure 32: Data Input Timing Figure 33: Write DM Operation Figure 34: WRITE Burst Figure 35: Consecutive WRITE-to-WRITE Figure 36: Nonconsecutive WRITE-to-WRITE Figure 37: Random WRITE Cycles Figure 38: WRITE-to-READ Uninterrupting Figure 39: WRITE-to-READ Interrupting Figure 4: WRITE-to-READ Odd Number of Data, Interrupting Figure 4: WRITE-to-PRECHARGE Uninterrupting... 8 Figure 42: WRITE-to-PRECHARGE Interrupting... 8 Figure 43: WRITE-to-PRECHARGE Odd Number of Data, Interrupting Figure 44: Bank Read With Auto Precharge Figure 45: Bank Read Without Auto Precharge Figure 46: Bank Write With Auto Precharge Figure 47: Bank Write Without Auto Precharge Figure 48: Auto Refresh Mode Figure 49: Self Refresh Mode... 9 Figure 5: Power-Down Entry in Active or Precharge Mode

6 Features Figure 5: Power-Down Mode Active or Precharge Figure 52: Deep Power-Down Mode Figure 53: Clock Stop Mode

7 Features List of Tables Table : Key Timing Parameters CL = 3... Table 2: Configuration Addressing... 2 Table 3: Ball Descriptions... 3 Table 4: Absolute Maximum Ratings... 7 Table 5: AC/DC Electrical Characteristics and Operating Conditions... 7 Table 6: Capacitance x6, x Table 7: I DD Specifications and Conditions, 4 C to +85 C x Table 8: I DD Specifications and Conditions, 4 C to +85 C x Table 9: I DD Specifications and Conditions, 4 C to +5 C x Table : I DD Specifications and Conditions, 4 C to +5 C x Table : I DD6 Specifications and Conditions Table 2: Electrical Characteristics and Recommended AC Operating Conditions Table 3: Target Output Drive Characteristics Full Strength... 3 Table 4: Target Output Drive Characteristics Three-Quarter Strength Table 5: Target Output Drive Characteristics One-Half Strength Table 6: Truth Table Commands Table 7: DM Operation Truth Table Table 8: Truth Table Current State Bank n Command to Bank n Table 9: Truth Table Current State Bank n Command to Bank m Table 2: Truth Table E Table 2: Burst Definition Table

8 General Description 52Mb: x6, x32 Mobile LPDDR SDRAM General Description The 52Mb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic randomaccess memory containing 536,87,92 bits. It is internally configured as a quad-bank DRAM. Each of the x6 s 34,27,728-bit banks is organized as 892 rows by 24 columns by 6 bits. Each of the x32 s 34,27,728-bit banks is organized as 892 rows by 52 columns by 32 bits. In the reduced page-size LG option, each of the x32 s 34,27,728- bit banks are organized as 6,384 rows by 256 columns by 32 bits. Note:. Throughout this data sheet, various figures and text refer to DQs as DQ. DQ should be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x6 is divided into 2 bytes: the lower byte and the upper byte. For the lower byte DQ[7:], DM refers to LDM and DQS refers to LDQS. For the upper byte DQ[5:8], DM refers to UDM and DQS refers to UDQS. The x32 is divided into 4 bytes. For DQ[7:], DM refers to DM and DQS refers to DQS. For DQ[5:8], DM refers to DM and DQS refers to DQS. For DQ[23:6], DM refers to DM2 and DQS refers to DQS2. For DQ[3:24], DM refers to DM3 and DQS refers to DQS3. 2. Complete functionality is described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. 3. Any specific requirement takes precedence over a general statement. 8

9 Functional Block Diagrams Functional Block Diagrams Figure 2: Functional Block Diagram x6 E # CS# WE# CAS# RAS# Command decode Control logic Refresh counter Bank 3 Bank Bank 2 Standard mode register Extended mode register Rowaddress Mux Bank rowaddress latch and decoder Bank memory array 6 Data Sense amplifiers 32 Read latch 6 MUX 6 DRVRS DQS generator 2 Address BA, BA Address register 2 2 Bank control logic Columnaddress counter/ latch I/O gating DM mask logic Column decoder Write FIFO and drivers out in COL Mask Data 4 32 COL Input registers DQS RCVRS DQ[5:] LDQS, UDQS LDM, UDM 9

10 Functional Block Diagrams Figure 3: Functional Block Diagram x32 E # CS# WE# CAS# RAS# Command decode Control logic Refresh counter Bank 3 Bank Bank 2 Standard mode register Extended mode register Rowaddress MUX Bank rowaddress latch and decoder Bank memory array 32 Data Sense amplifiers 64 Read latch 32 MUX 32 DRVRS Address, BA, BA Address register 2 2 Bank control logic Columnaddress counter/ latch I/O gating DM mask logic Column decoder Write FIFO and drivers out in COL Mask Data 8 64 COL DQS generator Input registers DQS RCVRS DQ[3:] DQS DQS DQS2 DQS3 DM DM DM2 DM3

11 Ball Assignments Ball Assignments Figure 4: 6-Ball VFBGA Top View, x6 only A V SS DQ5 V SSQ V DDQ DQ V DD B V DDQ DQ3 DQ4 DQ DQ2 V SSQ C V SSQ DQ DQ2 DQ3 DQ4 V DDQ D V DDQ DQ9 DQ DQ5 DQ6 TEST E V SSQ UDQS DQ8 DQ7 LDQS V DDQ F V SS UDM NC A3 LDM V DD G E # WE# CAS# RAS# H A9 A A2 CS# BA BA J A6 A7 A8 A/AP A A K V SS A4 A5 A2 A3 V DD Notes:. D9 is a test pin that must be tied to V SS or V SSQ in normal operations. 2. Unused address pins become RFU.

12 Ball Assignments Figure 5: 9-Ball VFBGA Top View, x32 only A V SS DQ3 V SSQ V DDQ DQ6 V DD B V DDQ DQ29 DQ3 DQ7 DQ8 V SSQ C V SSQ DQ27 DQ28 DQ9 DQ2 V DDQ D V DDQ DQ25 DQ26 DQ2 DQ22 TEST E V SSQ DQS3 DQ24 DQ23 DQS2 V DDQ F V DD DM3 NC A3 DM2 V SS G E # WE# CAS# RAS# H A9 A A2 CS# BA BA J A6 A7 A8 A/AP A A K A4 DM A5 A2 DM A3 L V SSQ DQS DQ8 DQ7 DQS V DDQ M V DDQ DQ9 DQ DQ5 DQ6 V SSQ N V SSQ DQ DQ2 DQ3 DQ4 V DDQ P V DDQ DQ3 DQ4 DQ DQ2 V SSQ R V SS DQ5 V SSQ V DDQ DQ V DD Notes:. D9 is a test pin that must be tied to V SS or V SSQ in normal operations. 2. Unused address pins become RFU. 2

13 Ball Descriptions Table 3: Ball Descriptions The ball descriptions table is a comprehensive list of all possible balls for all supported packages. Not all balls listed are supported for a given package. Symbol Type Description, # Input Clock: is the system clock input. and # are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of and the negative edge of #. Input and output data is referenced to the crossing of and # both directions of the crossing. E E, E CS# CS#, CS# Input Input Clock enable: E HIGH activates, and E LOW deactivates, the internal clock signals, input buffers, and output drivers. Taking E LOW enables PRECHARGE power-down and SELF REFRESH operations all banks idle, or ACTIVE power-down row active in any bank. E is synchronous for all functions except SELF REFRESH exit. All input buffers except E are disabled during power-down and self refresh modes. E is used for a single LPDDR product. E is used for dual LPDDR products and is considered RFU for single LPDDR MCPs. Chip select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. CS# is used for a single LPDDR product. CS# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# along with CS# define the command being entered. UDM, LDM x6 DM[3:] x32 Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of DQ and DQS balls. BA, BA Input Bank address inputs: BA and BA define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA and BA also determine which mode register is loaded during a LOAD MODE REGISTER command. A[3:] Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit A for READ or WRITE commands, to select one location out of the memory array in the respective bank. During a PRECHARGE command, A determines whether the PRECHARGE applies to one bank A LOW, bank selected by BA, BA or all banks A HIGH. The address inputs also provide the op-code during a LOAD MODE REGISTER command. The maximum address range is dependent upon configuration. Unused address balls become RFU. TEST Input Test pin: Must be tied to V SS or V SSQ in normal operations. DQ[5:] x6 DQ[3:] x32 LDQS, UDQS x6 DQS[3:] x32 Input/ output Input/ output Data input/output: Data bus for x6 and x32. 52Mb: x6, x32 Mobile LPDDR SDRAM Ball Descriptions Data strobe: Output with read data, input with write data. DQS is edge-aligned with read data, center-aligned in write data. It is used to capture data. TQ Output Temperature sensor output: TQ HIGH when LPDDR T J exceeds 85 C. V DDQ Supply DQ power supply. 3

14 Ball Descriptions Table 3: Ball Descriptions Continued Symbol Type Description V SSQ Supply DQ ground. V DD Supply Power supply. V SS Supply Ground. NC No connect: May be left unconnected. RFU Reserved for future use. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. 4

15 Package Dimensions Package Dimensions Figure 6: 6-Ball VFBGA 8mm x 9mm, Package Code: BF Seating plane A.2 A 6X Ø.45 Dimensions apply to solder balls post-reflow on Ø.4 SMD ball pads. Solder ball material: SAC5 98.5% Sn, % Ag,.5% Cu. Ball A ID covered by SR Ball A ID A B C 9 ±. 7.2 CTR D E F G H.8 TYP J K.8 TYP 6.4 CTR.9 ±..275 MIN 8 ±. Note:. All dimensions are in millimeters. 5

16 Package Dimensions Figure 7: 9-Ball VFBGA 8mm x 3mm, Package Code: B5 Seating plane A.2 A 9X Ø.45 Dimensions apply to solder balls post-reflow on Ø.4 SMD ball pads. Solder ball material: SAC % Sn, 3% Ag,.5% Cu OR SAC5 98.5% Sn, % Ag,.5% Cu Ball A ID covered by SR 3 2 Ball A ID.2 CTR 3 ±..8 TYP A B C D E F G H J K L M N P R.8 TYP 6.4 CTR.9 ±..275 MIN 8 ±. Note:. All dimensions are in millimeters. 6

17 Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 4: Absolute Maximum Ratings Note applies to all parameters in this table Parameter Symbol Min Max Unit V DD /V DDQ supply voltage relative to V SS V DD /V DDQ. 2.4 V Voltage on any pin relative to V SS V IN or V DDQ +.3V, V whichever is less Storage temperature plastic T STG 55 5 C Note:. V DD and V DDQ must be within 3mV of each other at all times. V DDQ must not exceed V DD. Table 5: AC/DC Electrical Characteristics and Operating Conditions Notes 5 apply to all parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Symbol Min Max Unit Notes Supply voltage V DD.7.95 V 6, 7 I/O supply voltage V DDQ.7.95 V 6, 7 Address and command inputs Input voltage high V IH.8 V DDQ V DDQ +.3 V 8, 9 Input voltage low V IL.3.2 V DDQ V 8, 9 Clock inputs, # DC input voltage V IN.3 V DDQ +.3 V DC input differential voltage V IDDC.4 V DDQ V DDQ +.6 V, AC input differential voltage V IDAC.6 V DDQ V DDQ +.6 V, AC differential crossing voltage V IX.4 V DDQ.6 V DDQ V, 2 Data inputs DC input high voltage V IHDC.7 V DDQ V DDQ +.3 V 8, 9, 3 DC input low voltage V ILDC.3.3 V DDQ V 8, 9, 3 AC input high voltage V IHAC.8 V DDQ V DDQ +.3 V 8, 9, 3 AC input low voltage V ILAC.3.2 V DDQ V 8, 9, 3 Data outputs DC output high voltage: Logic I OH =.ma V OH.9 V DDQ V DC output low voltage: Logic I OL =.ma V OL. V DDQ V Leakage current Input leakage current Any input V V IN V DD All other pins not under test = V I I μa 7

18 Electrical Specifications Table 5: AC/DC Electrical Characteristics and Operating Conditions Continued Notes 5 apply to all parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Symbol Min Max Unit Notes Output leakage current I OZ 5 5 μa DQ are disabled; V V OUT V DDQ Operating temperature Commercial T A +7 C Industrial T A C Automotive T A 4 +5 C Notes:. All voltages referenced to V SS. 2. All parameters assume proper device initialization. 3. Tests for AC timing, I DD, and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 4. Outputs measured with equivalent load; transmission line delay is assumed to be very small: I/O 5 5 I/O 2pF pf Full drive strength Half drive strength 5. Timing and I DD tests may use a V IL -to-v IH swing of up to.5v in the test environment, but input timing is still referenced to V DDQ /2 or to the crossing point for /#. The output timing reference voltage level is V DDQ /2. 6. Any positive glitch must be less than one-third of the clock cycle and not more than +2mV or 2.V, whichever is less. Any negative glitch must be less than one-third of the clock cycle and not exceed either 5mV or +.6V, whichever is more positive. 7. V DD and V DDQ must track each other and V DDQ must be less than or equal to V DD. 8. To maintain a valid level, the transitioning edge of the input must: 8a. Sustain a constant slew rate from the current AC level through to the target AC level, V ILAC Or V IHAC. 8b. Reach at least the target AC level. 8c. After the AC target level is reached, continue to maintain at least the target DC level, V ILDC or V IHDC. 9. V IH overshoot: V IHmax = V DDQ +.V for a pulse width 3ns and the pulse width cannot be greater than one-third of the cycle rate. V IL undershoot: V ILmin =.V for a pulse width 3ns and the pulse width cannot be greater than one-third of the cycle rate.. and # input slew rate must be V/ns 2 V/ns if measured differentially.. V ID is the magnitude of the difference between the input level on and the input level on #. 2. The value of V IX is expected to equal V DDQ/2 of the transmitting device and must track variations in the DC level of the same. 3. DQ and DM input slew rates must not deviate from DQS by more than %. 5ps must be added to t DS and t DH for each mv/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. 8

19 Electrical Specifications Table 6: Capacitance x6, x32 Note applies to all the parameters in this table Parameter Symbol Min Max Unit Notes Input capacitance:, # C.5 3. pf Delta input capacitance:, # C D.25 pf 2 Input capacitance: command and address C I.5 3. pf Delta input capacitance: command and address C DI.5 pf 2 Input/output capacitance: DQ, DQS, DM C IO pf Delta input/output capacitance: DQ, DQS, DM C DIO.5 pf 3 Notes:. This parameter is sampled. V DD /V DDQ =.7.95V, f = MHz, T A = 25 C, V OUTDC = V DDQ/2, V OUT peak-to-peak =.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 2. The input capacitance per pin group will not differ by more than this maximum amount for any given device. 3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 9

20 Electrical Specifications I DD Parameters 52Mb: x6, x32 Mobile LPDDR SDRAM Electrical Specifications I DD Parameters Table 7: I DD Specifications and Conditions, 4 C to +85 C x6 Notes 5 apply to all the parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Symbol Unit Notes Operating bank active precharge current: t RC = t RC MIN; t I DD ma 6 = t MIN; E is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable Precharge power-down standby current: All banks idle; E is LOW; CS is HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge power-down standby current: Clock stopped; All banks idle; E is LOW; CS is HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: All banks idle; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: Clock stopped; All banks idle; E = HIGH; CS = HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: bank active; E = LOW; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: Clock stopped; bank active; E = LOW; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: bank active; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: Clock stopped; bank active; E = HIGH; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Operating burst read: bank active; BL = 4; t = t MIN; Continuous READ bursts; Iout = ma; Address inputs are switching every 2 clock cycles; 5% data changing each burst Operating burst write: bank active; BL = 4; t = t MIN; Continuous WRITE bursts; Address inputs are switching; 5% data changing each burst Max I DD2P μa 7, 8 I DD2PS μa 7 I DD2N ma 9 I DD2NS ma 9 I DD3P ma 8 I DD3PS ma I DD3N ma 6 I DD3NS ma 6 I DD4R 5 5 ma 6 I DD4W 5 5 ma 6 Auto refresh: Burst refresh; E = HIGH; Address t RFC = 38ns I DD ma and control inputs are switching; Data bus inputs are stable t RFC = t REFI I DD5A ma, Deep power-down current: Address and control balls are stable; Data bus inputs are stable I DD8 μa 7, 3 2

21 Electrical Specifications I DD Parameters Table 8: I DD Specifications and Conditions, 4 C to +85 C x32 Notes 5 apply to all the parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Operating bank active precharge current: t RC = t RC MIN; t = t MIN; E is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable JEDEC-standard option Reduced page size option Precharge power-down standby current: All banks idle; E is LOW; CS is HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge power-down standby current: Clock stopped; All banks idle; E is LOW; CS is HIGH, = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: All banks idle; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: Clock stopped; All banks idle; E = HIGH; CS = HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: bank active; E = LOW; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: Clock stopped; bank active; E = LOW; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: bank active; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: Clock stopped; bank active; E = HIGH; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Operating burst read: bank active; BL = 4; CL = 3; t = t MIN; Continuous READ bursts; Iout = ma; Address inputs are switching every 2 clock cycles; 5% data changing each burst Operating burst write: One bank active; BL = 4; t = t MIN; Continuous WRITE bursts; Address inputs are switching; 5% data changing each burst Symbol Max Unit Notes I DD ma 6 I DD ma 6 I DD2P μa 7, 8 I DD2PS μa 7 I DD2N ma 9 I DD2NS ma 9 I DD3P ma 8 I DD3PS ma I DD3N ma 6 I DD3NS ma 6 I DD4R 5 5 ma 6 I DD4W 5 5 ma 6 Auto refresh: Burst refresh; E = HIGH; Address t RFC = 38ns I DD ma and control inputs are switching; Data bus inputs are stable t RFC = t REFI I DD5A ma, Deep power-down current: Address and control pins are stable; Data bus inputs are stable I DD8 μa 7, 3 2

22 Electrical Specifications I DD Parameters Table 9: I DD Specifications and Conditions, 4 C to +5 C x6 Notes 5 apply to all the parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Symbol Unit Notes Operating bank active precharge current: t RC = t RC MIN; t I DD ma 6 = t MIN; E is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable Precharge power-down standby current: All banks idle; E is LOW; CS is HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge power-down standby current: Clock stopped; All banks idle; E is LOW; CS is HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: All banks idle; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: Clock stopped; All banks idle; E = HIGH; CS = HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: bank active; E = LOW; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: Clock stopped; bank active; E = LOW; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: bank active; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: Clock stopped; bank active; E = HIGH; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Operating burst read: bank active; BL = 4; t = t MIN; Continuous READ bursts; Iout = ma; Address inputs are switching every 2 clock cycles; 5% data changing each burst Operating burst write: bank active; BL = 4; t = t MIN; Continuous WRITE bursts; Address inputs are switching; 5% data changing each burst Max I DD2P μa 7, 8 I DD2PS μa 7 I DD2N ma 9 I DD2NS ma 9 I DD3P ma 8 I DD3PS ma I DD3N ma 6 I DD3NS ma 6 I DD4R 5 5 ma 6 I DD4W 5 5 ma 6 Auto refresh: Burst refresh; E = HIGH; Address t RFC = 38ns I DD ma and control inputs are switching; Data bus inputs are stable t RFC = t REFI I DD5A ma, Deep power-down current: Address and control balls are stable; Data bus inputs are stable I DD μa 7, 3 22

23 Electrical Specifications I DD Parameters Table : I DD Specifications and Conditions, 4 C to +5 C x32 Notes 5 apply to all the parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Operating bank active precharge current: t RC = t RC MIN; t = t MIN; E is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable JEDEC-standard option Reduced page size option Precharge power-down standby current: All banks idle; E is LOW; CS is HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge power-down standby current: Clock stopped; All banks idle; E is LOW; CS is HIGH, = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: All banks idle; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: Clock stopped; All banks idle; E = HIGH; CS = HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: bank active; E = LOW; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: Clock stopped; bank active; E = LOW; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: bank active; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: Clock stopped; bank active; E = HIGH; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Operating burst read: bank active; BL = 4; CL = 3; t = t MIN; Continuous READ bursts; Iout = ma; Address inputs are switching every 2 clock cycles; 5% data changing each burst Operating burst write: One bank active; BL = 4; t = t MIN; Continuous WRITE bursts; Address inputs are switching; 5% data changing each burst Symbol Max Unit Notes I DD ma 6 I DD ma 6 I DD2P μa 7, 8 I DD2PS μa 7 I DD2N ma 9 I DD2NS ma 9 I DD3P ma 8 I DD3PS ma I DD3N ma 6 I DD3NS ma 6 I DD4R 5 5 ma 6 I DD4W 5 5 ma 6 Auto refresh: Burst refresh; E = HIGH; Address t RFC = 38ns I DD ma and control inputs are switching; Data bus inputs are stable t RFC = t REFI I DD5A ma, Deep power-down current: Address and control pins are stable; Data bus inputs are stable I DD μa 7, 3 23

24 Electrical Specifications I DD Parameters Table : I DD6 Specifications and Conditions Notes 5, 7, and 2 apply to all the parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Symbol Standard Unit Self refresh Full array, 5 C I DD6 n/a 4 μa E = LOW; t = t MIN; Address Full array, 85 C 7 μa and control inputs are stable; Data bus inputs are stable Full array, 45 C 39 μa /2 array, 85 C 52 μa /2 array, 45 C 3 μa /4 array, 85 C 43 μa /4 array, 45 C 275 μa /8 array, 85 C 43 μa /8 array, 45 C 275 μa /6 array, 85 C 375 μa /6 array, 45 C 25 μa Notes:. All voltages referenced to V SS. 2. Tests for I DD characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Timing and I DD tests may use a V IL -to-v IH swing of up to.5v in the test environment, but input timing is still referenced to V DDQ/2 or to the crossing point for /#. The output timing reference voltage level is V DDQ/2. 4. I DD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open. 5. I DD specifications are tested after the device is properly initialized and values are averaged at the defined cycle rate. 6. MIN t RC or t RFC for I DD measurements is the smallest multiple of t that meets the minimum absolute value for the respective parameter. t RASmax for I DD measurements is the largest multiple of t that meets the maximum absolute value for t RAS. 7. Measurement is taken 5ms after entering into this operating mode to provide settling time for the tester. 8. V DD must not vary more than 4% if E is not active while any bank is active. 9. I DD2N specifies DQ, DQS, and DM to be driven to a valid high or low logic level.. E must be active HIGH during the entire time a REFRESH command is executed. From the time the AUTO REFRESH command is registered, E must be active at each rising clock edge until t RFC later.. This limit is a nominal value and does not result in a fail. E is HIGH during REFRESH command period t RFC MIN else E is LOW for example, during standby. 2. Values for I DD6 85 C are guaranteed for the entire temperature range. All other I DD6 values are estimated. 3. Typical values at 25 C, not a maximum value. 4. Self refresh is not supported for AT 85 C to 5 C operation. 24

25 Electrical Specifications I DD Parameters Figure 8: Typical Self Refresh Current vs. Temperature I DD6 μa Full Half Quarter Eighth Sixteenth

26 Electrical Specifications AC Operating Conditions Electrical Specifications AC Operating Conditions Table 2: Electrical Characteristics and Recommended AC Operating Conditions Notes 9 apply to all the parameters in this table; V DD /V DDQ =.7.95V Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Access window of CL = 3 t AC ns DQ from /# CL = Clock cycle time CL = 3 t ns CL = high-level width t CH t low-level width t CL t E minimum pulse width t E t high and low Auto precharge write t DAL 2 recovery + precharge time DQ and DM input hold time relative to DQS fast slew rate DQ and DM input hold time relative to DQS slow slew rate DQ and DM input setup time relative to DQS fast slew rate DQ and DM input setup time relative to DQS slow slew rate t DH f ns 3, 4, 5 t DH s ns t DS f ns 3, 4, 5 t DS s ns DQ and DM input pulse width for each input t DIPW ns 6 Access window of CL = 3 t DQS ns DQS from /# CL = ns DQS input high pulse t DQSH t width DQS input low pulse width t DQSL t DQS DQ skew, DQS to last DQ valid, per group, per access t DQSQ ns 3, 7 WRITE command to first DQS latching transition DQS falling edge from rising hold time DQS falling edge to rising setup time t DQSS t t DSH t t DSS t 26

27 Electrical Specifications AC Operating Conditions Table 2: Electrical Characteristics and Recommended AC Operating Conditions Continued Notes 9 apply to all the parameters in this table; V DD /V DDQ =.7.95V Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Data valid output window n/a t QH - t DQSQ t QH - t DQSQ t QH - t DQSQ t QH - t DQSQ ns 7 DVW Half-clock period t HP t CH, t CH, t CH, t CH, ns 8 t CL t CL t CL t CL Data-out High-Z window from /# CL = 3 t HZ ns 9, 2 CL = ns Data-out Low-Z window from /# Address and control input hold time fast slew rate Address and control input hold time slow slew rate Address and control input setup time fast slew rate Address and control input setup time slow slew rate t LZ.... ns 9 t IH F ns 5, 2 t IH S ns t IS F ns 5, 2 t IS S ns Address and control input pulse width t IPW t IS + t IH ns 6 LOAD MODE REGISTER command cycle time t MRD t DQ DQS hold, DQS to first DQ to go nonvalid, per access t QH t HP - t QHS t HP - t QHS t HP - t QHS t HP - t QHS ns 3, 7 Data hold skew factor t QHS ns ACTIVE-to-PRECHARGE command ACTIVE to ACTIVE/ACTIVE to AUTO REFRESH command period Active to read or write delay t RAS 4 7, 42 7, 42 7, 45 7, ns 22 t RC ns 23 t RCD ns Refresh period t REF ms 24 Average periodic refresh interval: 64Mb, 28Mb, and 256Mb x32 Average periodic refresh interval: 256Mb, 52Mb, Gb, 2Gb AUTO REFRESH command period t REFI μs 24 t REFI μs 24 t RFC ns 27

28 Electrical Specifications AC Operating Conditions Table 2: Electrical Characteristics and Recommended AC Operating Conditions Continued Notes 9 apply to all the parameters in this table; V DD /V DDQ =.7.95V Parameter Symbol Min Max Min Max Min Max Min Max Unit PRECHARGE command t RP ns period DQS read preamble CL = 3 t RPRE t CL = 2 t RPRE t DQS read postamble t RPST t Active bank a to active t RRD ns bank b command Read of SRR to next valid t SRC CL + CL + CL + CL + t command SRR to read t SRR t Internal temperature sensor t TQ ms valid temperature out- put enable Notes DQS write preamble t WPRE t DQS write preamble setup t WPRES ns 25, 26 time DQS write postamble t WPST t 27 Write recovery time t WR ns 28 Internal WRITE-to-READ t WTR 2 2 t command delay Exit power-down mode to t XP 2 2 t first valid command Exit self refresh to first valid command t XSR ns 29 Notes:. All voltages referenced to V SS. 2. All parameters assume proper device initialization. 3. Tests for AC timing and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage ranges specified. 4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system environment. Specifications are correlated to production test conditions generally a coaxial transmission line terminated at the tester electronics. For the half-strength driver with a nominal pf load, parameters t AC and t QH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by design/characterization. Use of IBIS or other simu- 28

29 Electrical Specifications AC Operating Conditions lation tools for system design validation is suggested. I/O 5 5 I/O 2pF pf Full drive strength Half drive strength 5. The /# input reference voltage level for timing referenced to /# is the point at which and # cross; the input reference voltage level for signals other than /# is V DDQ/2. 6. A and # input slew rate V/ns 2 V/ns if measured differentially is assumed for all parameters. 7. All AC timings assume an input slew rate of V/ns. 8. CAS latency definition: with CL = 2, the first data element is valid at t + t AC after the clock at which the READ command was registered; for CL = 3, the first data element is valid at 2 t + t AC after the first clock at which the READ command was registered. 9. Timing tests may use a V IL -to-v IH swing of up to.5v in the test environment, but input timing is still referenced to V DDQ/2 or to the crossing point for /#. The output timing reference voltage level is V DDQ/2.. Clock frequency change is only permitted during clock stop, power-down, or self refresh mode.. In cases where the device is in self refresh mode for t E, t E starts at the rising edge of the clock and ends when E transitions HIGH. 2. t DAL = t WR/ t + t RP/ t : for each term, if not already an integer, round up to the next highest integer. 3. Referenced to each output group: for x6, LDQS with DQ[7:]; and UDQS with DQ[5:8]. For x32, DQS with DQ[7:]; DQS with DQ[5:8]; DQS2 with DQ[23:6]; and DQS3 with DQ[3:24]. 4. DQ and DM input slew rates must not deviate from DQS by more than %. If the DQ/DM/DQS slew rate is less than. V/ns, timing must be derated: 5ps must be added to t DS and t DH for each mv/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, functionality is uncertain. 5. The transition time for input signals CAS#, E, CS#, DM, DQ, DQS, RAS#, WE#, and addresses are measured between V ILDC to V IHAC for rising input signals and V IHDC to V ILAC for falling input signals. 6. These parameters guarantee device timing but are not tested on each device. 7. The valid data window is derived by achieving other specifications: t HP t /2, t DQSQ, and t QH t HP - t QHS. The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is provided a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. 8. t HP MIN is the lesser of t CL MIN and t CH MIN actually applied to the device and # inputs, collectively. 9. t HZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving t HZ or begins driving t LZ. 2. t HZ MAX will prevail over t DQS MAX + t RPST MAX condition. 2. Fast command/address input slew rate V/ns. Slow command/address input slew rate.5 V/ns. If the slew rate is less than.5 V/ns, timing must be derated: t IS has an additional 5ps per each mv/ns reduction in slew rate from the.5 V/ns. t IH has ps added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. 22. READs and WRITEs with auto precharge must not be issued until t RAS MIN can be satisfied prior to the internal PRECHARGE command being issued. 29

30 Electrical Specifications AC Operating Conditions 23. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime. 24. For the automotive temperature parts, t REF = t REF/2 and t REFI = t REFI/ This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 26. It is recommended that DQS be valid HIGH or LOW on or before the WRITE command. The case shown DQS going from High-Z to logic low applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on t DQSS. 27. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance bus turnaround will degrade accordingly. 28. At least clock cycle is required during t WR time when in auto precharge mode. 29. Clock must be toggled a minimum of two times during the t XSR period. 3

31 Output Drive Characteristics Output Drive Characteristics Table 3: Target Output Drive Characteristics Full Strength Notes 2 apply to all values; characteristics are specified under best and worst process variations/conditions Pull-Down Current ma Pull-Up Current ma Voltage V Min Max Min Max Notes:. Based on nominal impedance of 25Ω full strength at V DDQ /2. 2. The full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. 3

32 Output Drive Characteristics Table 4: Target Output Drive Characteristics Three-Quarter Strength Notes 3 apply to all values; characteristics are specified under best and worst process variations/conditions Pull-Down Current ma Pull-Up Current ma Voltage V Min Max Min Max Notes:. Based on nominal impedance of 37Ω three-quarter drive strength at V DDQ /2. 2. The full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. 3. Contact factory for availability of three-quarter drive strength. 32

33 Output Drive Characteristics Table 5: Target Output Drive Characteristics One-Half Strength Notes 3 apply to all values; characteristics are specified under best and worst process variations/conditions Pull-Down Current ma Pull-Up Current ma Voltage V Min Max Min Max Notes:. Based on nominal impedance of 55Ω one-half drive strength at V DDQ /2. 2. The full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. 3. The I-V curve for one-quarter drive strength is approximately 5% of one-half drive strength. 33

34 Functional Description 52Mb: x6, x32 Mobile LPDDR SDRAM Functional Description The Mobile LPDDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O. Single read or write access for the device consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clockcycle data transfers at the I/O. A bidirectional data strobe DQS is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the device during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x6 device has two data strobes, one for the lower byte and one for the upper byte; the x32 device has four data strobes, one per byte. The LPDDR device operates from a differential clock and #; the crossing of going HIGH and # going LOW will be referred to as the positive edge of. Commands address and control signals are registered at every positive edge of. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of. Read and write accesses to the device are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The device provides for programmable READ or WRITE burst lengths of 2, 4, 8, or 6. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of LPDDR supports concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. Deep power-down mode is offered to achieve maximum power reduction by eliminating the power of the memory array. Data will not be retained after the device enters deep power-down mode. Two self refresh features, temperature-compensated self refresh TCSR and partial-array self refresh PASR, offer additional power savings. TCSR is controlled by the automatic on-chip temperature sensor. PASR can be customized using the extended mode register settings. The two features can be combined to achieve even greater power savings. The DLL that is typically used on standard DDR devices is not necessary on LPDDR devices. It has been omitted to save power. 34

35 Commands Commands A quick reference for available commands is provided in Table 6 and Table 7 page 36, followed by a written description of each command. Three additional truth tables Table 8 page 42, Table 9 page 44, and Table 2 page 46 provide E commands and current/next state information. Table 6: Truth Table Commands E is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN; all states and sequences not shown are reserved and/or illegal Name Function CS# RAS# CAS# WE# Address Notes DESELECT NOP H X X X X NO OPERATION NOP L H H H X ACTIVE select bank and activate row L L H H Bank/row 2 READ select bank and column, and start READ burst L H L H Bank/column 3 WRITE select bank and column, and start WRITE burst L H L L Bank/column 3 BURST TERMINATE or DEEP POWER-DOWN enter deep L H H L X 4, 5 power-down mode PRECHARGE deactivate row in bank or banks L L H L Code 6 AUTO REFRESH refresh all or single bank or SELF RE- L L L H X 7, 8 FRESH enter self refresh mode LOAD MODE REGISTER L L L L Op-code 9 Notes:. DESELECT and NOP are functionally interchangeable. 2. BA BA provide bank address and A[:I] provide row address where I = the most significant address bit for each configuration. 3. BA BA provide bank address; A[:I] provide column address where I = the most significant address bit for each configuration; A HIGH enables the auto precharge feature nonpersistent; A LOW disables the auto precharge feature. 4. Applies only to READ bursts with auto precharge disabled; this command is undefined and should not be used for READ bursts with auto precharge enabled and for WRITE bursts. 5. This command is a BURST TERMINATE if E is HIGH and DEEP POWER-DOWN if E is LOW. 6. A LOW: BA BA determine which bank is precharged. A HIGH: all banks are precharged and BA BA are Don t Care. 7. This command is AUTO REFRESH if E is HIGH, SELF REFRESH if E is LOW. 8. Internal refresh counter controls row addressing; in self refresh mode all inputs and I/Os are Don t Care except for E. 9. BA BA select the standard mode register, extended mode register, or status register. 35