Automotive DDR SDRAM MT46V32M8 8 Meg x 8 x 4 banks MT46V16M16 4 Meg x 16 x 4 banks
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1 Automotive DDR SDRAM MT46V32M8 8 Meg x 8 x 4 banks MT46V16M16 4 Meg x 16 x 4 banks 256Mb: x8, x16 Automotive DDR SDRAM Features Features V DD = 2.5V ±.2V, V D = 2.5V ±.2V V DD = 2.6V ±.1V, V D = 2.6V ±.1V DDR4 1 Bidirectional data strobe transmitted/ received with data, that is, source-synchronous data capture x16 has two one per byte Internal, pipelined double-data-rate DDR architecture; two data accesses per clock cycle Differential clock inputs and # Commands entered on each positive edge edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align and transitions with Four internal banks for concurrent operation Data mask DM for masking write data x16 has two one per byte Programmable burst lengths BL: 2, 4, or 8 Auto refresh 64ms, 8192-cycleAIT 16ms, 8192-cycle AAT Self refresh not available on AAT devices Longer-lead TSOP for improved reliability OCPL 2.5V I/O SSTL_2-compatible Concurrent auto precharge option supported t RAS lockout supported t RAP = t RCD AEC-Q1 PPAP submission 8D response time Options Marking Configuration 32 Meg x 8 8 Meg x 8 x 4 banks 32M8 16 Meg x 16 4 Meg x 16 x 4 banks 16M16 Plastic package OCPL 66-pin TSOP TG 66-pin TSOP Pb-free P Plastic package 6-ball FBGA 8mm x 12.5mm CV 6-ball FBGA 8mm x 12.5mm CY Pb-free Timing cycle time CL = 3 DDR4-5B Self refresh Standard None Low-power self refresh L Temperature rating Industrial 4 C to +85 C AIT Automotive 4 C to +15 C AAT Revision x8, x16 :M Notes: 1. DDR4 devices operating at < DDR333 conditions can use V DD /V D = 2.5V +.2V. 2. Not all options listed can be combined to define an offered product. Use the Part Catalog Search on for product offerings and availability. 256mb_x8x16_at_ddr_t66a_d1.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.
2 Features Table 1: Key Timing Parameters CL = CAS READ latency; MIN clock rate with 5% duty cycle at CL = 2-75E, -75Z, CL = 2.5-6, -6T, -75, and CL = 3-5B Speed Grade Clock Rate MHz CL = 2 CL = 2.5 CL = 3 Data-Out Window Access Window Skew -5B ns ±.7ns +.4ns n/a 2.1ns ±.7ns +.4ns 6T n/a 2.ns ±.7ns +.45ns -75E/-75Z n/a 2.5ns ±.75ns +.5ns n/a 2.5ns ±.75ns +.5ns Table 2: Addressing Parameter 32 Meg x 8 16 Meg x 16 Configuration 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks Refresh count 8K 8K Row address 8K A[12:] 8K A[12:] Bank address 4 BA[1:] 4 BA[1:] Column address 1K A[9:] 512 A[8:] Table 3: Speed Grade Compatibility Marking PC PC PC PC PC PC B 1 Yes Yes Yes Yes Yes Yes -6 Yes Yes Yes Yes Yes -6T Yes Yes Yes Yes Yes -75E Yes Yes Yes Yes -75Z Yes Yes Yes -75 Yes Yes -5B -6/-6T -75E -75Z Notes: 1. The -5B device is backward compatible with all slower speed grades. The voltage range of -5B device operating at slower speed grades is V DD = V D = 2.5V ±.2V. 256mb_x8x16_at_ddr_t66a_d1.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
3 Features Figure 1: 256Mb DDR SDRAM Part Numbers Example Part Number: MT46V16M16P-5B AIT:M - MT46V Configuration Package Speed Sp. Op. Temp. : Revision Configuration 32 Meg x 8 32M8 16 Meg x 16 16M16 Package 4-mil TSOP 4-mil TSOP Pb-free 8mm x 12.5mm FBGA 8mm x 12.5mm FBGA Pb-free TG P CV CY L AIT AAT Revision :M x8, x16 Operating Temperature Automotive Industrial Temp Automotive Temp Special Options Standard Low power -5B Speed Grade t = 5ns, CL = 3 FBGA Part Marking System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron s Web site: 256mb_x8x16_at_ddr_t66a_d1.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
4 Table of Contents 256Mb: x8, x16 Automotive DDR SDRAM Table of Contents Features FBGA Part Marking System 3 State Diagram Functional Description General Notes Automotive Industrial Tempature Automotive Tempature Functional Block Diagrams Pin and Ball Assignments and Descriptions Package Dimensions Electrical Specifications I DD Electrical Specifications DC and AC Notes Commands DESELECT NO OPERATION NOP LOAD MODE REGISTER LMR ACTIVE ACT READ WRITE PRECHARGE PRE BURST TERMINATE BST AUTO REFRESH AR SELF REFRESH Operations INITIALIZATION REGISTER DEFINITION Mode Register 54 Extended Mode Register 57 ACTIVE READ WRITE PRECHARGE Auto Precharge 84 AUTO REFRESH SELF REFRESH Power-down E Not Active mb_x8x16_at_ddr_t66aTOC.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
5 State Diagram State Diagram Figure 2: Simplified State Diagram Power applied Power on PRE Precharge all banks LMR REFS Self refresh MR EMR LMR Idle all banks precharged REFSX REFA EL Auto refresh EH Active powerdown E HIGH ACT Precharge powerdown E LOW Row active Burst stop WRITE Write WRITE WRITE A READ A READ READ BST Read READ WRITE A READ A READ A Write A PRE PRE PRE Read A PRE Precharge PREALL Automatic sequence Command sequence ACT = ACTIVE BST = BURST TERMINATE EH = Exit power-down EL = Enter power-down EMR = Extended mode register LMR = LOAD MODE REGISTER MR = Mode register PRE = PRECHARGE PREALL = PRECHARGE all banks READ A = READ with auto precharge REFA = AUTO REFRESH REFS = Enter self refresh REFSX = Exit self refresh WRITE A = WRITE with auto precharge Note: This diagram represents operations within a single bank only and does not capture concurrent operations in other banks. DDR_x4x8x16_Core1.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
6 Functional Description 256Mb: x8, x16 Automotive DDR SDRAM Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. A bidirectional data strobe is transmitted externally, along with data, for use in data capture at the receiver. is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The DDR SDRAM operates from a differential clock and #; the crossing of going HIGH and # going LOW will be referred to as the positive edge of. Commands address and control signals are registered at every positive edge of. Input data is registered on both edges of, and output data is referenced to both edges of, as well as to both edges of. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which may then be followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs are SSTL_2, Class II compatible. General Notes The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. Throughout the data sheet, the various figures and text refer to s as. The term is to be interpreted as any and all collectively, unless specifically stated otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper byte. For the lower byte [7:] DM refers to LDM and refers to L. For the upper byte [15:8] DM refers to UDM and refers to U. Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. Any specific requirement takes precedence over a general statement. DDR_x4x8x16_Core1.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
7 Automotive Industrial Tempature Automotive Tempature 256Mb: x8, x16 Automotive DDR SDRAM Functional Description The automotive temperature AIT option, Ambient and case temperatures cannot be less than 4 C or greater than 85 C The automotive temperature AAT option adheres to the following specifications: 16ms refresh rate Self refresh not supported Ambient and case temperatures cannot be less than 4 C or greater than 15 C DDR_x4x8x16_Core1.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
8 Functional Block Diagrams 256Mb: x8, x16 Automotive DDR SDRAM Functional Block Diagrams The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a 4-bank DRAM. Figure 3: 32 Meg x 8 Functional Block Diagram E # CS# WE# CAS# RAS# COMMAND DECODE CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTERS 15 REFRESH 13 COUNTER 13 ROW- ADDRESS MUX 13 BANK ROW- ADDRESS 8192 LATCH & DECODER BANK MEMORY ARRAY 8192 x 512 x 16 8 DATA DLL SENSE AMPLIFIERS 16 READ LATCH 8 MUX 8 DRVRS 8192 GENERATOR 1 [7:] A[12:], BA[1:] 15 ADDRESS REGISTER 2 2 BANK CONTROL LOGIC I/O GATING DM MASK LOGIC 512 x16 COLUMN DECODER COL MASK WRITE FIFO 2 & DRIVERS 16 Out In DATA INPUT REGISTERS RCVRS DM 1 COLUMN- ADDRESS COUNTER/ LATCH 9 COL mb_x8x16_at_ddr_t66a_d2.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
9 Functional Block Diagrams Figure 4: 16 Meg x 16 Functional Block Diagram E # CS# WE# CAS# RAS# COMMAND DECODE CONTROL LOGIC REFRESH COUNTER BANK3 BANK1 BANK2 13 MODE REGISTERS ROW- ADDRESS MUX 13 BANK ROW- ADDRESS 8192 LATCH & DECODER BANK MEMORY ARRAY 8,192 x 256 x DATA DLL SENSE AMPLIFIERS 32 READ LATCH 16 MUX 16 DRVRS 8192 GENERATOR 2 [15:] A[12:], BA[1:] 15 ADDRESS REGISTER 2 2 BANK CONTROL LOGIC I/O GATING DM MASK LOGIC 256 x32 COLUMN DECODER COL MASK WRITE FIFO 4 & DRIVERS 32 Out In DATA INPUT REGISTERS RCVRS L U LDM, UDM 9 COLUMN- ADDRESS COUNTER/ LATCH 8 COL mb_x8x16_at_ddr_t66a_d2.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
![BA[1:] 15 ADDRESS REGISTER 2 2 BANK CONTROL LOGIC I/O GATING DM MASK LOGIC 256 x32 COLUMN DECODER 32 32 COL MASK WRITE FIFO 4 & DRIVERS 32 Out In DATA INPUT REGISTERS 2 2 2 2 16 16 16](/docs-images/46/21509825/images/page_9.jpg "16 2 16 RCVRS L U LDM, UDM 9 COLUMN- ADDRESS COUNTER/ LATCH 8 COL 2 1 256mb_x8x16_at_ddr_t66a_d2.fm - Rev. A; Core DDR Rev. B 11/11 EN 9 211 Micron Technology, Inc.")
10 Pin and Ball Assignments and Descriptions 256Mb: x8, x16 Automotive DDR SDRAM Pin and Ball Assignments and Descriptions Figure 5: 66-Pin TSOP Pin Assignments Top View x8 x16 V DD V DD V D V D NC V SSQ V SSQ NC V D V D NC V SSQ V SSQ NC 7 NC NC V D V D NC L NC NC V DD V DD DNU DNU NC LDM WE# WE# CAS# CAS# RAS# RAS# CS# CS# NC NC BA BA BA1 BA1 A1/AP A1/AP A A A1 A1 A2 A2 A3 A3 V DD V DD x16 V SS 15 V SSQ V D V SSQ 1 9 V D 8 NC V SSQ U DNU V REF V SS UDM # E NC A12 A11 A9 A8 A7 A6 A5 A4 V SS x8 V SS 7 V SSQ NC 6 V D NC 5 V SSQ NC 4 V D NC NC V SSQ DNU V REF V SS DM # E NC A12 A11 A9 A8 A7 A6 A5 A4 V SS 256mb_x8x16_at_ddr_t66a_d2.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
11 Pin and Ball Assignments and Descriptions Figure 6: 6-Ball FBGA Ball Assignments Top View V SSQ NC NC NC NC V REF 7 V D V SSQ V D V SSQ V SS A12 A11 A8 A6 A4 V SS DM # E A9 A7 A5 V SS x8 Top View A B C D E F G H J K L M V DD NC NC WE# RAS# BA1 A A2 V DD V SSQ V D V SSQ V D V DD CAS# CS# BA A1 A1 A3 V D NC NC NC NC DNU V SSQ V REF 15 V D V SSQ V D V SSQ V SS A12 A11 A8 A6 A4 VSS U UDM # E A9 A7 A5 V SS x16 Top View A B C D E F G H J K L M V DD L LDM WE# RAS# BA1 A A2 VDD V SSQ V D V SSQ V D V DD CAS# CS# BA A1 A1 A3 V D DNU 256mb_x8x16_at_ddr_t66a_d2.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
12 Pin and Ball Assignments and Descriptions Table 4: Pin and Ball Descriptions FBGA Numbers K7, L8, L7, M8, M2, L3, L2, K3, K2, J3, K8, J2, H2 TSOP Numbers Symbol Type Description 29, 3, 31, 32, 35, 36, 37, 38, 39, 4, 28 41, 42 A, A1, A2, A3, A4, A5, A6, A7, A8, A9, A1, A11, A12 Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit A1 for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A1 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A1 LOW, bank selected by BA[1:] or all banks A1 HIGH. The address inputs also provide the op-code during a LOAD MODE REGISTER command. J8, J7 26, 27 BA, BA1 Input Bank address inputs: BA[1:] define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA[1:] also define which mode register mode register or extended mode register is loaded during the LOAD MODE REGISTER LMR command. G2, G3 45, 46, # Input Clock: and # are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of and the negative edge of #. Output data and is referenced to the crossings of and #. H3 44 E Input Clock enable: E HIGH activates and E LOW deactivates the internal clock, input buffers, and output drivers. Taking E LOW provides PRECHARGE POWER-WN and SELF REFRESH operations all banks idle or ACTIVE POWER-WN row ACTIVE in any bank. E is synchronous for POWER-WN entry and exit and for SELF REFRESH entry. E is asynchronous for SELF REFRESH exit and for disabling the outputs. E must be maintained HIGH throughout read and write accesses. Input buffers excluding, #, and E are disabled during POWER- WN. Input buffers excluding E are disabled during SELF REFRESH. E is an SSTL_2 input but will detect an LVCMOS LOW level after V DD is applied and until E is first brought HIGH, after which it becomes a SSTL_2 input only. H8 24 CS# Input Chip select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. F3 F7, F3 47 2, 47 DM LDM, UDM H7, G8, G7 23, 22, 21 RAS#, CAS#, WE# A8, B9, B7, C9, C7, D9, D7, E9, E1, D3, D1, C3, C1, B3, B1, A2 A8, B7, C7, D7, D3, C3, B3, A2 2, 4, 5, 7, 8, 1, 11, 13, 54, 56, 57, 59, 6, 62, 63, 65 2, 5, 8, 11, 56, 59, 62, 65 [2:] [5:3] [8:6] [11:9] [14:12] 15 [2:] [5:3] [7:6] Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of. Although DM pins are input-only, the DM loading is designed to match that of and pins. For the x16, LDM is DM for [7:] and UDM is DM for [15:8]. Pin 2 is a NC on x8. Input Command inputs: RAS#, CAS#, and WE# along with CS# define the command being entered. I/O Data input/output: Data bus for x16. I/O Data input/output: Data bus for x8. 256mb_x8x16_at_ddr_t66a_d2.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
13 Pin and Ball Assignments and Descriptions Table 4: Pin and Ball Descriptions continued FBGA Numbers E3 E7 E L U F8, M7, A7 1, 18, 33 V DD Supply Power supply. B2, D2, C8, E8, A9 3, 9, 15, 55, 61 I/O Data strobe: Output with read data, input with write data. is edge-aligned with read data, centered in write data. It is used to capture data. For the x16, L is for [7:] and U is for [15:8]. Pin 16 E7 is NC on x8. V D Supply power supply: Isolated on the die for improved noise immunity. A3, F2, M3 34, 48, 66 V SS Supply Ground. A1, C2, E2, 6, 12, 52, V SSQ Supply ground: Isolated on the die for improved noise immunity. B8, D8 58, 64 F1 49 V REF Supply SSTL_2 reference voltage. 14, 17, 25, 43, 53 NC No connect for x16: These pins should be left unconnected. B1, B9, C1, C9, D1, D9, E1, E7, E9, F7 TSOP Numbers Symbol Type Description 4, 7, 1, 13, 14, 16, 17, 2, 25, 43, 53, 54, 57, 6, 63 NC No connect for x8: These pins should be left unconnected. F9 19, 5 DNU Do not use: Must float to minimize noise on V REF. Table 5: Reserved NC Pin Descriptions NC pins not listed may also be reserved for other uses; this table defines NC pins of importance TSOP Numbers Symbol Type Description 17 A13 Input Address input A13 for 1Gb devices. 256mb_x8x16_at_ddr_t66a_d2.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
![For the x16, L is for [7:] and U is for [15:8]. Pin 16 E7 is NC on x8. V D Supply power supply: Isolated on the die for improved noise immunity. A3, F2, M3 34, 48, 66 V SS Supply Ground.](/docs-images/46/21509825/images/page_13.jpg "A1, C2, E2, 6, 12, 52, V SSQ Supply ground: Isolated on the die for improved noise immunity. B8, D8 58, 64 F1 49 V REF Supply SSTL_2 reference voltage.")
14 Package Dimensions Package Dimensions Figure 7: 66-Pin Plastic TSOP 4 mil ±.8 SEE DETAIL A.65 TYP X.32 ±.75 TYP ± ±.8 PIN #1 ID GAGE PLANE MAX TYP.5 ±.1 DETAIL A Notes: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is.25mm per side. 256mb_x8x16_at_ddr_t66a_d2.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
15 Package Dimensions Figure 8: 6-Ball FBGA 8mm x 12.5mm Seating plane.12 A A.8 ±.1 6X Ø.45 Solder ball material: eutectic or SAC35. Dimensions apply to solder balls postreflow on Ø Ball A1 ID NSMD ball pads. A B C D E F 11 CTR 12.5 ±.15 G H J 1 TYP K L M Ball A1 ID.8 TYP 6.4 CTR 8 ± MAX.25 MIN Notes: 1. All dimensions are in millimeters. 2. Topside part marking decoder can be found on Micron s Web site. 256mb_x8x16_at_ddr_t66a_d2.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
16 Electrical Specifications I DD Electrical Specifications I DD Table 6: I DD Specifications and Conditions x8, x16: -5B V D = 2.6V ±.1V, V DD = 2.6V ±.1V -5B; C T A +7 C; Notes: 1 5, 11, 13, 15, 47; Notes appear on pages 34 39; See also Table 7 on page 17 Parameter/Condition Symbol -5B -6/6T Units Notes Operating one-bank precharge current: t RC = t RC MIN; I DD ma 23, 48 t = t MIN;, DM, and inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Operating one-bank active-read-precharge current: Burst = 4; I DD ma 23, 48 t RC = t RC MIN; t = t MIN; I OUT = ma; Address and control inputs changing once per clock cycle Precharge power-down standby current: All banks idle; Power-down I DD2P 4 4 ma 24, 33 mode; t = t MIN; E = LOW Idle standby current: CS# = HIGH; All banks are idle; t = t MIN; I DD2F ma 51 E = HIGH; Address and other control inputs changing once per clock cycle; V IN =V REF for,, and DM Active power-down standby current: One bank active; Power-down I DD3P ma 24, 33 mode; t = t MIN; E = LOW Active standby current: CS# = HIGH; E = HIGH; One bank active; I DD3N 3 3 ma 23 t RC = t RAS MAX; t = t MIN;, DM, and inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating burst read current: Burst = 2; Continuous burst reads; I DD4R ma 23, 48 One bank active; Address and control inputs changing once per clock cycle; t = t MIN; I OUT =ma Operating burst write current: Burst = 2; Continuous burst writes; One I DD4W ma 23 bank active; Address and control inputs changing once per clock cycle; = t MIN;, DM, and inputs changing twice per clock cycle Auto refresh burst current: t REFC = t RFC MIN I DD ma 5 t REFC =7.8µs AIT I DD5A 6 6 ma 28, 5 t REFC =1.95µs AAT I DD5A 9 9 ma 28, 5 Self refresh current: E.2V Standard I DD6 4 4 ma 12 Not supported for AAT Low power L I DD6A 2 2 ma 12 Operating bank interleave read current: Four-bank interleaving READs burst = 4 with auto precharge; t RC = minimum t RC allowed; = t MIN; Address and control inputs change only during ACTIVE, READ, or WRITE commands I DD ma 23, mb_x8x16_at_ddr_t66a_d2.fm - Rev. A; Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
17 Electrical Specifications DC and AC 256Mb: x8, x16 Automotive DDR SDRAM Electrical Specifications DC and AC Stresses greater than those listed in Table 7 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 7: Absolute Maximum Ratings Parameter Min Max Units V DD supply voltage relative to V SS 1V 3.6V V V D supply voltage relative to V SS 1V 3.6V V V REF and inputs voltage relative to V SS 1V 3.6V V I/O pins voltage relative to V SS.5V V D +.5V V Storage temperature plastic C Short circuit output current 5 ma Table 8: DC Electrical Characteristics and Operating Conditions -5B Notes: 1 5 and 17 apply to the entire table; Notes appear on page 34; V D = 2.6V ±.1V, V DD = 2.6V ±.1V Parameter/Condition Symbol Min Max Units Notes Supply voltage V DD V 37, 42 I/O supply voltage V D V 37, 42, 45 I/O reference voltage V REF.49 V D.51 V D V 7, 45 I/O termination voltage system V TT V REF -.4 V REF +.4 V 8, 45 Input high logic 1 voltage V IHDC V REF +.15 V DD +.3 V 29 Input low logic voltage V ILDC.3 V REF -.15 V 29 Input leakage current: I I 2 2 µa Any input V V IN V DD, V REF pin V V IN 1.35V All other pins not under test = V Output leakage current: I OZ 5 5 µa are disabled; V V OUT V D Full-drive option output High current V OUT = I OH 16.8 ma 38, 4 levels x8, x16: V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OL 16.8 ma Reduced-drive option output levels Ambient operating temperatures High current V OUT = I OHR 9 ma 39, 4 V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OLR 9 ma Commercial T A 7 C Industrial AIT T A 4 85 C Automotive AAT T A 4 15 C DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
18 Electrical Specifications DC and AC Table 9: DC Electrical Characteristics and Operating Conditions -6, -6T, -75E, -75Z, -75 Notes: 1 5, 17 apply to the entire table; Notes appear on page 34; V D = 2.5V ±.2V, V DD = 2.5V ±.2V Parameter/Condition Symbol Min Max Units Notes Supply voltage V DD V 37, 42 I/O supply voltage V D V 37, 42, 45 I/O reference voltage V REF.49 V D.51 V D V 7, 45 I/O termination voltage system V TT V REF -.4 V REF +.4 V 8, 45 Input high logic 1 voltage V IHDC V REF +.15 V DD +.3 V 29 Input low logic voltage V ILDC.3 V REF -.15 V 29 Input leakage current: I I 2 2 µa Any input V V IN V DD, V REF pin V V IN 1.35V All other pins not under test = V Output leakage current: I OZ 5 5 µa are disabled; V V OUT V D Full-drive option output High current V OUT = I OH 16.8 ma 38, 4 levels x8, x16: V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OL 16.8 ma Reduced-drive option output levels Design Revision F and K only: Ambient operating temperatures High current V OUT = I OHR 9 ma 39, 4 V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OLR 9 ma Commercial T A 7 C Industrial AIT T A 4 85 C Automotive AAT T A 4 15 C Table 1: AC Input Operating Conditions Notes: 1 5, 17 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V V D = 2.6V ±.1V, V DD = 2.6V ±.1V for -5B Parameter/Condition Symbol Min Max Units Notes Input high logic 1 voltage V IHAC V REF +.31 V 15, 29, 41 Input low logic voltage V ILAC V REF -.31 V 15, 29, 41 I/O reference voltage V REFAC.49 V D.51 V D V 7 DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
19 Electrical Specifications DC and AC Figure 9: Input Voltage Waveform V D 2.3V MIN V OH,min 1.67V 1 for SSTL_2 termination System noise margin power/ground, crosstalk, signal integrity attenuation 1.56V V IHAC 1.4V V IHDC 1.3V 1.275V 1.25V 1.225V 1.2V V REF + AC noise V REF + DC error V REF - DC error V REF - AC noise 1.1V V ILDC.94V V INAC - provides margin between V OL,max and V ILAC Receiver V ILDC V OL,max.83V 2 for SSTL_2 termination Transmitter Notes: V SSQ 1. V OH,min with test load is 1.927V. 2. V OL,max with test load is.373v. 3. Numbers in diagram reflect nominal values utilizing circuit below for all devices other than -5B. VTT 25Ω 25Ω Reference point DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
20 Electrical Specifications DC and AC Table 11: Clock Input Operating Conditions Notes: 1 5, 16, 17, 31 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V V D = 2.6V ±.1V, V DD = 2.6V ±.1V for -5B Parameter/Condition Symbol Min Max Units Notes Clock input mid-point voltage: and # V MPDC V 7, 1 Clock input voltage level: and # V INDC.3 V D +.3 V 7 Clock input differential voltage: and # V IDDC.36 V D +.6 V 7, 9 Clock input differential voltage: and # V IDAC.7 V D +.6 V 9 Clock input crossing point voltage: and # V IXAC.5 V D V D +.2 V 1 Figure 1: SSTL_2 Clock Input 2.8V Maximum clock level 1 # 1.45V X 1.25V 1.5V X V MPDC 2 V IXAC 3 V 4 IDDC V 5 IDAC.3V Minimum clock level 1 Notes: 1. or # may not be more positive than V D +.3V or more negative than V SS -.3V. 2. This provides a minimum of 1.15V to a maximum of 1.35V and is always half of V D. 3. and # must cross in this region. 4. and # must meet at least V IDDCmin when static and is centered around V MPDC. 5. and # must have a minimum 7mV peak-to-peak swing. 6. For AC operation, all DC clock requirements must also be satisfied. 7. Numbers in diagram reflect nominal values for all devices other than -5B. DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
21 Electrical Specifications DC and AC Table 12: Capacitance x8 TSOP Note: 14 applies to the entire table; Notes appear on page 34 Parameter Symbol Min Max Units Notes Delta input/output capacitance: [7:] x8 DC IO.5 pf 25 Delta input capacitance: Command and address DC I1.5 pf 3 Delta input capacitance:, # DC I2.25 pf 3 Input/output capacitance:,, DM C IO pf Input capacitance: Command and address C I pf Input capacitance:, # C I pf Input capacitance: E C I pf Table 13: Capacitance x8 FBGA Note: 14 applies to the entire table; Notes appear on page 34 Parameter Symbol Min Max Units Notes Delta input/output capacitance:,, DM DC IO.5 pf 25 Delta input capacitance: Command and address DC I1.5 pf 3 Delta input capacitance:, # DC I2.25 pf 3 Input/output capacitance:,, DM C IO pf Input capacitance: Command and address C I pf Input capacitance:, # C I pf Input capacitance: E C I pf Table 14: Capacitance x16 TSOP Note: 14 applies to the entire table; Notes appear on page 34 Parameter Symbol Min Max Units Notes Delta input/output capacitance: [7:], L, LDM DC IOL.5 pf 25 Delta input/output capacitance: [15:8], U, UDM DC IOU.5 pf 25 Delta input capacitance: Command and address DC I1.5 pf 3 Delta input capacitance:, # DC I2.25 pf 3 Input/output capacitance:, L, U, LDM, UDM C IO pf Input capacitance: Command and address C I pf Input capacitance:, # C I pf Input capacitance: E C I pf Table 15: Capacitance x16 FBGA Note: 14 applies to the entire table; Notes appear on page 34 Parameter Symbol Min Max Units Notes Delta input/output capacitance: [7:], L, LDM DC IOL.5 pf 25 Delta input/output capacitance: [15:8], U, UDM DC IOU.5 pf 25 Delta input capacitance: Command and address DC I1.5 pf 3 Delta input capacitance:, # DC I2.25 pf 3 Input/output capacitance:, L, U, LDM, UDM C IO pf Input capacitance: Command and address C I pf Input capacitance:, # C I pf Input capacitance: E C I pf DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
22 Electrical Specifications DC and AC Table 16: Electrical Characteristics and Recommended AC Operating Conditions -5B Notes 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.6V ±.1V, V DD = 2.6V ±.1V AC Characteristics -5B Parameter Symbol Min Max Units Notes Access window of from /# t AC.7.7 ns high-level width t CH t 31 Clock cycle time CL = 3 t ns 52 CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 31 and DM input hold time relative to t DH.4 ns 27, 32 and DM input pulse width for each input t DIPW 1.75 ns 32 Access window of from /# t.6.6 ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.4 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.4 ns 27, 32 falling edge from rising hold time t DSH.2 t falling edge to rising setup time t DSS.2 t Half-clock period t HP t CH, t CL ns 35 Data-out High-Z window from /# t HZ.7 ns 19, 43 Address and control input hold time slew rate.5 V/ns t IH F.6 ns 15 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time slew rate.5 V/ns t IS F.6 ns 15 Data-out Low-Z window from /# t LZ.7 ns 19, 43 LOAD MODE REGISTER command cycle time t MRD 1 ns hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.5 ns ACTIVE-to-READ with auto precharge command t RAP 15 ns ACTIVE-to-PRECHARGE command t RAS 4 7, ns 36 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 55 ns 55 ACTIVE-to-READ or WRITE delay t RCD 15 ns REFRESH-to-REFRESH command interval Industrial t REFC AIT 7.3 µs 24 REFRESH-to-REFRESH command interval Automotive t REFC AAT µs 24 Average periodic refresh interval Industrial t REFI AIT 7.8 µs 24 Average periodic refresh interval Automotive t REFI AAT 1.95 µs 24 AUTO REFRESH command period t RFC 7 ns 5 PRECHARGE command period t RP 15 ns read preamble t RPRE t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 1 ns Terminating voltage delay to V DD t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 21, 22 write postamble t WPST.4.6 t 2 DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
23 Electrical Specifications DC and AC Table 16: Electrical Characteristics and Recommended AC Operating Conditions -5B continued Notes 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.6V ±.1V, V DD = 2.6V ±.1V AC Characteristics -5B Parameter Symbol Min Max Units Notes Write recovery time t WR 15 ns Internal WRITE-to-READ command delay t WTR 2 t Exit SELF REFRESH-to-non-READ command t XSNR 7 ns Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
24 Electrical Specifications DC and AC Table 17: Electrical Characteristics and Recommended AC Operating Conditions -6 Notes: 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -6 FBGA Parameter Symbol Min Max Units Notes Access window of from /# t AC.7.7 ns high-level width t CH t 31 Clock cycle time CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 31 and DM input hold time relative to t DH.45 ns 27, 32 and DM input pulse width for each input t DIPW 1.75 ns 32 Access window of from /# t.6.6 ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.4 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.45 ns 27, 32 falling edge from rising - hold time t DSH.2 t falling edge to rising - setup time t DSS.2 t Half-clock period t HP t CH, ns 35 t CL Data-out High-Z window from /# t HZ.7 ns 19, 43 Address and control input hold time fast slew rate t IH F.75 ns Address and control input hold time slow slew rate t IH S.8 ns 15 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.75 ns Address and control input setup time slow slew rate t IS S.8 ns 15 Data-out Low-Z window from /# t LZ.7 ns 19, 43 LOAD MODE REGISTER command cycle time t MRD 12 ns - hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.5 ns ACTIVE-to-READ with auto precharge command t RAP 15 ns ACTIVE-to-PRECHARGE command t RAS 42 7, ns 36, 54 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 6 ns 55 ACTIVE-to-READ or WRITE delay t RCD 15 ns REFRESH-to-REFRESH command interval Industrial t REFC AIT 7.3 µs 24 REFRESH-to-REFRESH command interval Automotive t REFC AAT µs 24 Average periodic refresh interval Industrial t REFI AIT 7.8 µs 24 Average periodic refresh interval Automotive t REFI AAT 1.95 µs 24 AUTO REFRESH command period t RFC 72 ns 5 PRECHARGE command period t RP 15 ns read preamble t RPRE t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 12 ns Terminating voltage delay to V SS t VTD ns write preamble t WPRE.25 t DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
25 Electrical Specifications DC and AC Table 17: Electrical Characteristics and Recommended AC Operating Conditions -6 continued Notes: 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -6 FBGA Parameter Symbol Min Max Units Notes write preamble setup time t WPRES ns 21, 22 write postamble t WPST.4.6 t 2 Write recovery time t WR 15 ns Internal WRITE-to-READ command delay t WTR 1 t Exit SELF REFRESH-to-non-READ command t XSNR 75 ns Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window t QH - t Q ns 26 DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
26 Electrical Specifications DC and AC Table 18: Electrical Characteristics and Recommended AC Operating Conditions -6T Notes: 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -6T TSOP Parameter Symbol Min Max Units Notes Access window of from /# t AC.7.7 ns high-level width t CH t 31 Clock cycle time CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 31 and DM input hold time relative to t DH.45 ns 27, 32 and DM input pulse width for each input t DIPW 1.75 ns 32 Access window of from /# t.6.6 ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.45 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.45 ns 27, 32 falling edge from rising - hold time t DSH.2 t falling edge to rising - setup time t DSS.2 t Half-clock period t HP t CH, ns 35 t CL Data-out High-Z window from /# t HZ.7 ns 19, 43 Address and control input hold time fast slew rate t IH F.75 ns Address and control input hold time slow slew rate t IH S.8 ns 15 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.75 ns Address and control input setup time slow slew rate t IS S.8 ns 15 Data-out Low-Z window from /# t LZ.7 ns 19, 43 LOAD MODE REGISTER command cycle time t MRD 12 ns - hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.55 ns ACTIVE-to-READ with auto precharge command t RAP 15 ns ACTIVE-to-PRECHARGE command t RAS 42 7, ns 36, 54 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 6 ns 55 ACTIVE-to-READ or WRITE delay t RCD 15 ns REFRESH-to-REFRESH command interval Industrial t REFC AIT 7.3 µs 24 REFRESH-to-REFRESH command interval Automotive t REFC AAT µs 24 Average periodic refresh interval Industrial t REFI AIT 7.8 µs 24 Average periodic refresh interval Automotive t REFI AAT 1.95 µs 24 PRECHARGE command period t RP 15 ns read preamble t RPRE t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 12 ns Terminating voltage delay to V SS t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 21, 22 DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
27 Electrical Specifications DC and AC Table 18: Electrical Characteristics and Recommended AC Operating Conditions -6T continued Notes: 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -6T TSOP Parameter Symbol Min Max Units Notes write postamble t WPST.4.6 t 2 Write recovery time t WR 15 ns Internal WRITE-to-READ command delay t WTR 1 t Exit SELF REFRESH-to-non-READ command t XSNR 75 ns Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window t QH - t Q ns 26 DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
28 Electrical Specifications DC and AC Table 19: Electrical Characteristics and Recommended AC Operating Conditions -75E Notes: 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -75E Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 31 Clock cycle time CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 31 and DM input hold time relative to t DH.5 ns 27, 32 and DM input pulse width for each input t DIPW 1.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.5 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.5 ns 27, 32 falling edge from rising - hold time t DSH.2 t falling edge to rising - setup time t DSS.2 t Half-clock period t HP t CH, ns 35 t CL Data-out High-Z window from /# t HZ.75 ns 19, 43 Address and control input hold time fast slew rate t IH F.9 ns Address and control input hold time slow slew rate t IH S 1 ns 15 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.9 ns Address and control input setup time slow slew rate t IS S 1 ns 15 Data-out Low-Z window from /# t LZ.75 ns 19, 43 LOAD MODE REGISTER command cycle time t MRD 15 ns - hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.75 ns ACTIVE-to-READ with auto precharge command t RAP 15 ns ACTIVE-to-PRECHARGE command t RAS 4 12, ns 36, 54 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 6 ns 55 ACTIVE-to-READ or WRITE delay t RCD 15 ns REFRESH-to-REFRESH command interval Industrial t REFC AIT 7.3 µs 24 REFRESH-to-REFRESH command interval Automotive t REFC AAT µs 24 Average periodic refresh interval Industrial t REFI AIT 7.8 µs 24 Average periodic refresh interval Automotive t REFI AAT 1.95 µs 24 AUTO REFRESH command period t RFC 75 ns 5 PRECHARGE command period t RP 15 ns read preamble t RPRE t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 15 ns Terminating voltage delay to V SS t VTD ns write preamble t WPRE.25 t DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
29 Electrical Specifications DC and AC Table 19: Electrical Characteristics and Recommended AC Operating Conditions -75E continued Notes: 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -75E Parameter Symbol Min Max Units Notes write preamble setup time t WPRES ns 21, 22 write postamble t WPST.4.6 t 2 Write recovery time t WR 15 ns Internal WRITE-to-READ command delay t WTR 1 t Exit SELF REFRESH-to-non-READ command t XSNR 75 ns Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window t QH - t Q ns 26 DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
30 Electrical Specifications DC and AC Table 2: Electrical Characteristics and Recommended AC Operating Conditions -75Z Notes: 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -75Z Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 31 Clock cycle time CL = 2.5 t ns 46 CL = 2 t ns 46 low-level width t CL t 31 and DM input hold time relative to t DH.5 ns 27, 32 and DM input pulse width for each input t DIPW 1.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.5 ns 26, 27 WRITE command-to-first latching transition t S t and DM input setup time relative to t DS.5 ns 27, 32 falling edge from rising hold time t DSH.2 t falling edge to rising setup time t DSS.2 t Half-clock period t HP t CH, t CL ns 35 Data-out High-Z window from /# t HZ.75 ns 19, 43 Address and control input hold time fast slew rate t IH F.9 ns Address and control input hold time slow slew rate t IH S 1 ns 15 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.9 ns Address and control input setup time slow slew rate t IS S 1 ns 15 Data-out Low-Z window from /# t LZ.75 ns 19, 43 LOAD MODE REGISTER command cycle time t MRD 15 ns hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.75 ns ACTIVE-to-READ with auto precharge command t RAP 2 ns ACTIVE-to-PRECHARGE command t RAS 4 12, ns 36 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 65 ns 55 ACTIVE-to-READ or WRITE delay t RCD 2 ns REFRESH-to-REFRESH command interval Industrial t REFC AIT 7.3 µs 24 REFRESH-to-REFRESH command interval Automotive t REFC AAT µs 24 Average periodic refresh interval Industrial t REFI AIT 7.8 µs 24 Average periodic refresh interval Automotive t REFI AAT 1.95 µs 24 AUTO REFRESH command period t RFC 75 ns 5 PRECHARGE command period t RP 2 ns read preamble t RPRE t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 15 ns Terminating voltage delay to V DD t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 21, 22 DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
31 Electrical Specifications DC and AC Table 2: Electrical Characteristics and Recommended AC Operating Conditions -75Z continued Notes: 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -75Z Parameter Symbol Min Max Units Notes write postamble t WPST.4.6 t 2 Write recovery time t WR 15 ns Internal WRITE-to-READ command delay t WTR 1 t Exit SELF REFRESH-to-non-READ command t XSNR 75 ns Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window t QH - t Q ns 26 DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
32 Electrical Specifications DC and AC Table 21: Electrical Characteristics and Recommended AC Operating Conditions -75 Notes: 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -75 Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 31 Clock cycle time CL = 2.5 t ns 46 CL = 2 t ns 46 low-level width t CL t 31 and DM input hold time relative to t DH.5 ns 27, 32 and DM input pulse width for each input t DIPW 1.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.5 ns 26, 27 WRITE command-to-first latching transition t S t and DM input setup time relative to t DS.5 ns 27, 32 falling edge from rising hold time t DSH.2 t falling edge to rising setup time t DSS.2 t Half-clock period t HP t CH, t CL ns 35 Data-out High-Z window from /# t HZ.75 ns 19, 43 Address and control input hold time fast slew rate t IH F.9 ns Address and control input hold time slow slew rate t IH S 1 ns 15 Address and control input pulse width for each input t IPW 2.2 ns Address and control input setup time fast slew rate t IS F.9 ns Address and control input setup time slow slew rate t IS S 1 ns 15 Data-out Low-Z window from /# t LZ.75 ns 19, 43 LOAD MODE REGISTER command cycle time t MRD 15 ns hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.75 ns ACTIVE-to-READ with auto precharge command t RAP 2 ns ACTIVE-to-PRECHARGE command t RAS 4 12, ns 36 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 65 ns 55 ACTIVE-to-READ or WRITE delay t RCD 2 ns REFRESH-to-REFRESH command interval Industrial t REFC AIT 7.3 µs 24 REFRESH-to-REFRESH command interval Automotive t REFC AAT µs 24 Average periodic refresh interval Industrial t REFI AIT 7.8 µs 24 Average periodic refresh interval Automotive t REFI AAT 1.95 µs 24 AUTO REFRESH command period tr FC 75 ns 5 PRECHARGE command period t RP 2 ns read preamble t RPRE t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 15 ns Terminating voltage delay to V DD t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 21, 22 DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
33 Electrical Specifications DC and AC Table 21: Electrical Characteristics and Recommended AC Operating Conditions -75 continued Notes: 1 6, 16 18, 34 apply to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -75 Parameter Symbol Min Max Units Notes write postamble twpst.4.6 t 2 Write recovery time twr 15 ns Internal WRITE-to-READ command delay t WTR 1 t Exit SELF REFRESH-to-non-READ command t XSNR 75 ns Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window t QH - t Q ns 26 Table 22: Input Slew Rate Derating Values for Addresses and Commands Note: 15 applies to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V Speed Slew Rate t IS t IH Units -75Z/-75E.5 V/ns 1. 1 ns -75Z/-75E.4 V/ns ns -75Z/-75E.3 V/ns ns Table 23: Input Slew Rate Derating Values for,, and DM Note: 32 applies to the entire table; Notes appear on page 34; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V Speed Slew Rate t DS t DH Units -75Z/-75E.5 V/ns.5.5 ns -75Z/-75E.4 V/ns ns -75Z/-75E.3 V/ns.6.6 ns DDR_x4x8x16_Core2.fm - Core DDR Rev. B 11/11 EN Micron Technology, Inc. All rights reserved.
Double Data Rate (DDR) SDRAM MT46V128M4 32 Meg x 4 x 4 banks MT46V64M8 16 Meg x 8 x 4 banks MT46V32M16 8 Meg x 16 x 4 banks
Double Data Rate DDR SDRAM MT46V28M4 32 Meg x 4 x 4 banks MT46V64M8 6 Meg x 8 x 4 banks MT46V32M6 8 Meg x 6 x 4 banks 52Mb: x4, x8, x6 DDR SDRAM Features Features V DD = 2.5V ±.2V, V D = 2.5V ±.2V V DD
DDR SDRAM MT46V256M4 64 Meg x 4 x 4 Banks MT46V128M8 32 Meg x 8 x 4 Banks MT46V64M16 16 Meg x 16 x 4 Banks
Features DDR SDRAM MT46V256M4 64 Meg x 4 x 4 Banks MT46V28M8 32 Meg x 8 x 4 Banks MT46V64M6 6 Meg x 6 x 4 Banks Features VDD = 2.5V ±.2V, VD = 2.5V ±.2V VDD = 2.6V ±.V, VD = 2.6V ±.V DDR4 Bidirectional
DOUBLE DATA RATE (DDR) SDRAM
DOUBLE DATA RATE (DDR) SDRAM 256Mb: x8, x6 DDR 4 SDRAM Addendum MT46V32M8 8 MEG X 8 X 4 BANKS MT46V6M6 4 MEG X 6 X 4 BANKS For the latest data sheet revisions, please refer to the Micron Website: www.micron.com/dramds
Note: Data Rate (MT/s) CL = 3 CL = 4 CL = 5 CL = 6. t RCD (ns) t RP (ns) t RC (ns) t RFC (ns)
TwinDie DDR2 SDRAM MT47H512M4 32 Meg x 4 x 8 Banks x 2 Ranks MT47H256M8 16 Meg x 8 x 8 Banks x 2 Ranks 2Gb: x4, x8 TwinDie DDR2 SDRAM Features Features Uses two 1Gb Micron die Two ranks (includes dual
DDR SDRAM UDIMM MT16VDDT6464A 512MB MT16VDDT12864A 1GB MT16VDDT25664A 2GB
DDR SDRAM UDIMM MT16VDDT6464A 512MB MT16VDDT12864A 1GB MT16VDDT25664A 2GB For component data sheets, refer to Micron s Web site: www.micron.com 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Features
DDR SDRAM SODIMM. MT8VDDT3264H 256MB 1 MT8VDDT6464H 512MB For component data sheets, refer to Micron s Web site: www.micron.com
SODIMM MT8VDDT3264H 256MB 1 MT8VDDT6464H 512MB For component data sheets, refer to Micron s Web site: www.micron.com 256MB, 512MB (x64, SR) 200-Pin SODIMM Features Features 200-pin, small-outline dual
DDR SDRAM SODIMM. MT9VDDT1672H 128MB 1 MT9VDDT3272H 256MB MT9VDDT6472H 512MB For component data sheets, refer to Micron s Web site: www.micron.
Features DDR SDRAM SODIMM MT9VDDT1672H 128MB 1 MT9VDDT3272H 256MB MT9VDDT6472H 512MB For component data sheets, refer to Micron s Web site: www.micron.com Features 200-pin, small-outline dual in-line memory
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Features DDR2 SDRAM SODIMM MT16HTF12864H 1GB MT16HTF25664H 2GB For component data sheets, refer to Micron s Web site: www.micron.com Features 200-pin, small outline dual in-line memory module (SODIMM)
Mobile SDRAM. MT48H16M16LF 4 Meg x 16 x 4 banks MT48H8M32LF 2 Meg x 32 x 4 banks
Features Mobile SDRAM MT48H6M6LF 4 Meg x 6 x 4 banks MT48H8M32LF 2 Meg x 32 x 4 banks Features Fully synchronous; all signals registered on positive edge of system clock V DD /V D =.7.95V Internal, pipelined
DDR SDRAM SODIMM MT16VDDF6464H 512MB MT16VDDF12864H 1GB
SODIMM MT16VDDF6464H 512MB MT16VDDF12864H 1GB 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Features For component data sheets, refer to Micron s Web site: www.micron.com Features 200-pin, small-outline dual
Table 1: Address Table
DDR SDRAM DIMM D32PB12C 512MB D32PB1GJ 1GB For the latest data sheet, please visit the Super Talent Electronics web site: www.supertalentmemory.com Features 184-pin, dual in-line memory module (DIMM) Fast
V58C2512(804/404/164)SB HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164)
V58C2512804/404/164SB HIGH PERFORMAE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 804 4 BANKS X 32Mbit X 4 404 4 BANKS X 8Mbit X 16 164 5 6 75 DDR400 DDR333 DDR266 Clock Cycle Time t CK2.5 6ns 6ns 7.5ns Clock
DDR2 SDRAM SODIMM MT8HTF6464HDZ 512MB MT8HTF12864HDZ 1GB. Features. 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM. Features
DDR SDRAM SODIMM MT8HTF6464HDZ 5MB MT8HTF864HDZ GB 5MB, GB (x64, DR) 00-Pin DDR SODIMM Features Features 00-pin, small-outline dual in-line memory module (SODIMM) Fast data transfer rates: PC-300, PC-400,
DDR2 SDRAM SODIMM MT8HTF12864HZ 1GB MT8HTF25664HZ 2GB. Features. 1GB, 2GB (x64, SR) 200-Pin DDR2 SDRAM SODIMM. Features
DDR2 SDRAM SODIMM MT8HTF12864HZ 1GB MT8HTF25664HZ 2GB 1GB, 2GB (x64, SR) 200-Pin DDR2 SDRAM SODIMM Features Features 200-pin, small-outline dual in-line memory module (SODIMM) Fast data transfer rates:
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DDR2 SDRAM SODIMM MT8HTF3264HD 256MB MT8HTF6464HD 512MB MT8HTF12864HD 1GB For component data sheets, refer to Micron s Web site: www.micron.
DDR2 SDRAM SODIMM MT8HTF3264HD 256MB MT8HTF6464HD 512MB MT8HTF12864HD 1GB For component data sheets, refer to Micron s Web site: www.micron.com 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SODIMM Features
DDR2 SDRAM SODIMM MT4HTF6464HZ 512MB. Features. 512MB (x64, SR) 200-Pin DDR2 SODIMM. Features. Figure 1: 200-Pin SODIMM (MO-224 R/C C)
DDR2 SDRAM SODIMM MT4HTF6464HZ 512MB 512MB (x64, SR) 200-Pin DDR2 SODIMM Features Features 200-pin, small-outline dual in-line memory module (SODIMM) Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300,
DDR2 SDRAM UDIMM MT18HTF6472AY 512MB MT18HTF12872AY 1GB MT18HTF25672AY 2GB MT18HTF51272AY 4GB. Features
DDR SDRAM UDIMM MT8HTF647AY 5MB MT8HTF87AY GB MT8HTF567AY GB MT8HTF57AY 4GB 5MB, GB, GB, 4GB (x7, DR) 40-Pin DDR SDRAM UDIMM Features Features 40-pin, unbuffered dual in-line memory module Fast data transfer
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DDR SDRAM SODIMM MT6HTF864HZ GB MT6HTF5664HZ GB MT6HTF564HZ 4GB GB, GB, 4GB (x64, DR) 00-Pin DDR SDRAM SODIMM Features Features 00-pin, small-outline dual in-line memory module (SODIMM) Fast data transfer
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Features DDR SDRAM Small-Outline DIMM MT16VDDF6464H 512MB MT16VDDF12864H 1GB For the latest component data sheet, refer to the Micron's Web site: www.micron.com/products/modules Features 200-pin, small-outline,
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DDR SDRAM RDIMM MT36VDDF12872 1GB MT36VDDF25672 2GB For component data sheets, refer to Micron s Web site: www.micron.com 1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM Features Features 184-pin, registered
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DDR3 SDRAM SODIMM MT8JSF12864HZ 1GB MT8JSF25664HZ 2GB. Features. 1GB, 2GB (x64, SR) 204-Pin Halogen-Free DDR3 SDRAM SO- DIMM.
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DDR3 SDRAM SODIMM MT16JSF25664HZ 2GB MT16JSF51264HZ 4GB. Features. 2GB, 4GB (x64, DR) 204-Pin Halogen-Free DDR3 SODIMM. Features
DDR3 SDRAM SODIMM MT6JSF5664HZ GB MT6JSF564HZ 4GB GB, 4GB (x64, DR) 04-Pin Halogen-Free DDR3 SODIMM Features Features DDR3 functionality and operations supported as defined in the component data sheet
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DDR3 SDRAM UDIMM MT16JTF25664AZ 2GB MT16JTF51264AZ 4GB MT16JTF1G64AZ 8GB. Features. 2GB, 4GB, 8GB (x64, DR) 240-Pin DDR3 UDIMM.
DDR3 SDRAM UDIMM MT6JTF5664AZ GB MT6JTF564AZ 4GB MT6JTFG64AZ 8GB GB, 4GB, 8GB (x64, DR) 40-Pin DDR3 UDIMM Features Features DDR3 functionality and operations supported as per component data sheet 40-pin,
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DDR2 SDRAM FBDIMM MT9HTF6472F 512MB MT9HTF12872F 1GB. Features. 512MB, 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM. Features
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Features DDR2 SDRAM SODIMM MT4HTF1664H 128MB MT4HTF3264H 256MB MT4HTF6464H 512MB For component specifications, refer to Micron s Web site: www.micron.com/products/ddr2sdram Features 200-pin, small outline,
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DDR3L SDRAM MT41K512M4 64 Meg x 4 x 8 banks MT41K256M8 32 Meg x 8 x 8 banks MT41K128M16 16 Meg x 16 x 8 banks 2Gb: x4, x8, x16 DDR3L SDRAM Description Description The 1.35V DDR3L SDRAM device is a low-voltage
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GENERAL DESCRIPTION The Gigaram is a 128M/256M bit x 72 DDDR2 SDRAM high density JEDEC standard ECC Registered memory module. The Gigaram consists of eighteen CMOS 128MX4 DDR2 for 1GB and thirty-six CMOS
-80E PC2-6400 800 800 533 400 12.5 12.5 55-667 PC2-5300 667 533 400 15 15 55-53E PC2-4200 533 400 15 15 55
SDRAM FBDIMM MT36HTF25672FZ 2GB MT36HTF51272FZ 4GB MT36HTF1G72FZ 8GB 2GB, 4GB, 8GB (x72, DR) 240-Pin SDRAM FBDIMM Features Features 240-pin, fully buffered dual in-line memory module (FBDIMM) Fast data
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DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks 2Gb: x4, x8, x16 DDR3 SDRAM Features Features V DD = V DDQ = 1.5V ±0.075V 1.5V center-terminated
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WE# RAS# A0 A1 A2 A3
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256MB, 52MB, GB (x72, SR, ECC) 24-Pin DDR2 SDRAM UDIMM Features DDR2 SDRAM Unbuffered DIMM MT9HTF3272A 256MB MT9HTF6472A 52MB MT9HTF2872A GB For the latest data sheet, please refer to the Micron Web site:
DDR3L SDRAM. MT41K1G4 128 Meg x 4 x 8 banks MT41K512M8 64 Meg x 8 x 8 banks MT41K256M16 32 Meg x 16 x 8 banks. Description
DDR3L SDRAM MT41K1G4 128 Meg x 4 x 8 banks MT41K512M8 64 Meg x 8 x 8 banks MT41K256M16 32 Meg x 16 x 8 banks 4Gb: x4, x8, x16 DDR3L SDRAM Description Description DDR3L SDRAM 1.35V is a low voltage version
Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 NC. NC NC WE# RAS# NC NC A0 A1 A2 A3 Vcc
TECHNOLOGY INC. MEG x 6 DRAM MT4CM6E5 MT4LCM6E5 FEATURES JEDEC- and industry-standard x6 timing functions pinouts and packages High-performance CMOS silicon-gate process Single power supply (+3.3 ±.3 or
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-80E PC2-6400 800 800 533 400 12.5 12.5 55-667 PC2-5300 667 533 400 15 15 55-53E PC2-4200 533 400 15 15 55
SDRAM FBDIMM MT18HTF12872FDZ 1GB MT18HTF25672FDZ 2GB 1GB, 2GB (x72, DR) 240-Pin SDRAM FBDIMM Features Features 240-pin, fully buffered dual in-line memory module (FBDIMM) Fast data transfer rates: PC2-4200,
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