Linear Scan Register Allocation on SSA Form

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7 Compilation Statistics SPECjvm2008 SPECjbb2005 DaCapo SciMark Baseline SSA Form Baseline SSA Form Baseline SSA Form Baseline SSA Form Compiled Methods 6,788 6, ,242 8, Compiled Bytecodes [KByte] 1,094 1, ,272 2, Avg. Method Size [Byte/Method] Compilation Time [msec.] 4,250 4,080-4% % 13,390 12,700-5% % Back End Time [msec.] 1,170 1,020-13% % 2,930 2,460-16% % Machine Code Size [KByte] 4,581 4,563-0% % 11,760 11,719-0% % Memory Allocation Lifetime Analysis [KByte] 65,248 58,877-10% 5,047 4,559-10% 171, ,794-24% % Allocation and Resolution [KByte] 48,171 48,169-0% 3,255 3,239-0% 89,144 88,879-0% % LIR Before Register Allocation Moves 203, ,640-11% 15,797 13,644-14% 402, ,936-12% % Phi Functions 0 10, , LIR After Register Allocation Moves Register to Register 55,592 53,856-3% 4,473 4,245-5% 127, ,351-2% % Moves Constant to Register 35,348 34,612-2% 3,129 3,028-3% 71,967 70,663-2% % Moves Stack to Register 4,537 4,550 +0% % 3,718 3,722 +0% % Moves Register to Stack 38,715 33,650-13% 2,636 2,187-17% 65,973 56,639-14% % Moves Constant to Stack , Moves Stack to Stack Figure 9. Comparison of compilation statistics. The same steps are performed for the control flow edge from B3 to B4. The location of interval i10 is s1 at the end of B2 and eax at the beginning of B4, so a move from s1 to eax is added. The phi function requires a resolving move from interval i12 to i14, i.e., from the location s2 to ecx. Because the operands of the two moves are not overlapping, they can be emitted in any order, and resolving the mapping is trivial in this case. Both the source and target operand of a move can be a stack slot. Because one interval is assigned only one stack slot even when it is split and spilled multiple times, moves between two different stack slots can only occur with our added handling for phi functions. Stack-to-stack moves are not supported by most architectures and must be emulated with either a load and a store to a register currently not in use, or a push and a pop of a memory location if no register is free. Our implementation for the Intel x86 architecture does not reserve a scratch register that is always available for such moves. However, the register allocator has exact knowledge if there is a register that is currently unused, and it is also possible to use a floating point register for an integer value because no computations need to be performed. Therefore, a register is available in nearly all cases. Still, a stack-to-stack moves requires two machine instructions, so we try to assign the same stack slot to the source and target of a phi function when the according intervals do not overlap. 7. Evaluation We modified the client compiler of Sun Microsystems Java HotSpot TM VM, using an early snapshot version of the upcoming JDK 7 available from the OpenJDK project [27]. All benchmarks are executed on a system with two Intel Xeon X GHz processors, 4 cores, and 32 GByte main memory, running Ubuntu Linux with kernel version The results are obtained using 32-bit VMs. We compare our modified linear scan algorithm that operates on SSA form with the unmodified baseline version of the JDK. We evaluate using the following groups of benchmarks: (1) SPECjvm2008 [26] excluding the startup benchmarks (because each of these runs in a new VM but we want to accumulate compilation counters of one VM run) and the SciMark benchmarks (because we evaluate them separately), (2) SPECjbb2005 [25], (3) the DaCapo benchmarks [2] version MR2, and (4) Sci- Mark 2.0 [23]. SciMark is available both standalone and as part of SPECjvm2008. It consists of scientific kernels that require only few methods to be compiled. We use the standalone version because the framework infrastructure of SPECjvm2008 would significantly increase the number of compiled methods. 7.1 Impact on Compile Time Measuring the compile time is complicated because compilation is done in parallel with execution and thus subject to random noise. In particular, the Java HotSpot TM VM does not allow the recording and replaying of a certain set of compiled methods. Therefore, a slightly different set of methods is compiled when repeatedly executing the same benchmark. To reduce this noise, we limit the benchmarks to one benchmark thread if possible, disable compilation in a separate thread, and report the average of 20 executions. The standard deviation of the number of compiled methods and the size of compiled bytecodes is less than 0.8% (relative to the reported mean) for all benchmarks. Nevertheless, Figure 9 shows slightly different numbers when comparing the baseline and our modified version of the client compiler. The first group of rows in Figure 9 shows the basic compilation statistics. SPECjvm2008 and DaCapo are large benchmark suites 176

10 [3] B. Boissinot, A. Darte, F. Rastello, B. D. de Dinechin, and C. Guillon. Revisiting out-of-ssa translation for correctness, code quality and efficiency. In Proceedings of the International Symposium on Code Generation and Optimization, pages IEEE Computer Society, [4] B. Boissinot, S. Hack, D. Grund, B. Dupont de Dinechin, and F. Rastello. Fast liveness checking for SSA-form programs. In Proceedings of the International Symposium on Code Generation and Optimization, pages ACM Press, [5] P. Briggs, K. D. Cooper, and L. Torczon. Improvements to graph coloring register allocation. ACM Transactions on Programming Languages and Systems, 16(3): , [6] P. Brisk, F. Dabiri, R. Jafari, and M. Sarrafzadeh. Optimal register sharing for high-level synthesis of SSA form programs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(5): , [7] Z. Budimlic, K. D. Cooper, T. J. Harvey, K. Kennedy, T. S. Oberg, and S. W. Reeves. Fast copy coalescing and live-range identification. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages ACM Press, [8] G. J. Chaitin, M. A. Auslander, A. K. Chandra, J. Cocke, M. E. Hopkins, and P. W. Markstein. Register allocation via coloring. Computer Languages, 6:47 57, [9] R. Cytron, J. Ferrante, B. K. Rosen, M. N. Wegman, and F. K. Zadeck. Efficiently computing static single assignment form and the control dependence graph. ACM Transactions on Programming Languages and Systems, 13(4): , [10] S. J. Fink and F. Qian. Design, implementation and evaluation of adaptive recompilation with on-stack replacement. In Proceedings of the International Symposium on Code Generation and Optimization, pages IEEE Computer Society, [11] R. Griesemer and S. Mitrovic. A compiler for the Java HotSpot TM virtual machine. In The School of Niklaus Wirth: The Art of Simplicity, pages dpunkt.verlag, [12] S. Hack and G. Goos. Optimal register allocation for SSA-form programs in polynomial time. Information Processing Letters, 98(4): , [13] S. Hack and G. Goos. Copy coalescing by graph recoloring. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages ACM Press, [14] S. Hack, D. Grund, and G. Goos. Register allocation for programs in SSA-form. In Proceedings of the International Conference on Compiler Construction, pages LNCS 3923, Springer Verlag, [15] U. Hölzle and D. Ungar. Optimizing dynamically-dispatched calls with run-time type feedback. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages ACM Press, [16] T. Kotzmann, C. Wimmer, H. Mössenböck, T. Rodriguez, K. Russell, and D. Cox. Design of the Java HotSpot TM client compiler for Java 6. ACM Transactions on Architecture and Code Optimization, 5(1):Article 7, [17] C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In Proceedings of the International Symposium on Code Generation and Optimization, pages IEEE Computer Society, [18] T. Lindholm and F. Yellin. The Java TM Virtual Machine Specification. Addison-Wesley, 2nd edition, [19] H. Mössenböck and M. Pfeiffer. Linear scan register allocation in the context of SSA form and register constraints. In Proceedings of the International Conference on Compiler Construction, pages LNCS 2304, Springer-Verlag, [20] F. M. Q. Pereira and J. Palsberg. Register allocation by puzzle solving. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages ACM Press, [21] F. M. Q. Pereira and J. Palsberg. SSA elimination after register allocation. In Proceedings of the International Conference on Compiler Construction, pages LNCS 5501, Springer Verlag, [22] M. Poletto and V. Sarkar. Linear scan register allocation. ACM Transactions on Programming Languages and Systems, 21(5): , [23] R. Pozo and B. Miller. SciMark 2.0, scimark2/. [24] V. Sarkar and R. Barik. Extended linear scan: An alternate foundation for global register allocation. In Proceedings of the International Conference on Compiler Construction, pages LNCS 4420, Springer Verlag, [25] Standard Performance Evaluation Corporation. SPECjbb2005, [26] Standard Performance Evaluation Corporation. SPECjvm2008, [27] Sun Microsystems, Inc. OpenJDK, [28] O. Traub, G. Holloway, and M. D. Smith. Quality and speed in linear-scan register allocation. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages ACM Press, [29] C. Wimmer. Linear scan register allocation for the Java HotSpot TM client compiler. Master s thesis, Johannes Kepler University Linz, [30] C. Wimmer and H. Mössenböck. Optimized interval splitting in a linear scan register allocator. In Proceedings of the ACM/USENIX International Conference on Virtual Execution Environments, pages ACM Press,

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