Vivado Design Suite User Guide

Transcription

1 Vivado Design Suite User Guide Designing with IP

2 Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: Copyright 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 07/25/ Initial Xilinx release. 12/18/ Updated text and graphics to match changes in the Vivado IDE GUI. Vivado: Designing with IP 2

3 Table of Contents Revision History Chapter 1: IP Centric Design Flow Overview Vivado IP Catalog Vivado IP Packager Chapter 2: Adding IP Sources Accessing IP Adding Pre Generated IP Creating an IP Instance from the IP Catalog Customizing IP for the Design Generating IP Output Products Re Customizing an IP Instance Resetting IP Instance Output Products Instantiating IP Synthesizing IP Simulating IP Simulating IP within the RTL Design Simulating with Other Simulators Constraining IP within a Design Using an IP Example Design Using Fee Based Licensed IP Upgrading IP to the Latest Version Tcl Commands for Common IP Operations Chapter 3: Using the IP Packager IP Packaging and Usage Flow IP Packaging Flow IP User Flow Repository Management IP Catalog IP Customization and Generation IP Packaging Verification IP Packager Inputs Input File Groups Minimum File Set Required for Packaged IP IP Packager Outputs Vivado: Designing with IP 3

4 Organization of IP Design Files in the Output Package Other Files Written to the Output Package IP Packaging Using the Command Line Interface IP Packaging Steps Package an Existing Vivado Project or Create a New Project Packaging the Project as IP Adding New IP to the IP Catalog Adding Non HDL Files to the IP Package Appendix A: Additional Resources Vivado: Designing with IP 4

5 Chapter 1 IP Centric Design Flow Overview The Vivado Integrated Design Environment (IDE) provides an IP-centric design flow that allows you add IP modules to your design from a variety of design sources. X-Ref Target - Figure 1-1 Figure 1 1: IP Centric Design Flow As shown in Figure 1-1, the environment contains a central repository called the IP catalog that consolidates IP sources from: Vivado Design Suite cores Xilinx CORE Generator cores Modules from System Generator for DSP designs (MATLAB/Simulink algorithms) and Vivado High-Level Synthesis designs (C/C++ algorithms) Third party IP In some cases, third-party providers offer IP as synthesized NGC or EDIF netlists. You can load these files into a Vivado IDE design using the Add Sources command. Vivado IP Catalog As previously mentioned, the Vivado IP catalog provides a central repository for Xilinx, third party and intra-company IP that can be shared across a design team, division or company in a manner that facilitates design reuse. The key features of the Vivado IP catalog include: Consistent, easy access to all Xilinx IP, including building blocks, wizards, connectivity, DSP, embedded, AXI infrastructure and video IP from a single common repository that can be accessed consistently regardless of the end application being developed. Vivado: Designing with IP 5

6 Support for multiple physical locations, including shared networked drives, allowing users or organizations to leverage a consistent IP deployment environment for third party or internally developed IP. Instant access to IP customization and generation using the Vivado Integrated Design Environment (IDE) or automated script-based flows using Tcl On-demand delivery of optional IP output products such as instantiation templates, simulation models (HDL, C or MATLAB) and HDL example designs Integrated IP example designs that provide capability to evaluate IP directly as an instantiated source in a Vivado project Global RTL synthesis of IP with design with capability to use synthesizable RTL or behavioral simulation models of IP for simulation Capability to create an HDL netlist by treating customized IP as top and then use post-synthesis back-annotated structural simulation models by using write_verilog or write_vhdl Vivado IP Packager Also shown in Figure 1-1, is a unique design reuse feature is included called IP packager. IP packager is based on the IP-XACT standard. Once your Vivado IDE user design is assembled, IP packager allows you to quickly turn your design into a reusable IP module that can be added to the Vivado IP catalog and used by others in their design. Vivado: Designing with IP 6

7 Chapter 2 Adding IP Sources In RTL-based projects, you can add existing IP from outside the environment or browse the IP catalog to generate and add IP core instances to your project. The common tasks involved in adding IP sources are as follows: Accessing IP Customizing IP for the Design Generating IP Output Products Re-Customizing an IP Instance Resetting IP Instance Output Products Instantiating IP Synthesizing IP Simulating IP Constraining IP within a Design Using an IP Example Design Using Fee-Based Licensed IP Upgrading IP to the Latest Version Tcl Commands for Common IP Operations Each task is described in the sections that follow. Vivado: Designing with IP 7

8 Accessing IP Accessing IP Adding Pre Generated IP You can add pre-generated CORE Generator IP (<core_name>.xco instance files) or pre-generated Vivado IP (<core_name>.xci instance files) by using the Add Existing IP option in the Add Sources dialog box as shown in Figure 2-1. You can choose whether to point to the pre-generated IP or to copy the generated source files into your project. X-Ref Target - Figure 2-1 Figure 2 1: Adding Pre Generated IP Sources X-Ref Target - Figure 2-2 Figure 2 2: Adding Existing IP Adding existing IP can also be performed using the import_ip Tcl command as shown in the following examples: import_ip -file C:/coregen_ip/aurora_8b10b_v7_1.xco -name aurora_8b10b_v7_1 import_ip -file C:/coregen_ip/blk_mem_gen_v6_1.xco -name blk_mem_gen_v6_1 Vivado: Designing with IP 8

9 Accessing IP The added IP cores display separately in the IP Sources view of the Sources window, as well as with other source files in the Hierarchy, Libraries, and Compile Order views. You can select these cores in the Sources window to see the files that make up the core, and to view the properties in the Source File Properties window. Note: You can also add EDIF, Verilog, or SystemVerilog netlists or NGC files for IP cores into either RTL or netlist-based projects. For more information, see the topic Creating a Post-Synthesis Project in Chapter 2 of the Vivado Design Suite User Guide: System-Level Design Entry. Creating an IP Instance from the IP Catalog To create an IP instance, open the IP catalog, select Window > IP Catalog, or IP Catalog under the Project Manager menu in Flow Navigator. The IP cores display by category in an expandable tree table that provides the IP version, Advanced extensible Interface (AXI) protocol compliance, status of the IP, and license requirements. When you select a specific IP core, a description displays in the lower pane of the view. You can select an IP core from the catalog and view a variety of information regarding that IP. To bring up the documentation for a selected IP, you can: Access the documentation by clicking on the PDF symbol in the IP customization interface Click the View Information button on the IP catalog toolbar and select the DataSheet command from that popup menu. Vivado: Designing with IP 9

10 Accessing IP The figure below shows an example of the IP Catalog view. X-Ref Target - Figure 2-3 Figure 2 3: IP Catalog GUI Command options available in the IP catalog toolbar and/or popup menu include: Show Search: Displays a Search field to search the catalog for any text string. Collapse/Expand All: Collapses or Expands the IP catalog tree. Hide Superseded and Discontinued IPs: Filters the list to show current IP only. Hide incompatible IP: Filters the list to show only the IP that is compatible with the selected device family. Group by Category: Groups or flattens the list for better sorting and searching. Customize IP: Opens the customization GUI for the selected IP. License Status: Displays license requirements and status for the selected IP. Compatible Families: Displays a list of all device families that are compatible with the selected IP. View Data Sheet, Version Information, Webpage and Answer Records: Displays specified documentation for the selected IP. Vivado: Designing with IP 10

11 Customizing IP for the Design Update IP Catalog: Provides the capability to update the IP catalog with third party or user-developed IP. The update IP catalog provides the capability to add multiple directories. Automatically Scroll to Selected Objects: Toggles the display to jump to the selected object in the open view. Export to Spreadsheet: Lets you output the IP catalog to an XLS file for use in a spreadsheet. Customizing IP for the Design You can select a core from the IP catalog and customize the IP for use in your design by specifying values for the various parameters associated with the IP core. Note: A majority of the IP in the IP Catalog supports the integrated capabilities. However, some IP (for example, MIG, ChipScope tool 1.x, and wireless cores) do not yet support the Vivado Design Suite integrated capabilities. Instead, this IP uses the existing CORE Generator tool IP customization and generation interface. 1. Select the IP to customize from the IP catalog. 2. Double-click on the selected IP or select the Customize IP command from the toolbar or popup menu. The Figure below shows the customization interface for the Fifo Generator IP: X-Ref Target - Figure 2-4 Figure 2 4: Customize IP Dialog Box The customization interface fields present the parameters of the IP that allow you to customize the IP for use in your design. The IP interface varies, depending on the type of IP Vivado: Designing with IP 11

12 Customizing IP for the Design core you select, and can include one or more tabs of parameters to enter. You can toggle through these different views by selecting the appropriate tab on the top of the customization interface. The customization interface also includes the IP symbol and optionally can include information such as Frequency Response graph, Resource Estimates, AXI4-Stream port structure, etc. depending on the selected IP. The IP symbol supports zooming, resizing, and autofit options consistent with the schematic viewer canvas in Vivado IDE. If you click on the Adobe Acrobat symbol in the upper-right corner of the dialog box, supporting IP core documentation should come up in your Web Browser. You can also right-click on an IP in the IP catalog and select Data Sheet. After you finish entering the various parameters in the customization interface, you click OK; the IP core along with an instantiation template is then placed into the project as a design source. You can then right-click on the customized IP core and select Generate to create the targets for the IP core. The core is not synthesized at this time. After IP cores are added to your project and you run synthesis, the Vivado IDE automatically synthesizes the IP with the sources in the entire design. This lets you quickly instantiate multiple IP cores in your design without having to synthesize each one as it is added to the project. IP cores are displayed in the IP Sources view when they have been added to your project after customization. You can select these cores in the IP Sources view to see the various files that make up the core, and to view the properties in the Source File Properties view. Customizing an IP can also be accomplished via a create_ip Tcl command. For example: create_ip -name fifo_generator -version 9.2 -vendor xilinx.com -library ip -module_name fifo_gen Note: Executing the create_ip Tcl command creates the source files, but does not create an instantiation template. To modify an IP core in the Sources view, use Re-customize IP to reopen the customization interface and change any of the parameters associated with the core for this project. You can also select the IP cores in the Sources view, and use Upgrade IP to update the customized IP core to the latest version from the Xilinx IP catalog, and reapply any customizations from the current IP core. For information on IP supporting the Vivado Design Suite, refer to vado For information on specific IP, refer to or the IP catalog. Refer to for information on AXI IP. Vivado: Designing with IP 12

13 Generating IP Output Products Generating IP Output Products A Vivado IP instance allows you to generate various output products (instantiation template, synthesis, simulation, example designs, etc.) on demand. Some products are generated by default. You can change the default products that are generated with the IP Settings option in the IP catalog window. You can also generate additional selected products for a selected IP instance by using the Generate Output Products option in the right-click menu as shown below. X-Ref Target - Figure 2-5 Figure 2 5: Managing IP Output Products Re Customizing an IP Instance After you have generated the output products for an IP instance, you can re-customize the IP instance in place as follows: 1. In the IP Sources view of the Sources window, right-click on the IP and select Re-customize IP from the popup menu. Note: Alternatively, you can double-click the IP. 2. In the Re-Customize IP dialog box, change any of the parameters associated with the instance for this project, and click OK. Vivado: Designing with IP 13

14 Resetting IP Instance Output Products Resetting IP Instance Output Products You can reset the output products of an IP instance at any time to eliminate the chosen generated files. To delete the current output product data for an IP instance, select the instance in the IP sources tab of the Sources view and select Reset Output Products from the popup menu. The Reset Output Products command lets you select one output product to reset, or reset all output products for the instance. This eliminates the current output product data and requires that you generate the output products again. An equivalent Tcl command is: reset_ip [get_ips fifo_gen] Instantiating IP After you customize the IP and add it to your project, the IP instance displays in the Sources view under IP Sources. Expanding the IP instance in the Sources view displays the instantiation_template folder and the VHO/VEO file containing the instantiation template that you can copy and paste into your RTL design. Figure 2-6 shows the instantiation template of the FIFO Generator core. X-Ref Target - Figure 2-6 Figure 2 6: Sources View Instantiation IP RTL Code 1. To use the instantiation template in your design, you open either the VEO or VHO template file for the IP core and the RTL design file in the Text Editor by double-clicking on each source file in the Sources view, or by selecting the files and using the Open Files option. Vivado: Designing with IP 14

15 Synthesizing IP 2. Select the Instantiation Template in the VEO or VHO template file and copy it to the open RTL design at the appropriate location. 3. Edit the RTL to integrate the IP template into your design as needed. 4. With the IP core properly instantiated into your design, you are ready to synthesize the IP core along with the rest of your design. Synthesizing IP You can synthesize IP cores in a project along with the overall design by running synthesis. You can also synthesize a specific IP instance at any time by selecting the IP in the Hierarchy view, and selecting the Set as Top option from the right-click popup menu and then selecting Run Synthesis. X-Ref Target - Figure 2-7 Figure 2 7: Setting an IP Instance as the Design Top Simulating IP Simulating IP within the RTL Design You click Run Simulation in the Flow Navigator to simulate the IP cores with the overall design. The Vivado IDE uses the simulation sources delivered by the IP to perform a functional simulation of the entire design. IPs deliver either a behavioral model, plain text synthesizable source or encrypted synthesizable source as VHDL or Verilog simulation models. For IP delivering encrypted files as simulation sources, the Vivado IDE manages the compilation of the simulation sources for the selected target simulator (Vivado simulator or Vivado: Designing with IP 15

16 Constraining IP within a Design QuestaSim/ModelSim). The Vivado IDE also sets up the project for mixed-mode simulation when IP simulation sources are not available in the project target language. Simulating with Other Simulators To simulate with other simulators, you are required to create a structural simulation model for the IP specifying encrypted simulation sources. You might also need to create a structural simulation model to enable a single-language simulation of your design. To create a structural simulation model, do the following: Select the IP in the Hierarchy view Right-click, select Set as Top, and then run synthesis After synthesis is finished, you can generate the IP simulation model by using Tcl commands: write_verilog mode funcsim <corename>.v (for Verilog) write_vhdl mode funcsim <corename>.vhd (for VHDL) Constraining IP within a Design The Vivado IDE manages user-defined XDC timing and physical constraints for the entire design including IP. The Vivado IDE handles the association and the uniquification of constraints for design elements in IP instantiated multiple times within a project. Some IP in the IP catalog also deliver IP-specific XDC constraints based on user customization. During design synthesis and implementation, the Vivado IDE reads in the IP delivered XDC constraints after processing user defined XDC constraints. For information on XDC constraints, including specifics about XDC constraints for IP, see the Timing Constraints chapter of the Vivado Design Suite User Guide. Using an IP Example Design The example design is an optional output product that is generated on demand for IP cores that support the feature. The example design can be generated upon user request and opened in a new window of the Vivado IDE when Open IP Example Design is selected. This allows users to view and modify examples of various IP cores being used without touching their own design. As shown in Figure 2-8, to generate the example design, right click on the Vivado: Designing with IP 16

17 Using an IP Example Design IP under IP Sources, select Generate from right-click pop-up menu, check the Examples target to generate, then click OK. X-Ref Target - Figure 2-8 Figure 2 8: Generating and Launching an IP Example Design To launch the example design, right click on the IP under IP Sources, select Open IP Example Design from the right-click pop-up menu. A dialog box opens asking where to place the example design. By default, the Vivado IDE uses the current project directory. RECOMMENDED: Choose a separate working directory to evaluate the IP example design. X-Ref Target - Figure 2-9 Figure 2 9: Select OK to open the IP example design. Opening an IP Example Design If the example target is not generated yet, it will be generated first, and a new session of the Vivado IDE will open showing the example design under the Design Sources window. Notice Vivado: Designing with IP 17

18 Using Fee Based Licensed IP that the IP is instantiated in the example design with an example XDC constraint file to enable further evaluation of the IP. X-Ref Target - Figure 2-10 Figure 2 10: IP Example Design Instance with Constraints File Using Fee Based Licensed IP The Vivado IP catalog displays either Included or Purchase under the License column in the IP catalog. The following definitions apply to IP offered by Xilinx: Included: The Xilinx End User License Agreement applies to Xilinx LogiCORE IP cores that are licensed within the Xilinx Vivado Design Suite software tools at no additional charge Purchase: The Core License Agreement applies to fee-based Xilinx LogiCORE IP cores, and the Core Evaluation License Agreement applies to the evaluation of fee-based Xilinx LogiCORE IP cores. For more information on how to obtain IP licenses, visit the Xilinx Licensing site at Vivado: Designing with IP 18

19 Using Fee Based Licensed IP For fee-based IP, the OK button on the Customize IP dialog box is disabled until an evaluation or a paid license is found as shown in the figures below. X-Ref Target - Figure 2-11 Figure 2 11: Fee Based IP OK Button Disabled while Checking for License X-Ref Target - Figure 2-12 Figure 2 12: Fee Based IP OK Button Enabled after License Found Vivado: Designing with IP 19

20 Upgrading IP to the Latest Version Upgrading IP to the Latest Version IP can be upgraded to the latest version by: Using the Upgrade IP option in the right-click menu for IP that supports this feature Manually re-customizing IP to match existing custom parameters for the remaining IP For IP that supports the Upgrade IP feature, the IP can be upgraded by right-clicking on the IP instance in the IP Sources window and selecting Upgrade IP as shown in the figure below. X-Ref Target - Figure 2-13 Figure 2 13: Upgrading IP Vivado: Designing with IP 20

21 Tcl Commands for Common IP Operations The upgrade steps can also be performed by using the Tcl command upgrade_ip as shown in the examples below: upgrade_ip -version 7.2 [get_ips blk_mem_gen_v6_1] (for upgrading to the latest version) Tcl Commands for Common IP Operations As a result of the tight integration within the Vivado IDE, the Vivado IP catalog can be seamlessly accessed from the Vivado IDE and Tcl design environment. To accommodate batch mode users, every IP catalog action such as IP creation, re-customization, output product generation, etc. performed in the GUI issues an equivalent Tcl command, so that anything that can be done in the GUI can also be automated by scripting. The Vivado IP catalog provides direct access to IP parameter customization from the integrated Vivado IDE Tcl Console to enable users to set individual IP parameters directly from the Tcl Console. For example: set_property -name CONFIG.Input_Type -value {Unsigned} -objects [get_ips c_accum_v11_0_0] generate_target {instantiation_template synthesis} [get_ips c_accum_v11_0_0] For more information on the supported IP Tcl commands type help -category IPFlow in the Tcl Console as shown in the figure below. X-Ref Target - Figure 2-14 Figure 2 14: Getting Help on IP Tcl Commands Vivado: Designing with IP 21

22 Chapter 3 Using the IP Packager IP Packaging and Usage Flow The Vivado IP packager enables Vivado IDE users and third-party IP developers to easily prepare an Intellectual Property (IP) design for use in the Vivado IP catalog. The IP user can then instantiate this third party IP into their design in the Vivado Design Suite. When IP developers use the Vivado Design Suite IP packaging flow, the IP user will have a consistent user experience whether using Xilinx IP, third-party IP, or customer developed IP within the Vivado Design Suite. Figure 3-1 shows the flow in the IP packaging and usage model. The IP developer uses the IP packager feature to package IP files and associated data into a ZIP file. The IP user receives this generated ZIP file, installs the IP into the Vivado Design Suite IP catalog. The IP user then customizes the IP through parameter selections and generates an instance of the IP. To verify the proper packaging of the IP before handing it off to the IP user, Xilinx recommends that the IP developer run each IP module completely through the IP user flow to validate that the IP is ready for use. X-Ref Target - Figure 3-1 Figure 3 1: IP Packaging and Usage Flow Vivado: Designing with IP 22

23 IP Packaging and Usage Flow IP Packaging Flow Step 1: IP Packaging The output of IP packager is primarily an IP-XACT component file that can include default GUI files incorporated into a ZIP file, along with report and regeneration files. The IP developer can either: Package a design from an already populated Vivado Design Suite project. Create a new Vivado Design Suite project file, and use the IP packager wizards to import the IP source files and associated data. To invoke IP packager, select Tools > IP Packager. Alternatively, you can drive IP packager in batch mode using the Vivado Design Suite Tcl command line interface. Step 2: Secure IP Delivery The IP developer is responsible for securely delivering IP to the IP end-user. IP User Flow Step 1: Updating the IP Catalog After receiving IP from a third-party IP developer or an inter-company IP developer, the IP user starts the Vivado Design Suite and adds IP to the Vivado Design Suite IP catalog. Step 2: Installing the IP License (Optional) Optionally, the user can acquire a FlexNet license from the third-party provider and install it. Step 3: Third Party IP Usage Using the Vivado Design Suite, the IP user can start designing with the third-party IP cores. Vivado: Designing with IP 23

24 IP Packaging and Usage Flow Repository Management The Vivado IP catalog contains built-in repository management features that enable the IP user to add IP from another party. To make the third-party IP visible, the IP must be placed in a location visible from the user s machine. The user must then launch the Vivado Design Suite and run the IP Settings functions from the IP catalog to register the new user repository location and include the new IP in the catalog. As shown in Figure 3-2, there are two different types of repositories: standard Xilinx repositories and configured user repositories. Standard Xilinx repositories are shipped as part of the Vivado Design Suite, are always enabled, and are unchangeable by the user. User repositories are locations visible from the user's machines that contain one or more IPs. Xilinx or third-party IP providers can deliver IP updates to the catalog through patches. X-Ref Target - Figure 3-2 Figure 3 2: Repository Types The Repository Manager enables you to add or remove user repositories and establish precedence between repositories. IP is distinguished through a unique ordered list of elements corresponding to the Vendor, Library, Name, and Version (VLNV). If multiple repositories are referenced and have the same IP that occur in multiple locations, the IP that appears in the repository with highest precedence is displayed. The Xilinx IP repositories are always enabled and always have lowest precedence. Any changes to the repository setup for a project are stored with the project so the repository changes are visible whenever the project is re-opened on any machine (assuming the repository paths are also available). Note: User repositories may be made available to newly created projects. See Tools >Options General/IP Category. Vivado: Designing with IP 24

25 IP Packaging and Usage Flow IP Catalog The Vivado Design Suite IP catalog is a unified repository that enables you to search, review detailed information, and view associated documentation for the IP. After you add the third-party or customer IP to the Vivado Design Suite IP catalog (Figure 3-3), you can access the IP through the Vivado Design Suite flows. X-Ref Target - Figure 3-3 Figure 3 3: Repositories and the IP Catalog IP Customization and Generation To parameterize and generate output products of the IP, IP users can open the Vivado Design Suite IP customization GUI from the IP catalog. After specifying valid parameter combinations in the IP GUI, the IP user can click Generate to produce the IP specified output products in the Vivado Design Suite project directory. Output products can include Vivado: Designing with IP 25

26 IP Packager Inputs customization options, netlists, HDL synthesis and simulation files, test benches, example designs, and more. IP Packaging Verification The following are recommended tests to run after successfully packaging the IP using IP packager: Add the IP to the Vivado Design Suite IP repository and ensure that the IP appears correctly in the Vivado Design Suite IP catalog GUI. Parameterize the IP using the customization dialog in the Vivado Design Suite IP catalog and generate output products of the IP. Instantiate the IP in a design and run the design through the Vivado Design Suite flows. Generate the example project (if an example was packaged with the IP) and verify that the example functions properly with the Vivado Design Suite. IP Packager Inputs Input File Groups IP packager supports various input file groups, including: HDL synthesis HDL simulation Documentation HDL test bench Example design Implementation files (including constraint and structural netlist files) Minimum File Set Required for Packaged IP IP can designate as many or as few file groups as is appropriate to the IP. There is no hard requirement for a minimum set of file groups; however, the IP packager IP File Groups page presents a typical set of file groups, including logic synthesis, simulation, and documentation. If any of these file groups are empty, the final Review and Package page will warn the IP developer that file content has not been provided. Vivado: Designing with IP 26

27 IP Packager Outputs IP Packager Outputs Organization of IP Design Files in the Output Package The design files in the output package are organized into sub-folders identical to the organization of the input directory. They are not reorganized physically to match the logical groupings specified in the IP File Groups page. Other Files Written to the Output Package In addition to the IP design files and the IP-XACT XML file, the GUI folder is included in the output package. It contains files that help Xilinx tools display customization and other presentation GUIs for IP. IP Packaging Using the Command Line Interface All GUI operations can be duplicated using a Tcl shell executable. This interface is typically used as a means to automate the regeneration of the metadata file in a batch setting, such as a build. Vivado: Designing with IP 27

28 IP Packaging Steps IP Packaging Steps The following procedures provide generalized procedures that describe how to use the IP Packager wizards to package IP. These procedures use an example IP design called my_complex_mult. The document named Vivado Design Suite Tutorial: Designing with IP contains explicit instructions along with design data in a lab exercise format, Package an Existing Vivado Project or Create a New Project You can invoke the IP packager on an existing Vivado project or create a new Vivado project for IP you wish to package. To create a new project, do the following: 1. In the Vivado IDE, click Create New Project. 2. Name the project my_complex_mult, verify the project location, and click Next (Figure 3-4). X-Ref Target - Figure In the Design Source page, verify that RTL Project is selected, and then click Next. 4. In the Add Sources page, do the following: a. Add the three RTL subdirectories named cmpy_v3_1, mult_gen_v11_2, and xbip_utils_v2_0. b. Rename the Library field for the three subdirectories as shown in Figure 3-5. c. Add the top-level VHDL file named my_complex_mult_rtl.vhd. d. Deselect Copy Sources into Project, which is normally used by IP developers to preserve an established directory structure. e. Select VHDL as the target language. f. Click Next. Figure 3 4: New Project Dialog Box, Project Name Page Vivado: Designing with IP 28

29 IP Packaging Steps X-Ref Target - Figure 3-5 Figure 3 5: 5. Click through the remaining wizard panes, and click Finish. Packaging the Project as IP To package a Vivado project as IP, do the following: 1. With the Vivado project open, select Tools > IP Packager. 2. In the Welcome to the IP Packager page, click Next. 3. In the Begin IP Creation Page, click Finish. Information about the project is automatically gathered and a basic IP package is created in a staging area. 4. In the IP Packager Summary page, click OK. New Project Dialog Box, Add Sources Page 5. Fill in the fields shown in Figure 3-6 and then click Next. Vivado: Designing with IP 29

30 IP Packaging Steps X-Ref Target - Figure 3-6 Figure 3 6: IP Identification 6. Click Review and Package as shown in Figure 3-7. X-Ref Target - Figure 3-7 Figure 3 7: Review and Package Vivado: Designing with IP 30

31 IP Packaging Steps Note: The IP packager lists possible missing information that should be included. You can ignore this for now because you will add the missing IP documentation as part of the procedure in the Adding Non-HDL Files to the IP Package section. 7. Click the Package IP button to create an IP package ZIP file that you can send to an IP user. 8. In the Package IP dialog box, do the following: a. Verify that the name of the ZIP file is IPwizards_ip_my_complex_mult_3.0.zip, as shown in Figure 3-8. b. Change the Output Directory to: C:\my_complex_mult. c. Click OK. X-Ref Target - Figure 3-8 Figure 3 8: 9. Check the C:\my_complex_mult folder to make sure that the new ZIP file was added. Adding New IP to the IP Catalog Package IP The following procedure explains how to add packaged IP to the IP catalog. 1. In the Project Manager area of the Flow Navigator (left side of the main window), click IP Catalog. 2. In the IP catalog window, right-click and select IP Settings (Figure 3-9). Vivado: Designing with IP 31

32 IP Packaging Steps X-Ref Target - Figure 3-9 Figure 3 9: IP Settings Command 3. In the IP Settings dialog box, click Add Directories, select C:/third_party_ip as the IP Repository search path, and click Apply (Figure 3-10). This search path leaf must contain the component.xml file or the packaged ZIP file for the IP. X-Ref Target - Figure 3-10 Figure 3 10: IP Repository Search Path 4. Select the user repository just added, click Add IP, select the my_complex mult ZIP file and click OK. 5. In the IP catalog window, type My Complex in the Search window to verify that your IP named My Complex Multiplier was added to the IP catalog. Also verify that the Vivado: Designing with IP 32

33 IP Packaging Steps metadata you entered is correctly displayed in the Details window, as shown in Figure X-Ref Target - Figure 3-11 Figure 3 11: IP Catalog Window Adding Non HDL Files to the IP Package The following procedure explains how to add non-hdl files to a package already created by IP packager. 1. In the IP Packager tab, select IP Files Groups in the left frame, right-click on the Data Sheet category in the right frame and select Add Files (Data Sheet), as shown in Figure Vivado: Designing with IP 33

34 IP Packaging Steps X-Ref Target - Figure 3-12 Figure 3 12: Add a Data Sheet File to the Package 2. Click on the Add Files button in the popup dialog box, navigate to the directory C:/my_complex_mult/doc and select All Files in the Files of type: entry line. You should now see two documentation files in the popup dialog window. 3. Select the file my_complex_mult_data_sheet.pdf and click OK. Click OK again in the Add IP Files (Data Sheet) dialog box. 4. Expand the Data Sheet (1 file) category, as shown in Figure 3-13, and see that the PDF file has been added to the package. Vivado: Designing with IP 34

35 IP Packaging Steps X-Ref Target - Figure 3-13 Figure 3 13: Verify that the Data Sheet was Added 5. Repeat steps 1-4 to add the file named my_complex_mult_release_notes.txt to the Readme category. 6. Click Review and Package and then click the Package IP button to re-package your IP with the new documentation files. Vivado: Designing with IP 35

36 Appendix A Additional Resources 1. Xilinx Design Tools: Release Notes Guide (UG631) 2. Xilinx Design Tools: Installation and Licensing Guide (UG798) 3. Vivado Design Suite User Guide: Using the Vivado IDE (UG893) 4. Vivado Tcl Command Reference Guide (UG835) Vivado: Designing with IP 36