REV /2006 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.

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1 200 pin Unbuffered DDR2 SO-DIMM Based on DDR2-533/667 32Mx16 SDRAM Features 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) 32Mx64 and 64Mx64 Unbuffered DDR2 SO-DIMM based on 32Mx16 DDR2 SDRAM devices. Performance: PC PC Speed Sort 37B 3C DIMM Latency 4 5 Unit f CK MHz t CK ns f DQ MHz Intended for 266MHz and 333MHz applications Inputs and outputs are SSTL-18 compatible V DD = V DDQ = 1.8V ± 0.1V SDRAMs have 4 internal banks for concurrent operation Module has one physical bank Differential clock inputs Data is read or written on both clock edges DRAM DLL aligns DQ and DQS transitions with clock transitions. Address and control signals are fully synchronous to positive clock edge Programmable Operation: - DIMM Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write Auto Refresh (CBR) and Self Refresh Modes Automatic and controlled precharge commands 13/10/1 Addressing (NT256T64UH4A1FN) 13/10/2 Addressing (NT512T64UH8A1FN) 7.8 µs Max. Average Periodic Refresh Interval Serial Presence Detect Gold contacts SDRAMs in 84-ball FBGA Package RoHS Compliance Description NT256T64UH4A1FN and NT512T64UH8A1FN are unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as one rank of 32x64 and two ranks of 64x64 high-speed memory array. Modules use four 32Mx16 (NT256T64UH4A1FN) or eight 32Mx16 (NT512T64UH8A1FN) 84-ball FBGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66 long space-saving footprint. The DIMM is intended for use in applications operating up to 266 MHz (333MHz) clock speeds and achieves high-speed data transfer rates of up to 533 MHz (667MHz). Prior to any access operation, the device latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.3 1

2 Ordering Information Part Number Speed Organization Power Leads Note NT256T64UH4A1FN 37B DDR2-533 PC MHz CL = 4) NT256T64UH4A1FN 3C DDR2-667 PC MHz CL = 5) NT512T64UH8A1FN 37B DDR2-533 PC MHz CL = 4) NT512T64UH8A1FN 3C DDR2-667 PC MHz CL = 5) 32Mx64 64Mx64 1.8V Gold Green REV 1.3 2

3 Pin Description CK0, Differential Clock Inputs DQ0-DQ63 Data input/output CKE0, CKE1 Clock Enable DQS0-DQS7 Bidirectional data strobes Row Address Strobe - Differential data strobes Column Address Strobe DM0-DM7 Input Data Masks Write Enable V DD Power (1.8V), Chip Selects V REF Ref. Voltage for SSTL_18 inputs A0-A12 Row Address Inputs V DDSPD Serial EEPROM positive power supply A0-A9 Column Address Inputs V SS Ground A10/AP Column Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output ODT0, ODT1 Active termination control lines SA0, SA1 Serial Presence Detect Address Inputs NC Pinout No Connect Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 V REF 2 V SS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ DQ46 3 V SS 4 DQ4 53 V SS 54 V SS 103 V DD 104 V DD 153 DQ DQ47 5 DQ0 6 DQ5 55 DQ18 56 DQ A10/AP 106 BA1 155 V SS 156 V SS 7 DQ1 8 V SS 57 DQ19 58 DQ BA DQ DQ52 9 V SS 10 DM0 59 V SS 60 V SS DQ DQ V SS 61 DQ24 62 DQ V DD 112 V DD 161 V SS 162 V SS 13 DQS0 14 DQ6 63 DQ25 64 DQ ODT0 163 NC 164 CK1 15 V SS 16 DQ7 65 V SS 66 V SS (A13) 165 V SS DQ2 18 V SS 67 DM V DD 118 V DD V SS 19 DQ3 20 DQ12 69 NC 70 DQS3 119 ODT1 120 NC 169 DQS6 170 DM6 21 V SS 22 DQ13 71 V SS 72 V SS 121 V SS 122 V SS 171 V SS 172 V SS 23 DQ8 24 V SS 73 DQ26 74 DQ DQ DQ DQ DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ DQ DQ DQ DQ55 27 V SS 28 V SS 77 V SS 78 V SS 127 V SS 128 V SS 177 V SS 178 V SS CK0 79 CKE0 80 CKE DM4 179 DQ DQ60 31 DQS V DD 82 V DD 131 DQS4 132 V SS 181 DQ DQ61 33 V SS 34 V SS 83 NC 84 (A15) 133 V SS 134 DQ V SS 184 V SS 35 DQ10 36 DQ14 85 (BA2) 86 (A14) 135 DQ DQ DM DQ11 38 DQ15 87 V DD 88 V DD 137 DQ V SS 187 V SS 188 DQS7 39 V SS 40 V SS 89 A12 90 A V SS 140 DQ DQ V SS 41 V SS 42 V SS 91 A9 92 A7 141 DQ DQ DQ DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ V SS 193 V SS 194 DQ63 45 DQ17 46 DQ21 95 V DD 96 V DD 145 V SS SDA 196 V SS 47 V SS 48 V SS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA NC 99 A3 100 A2 149 V SS 150 V SS 199 V DDSPD 200 SA1 Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.3 3

4 Input/Output Functional Description Symbol Type Polarity Function CK0 CKE0, CKE1,,, (SSTL) (SSTL) (SSTL) (SSTL) (SSTL) Positive Edge Negative Edge Active High Active Low Active Low The positive line of the differential pair of system clock inputs which drives the input to the on-dimm PLL. All the DDR2 SDRAM address and control inputs are sampled on the rising edge of their associated clocks. The negative line of the differential pair of system clock inputs which drives the input to the on-dimm PLL. Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock,,, define the operation to be executed by the SDRAM. V REF Supply Reference voltage for SSTL-18 inputs ODT0, ODT1 Input Active High On-Die Termination control signals BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. A0 - A9 A10/AP A11, A12 DQ0 DQ63 CB0 CB7 (SSTL) - (SSTL) Active High During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0- CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to precharge. Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. V DD, V SS Supply Power and ground for the DDR2 SDRAM input buffers and core logic DQS0 DQS7 DM0 DM7 (SSTL) Input Negative and Positive Edge Active High SA0 SA2 - SDA - SCL - Data strobe for input and output data The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. V DDSPD Supply Serial EEPROM positive power supply. REV 1.3 4

5 Functional Block Diagram (256MB 1 Rank, 32Mx16 DDR2 SDRAMs) DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D0 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 D1 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 BA0-BA1 A0-A12 CKE0 BA0-BA1 : SDRAMs D0-D3 A0-A12 : SDRAMs D0-D3 : SDRAMs D0-D3 : SDRAMs D0-D3 CKE : SDRAMs D0-D3 VDDSPD VDD/VDDQ VREF VSS VDDID SPD D0-D3 D0-D3 D0-D3 CK0 CK1 2 loads 2 loads CKE1 N.C. : SDRAMs D0-D3 SCL WP Serial PD A0 A1 A2 SDA SA0 SA1 SA2 Notes : 1. DQ wiring may differ from that described in this drawing. 2. DQ/DQS/DM/CKE/S relationships are maintained as shown. 3. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. REV 1.3 5

6 Functional Block Diagram (512MB 2 Ranks, 32Mx16 DDR2 SDRAMs) DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D0 D4 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D2 D6 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 D1 D5 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 D7 BA0-BA1 BA0-BA1 : SDRAMs D0-D3 A0-A12 CKE0 CKE1 A0-A12 : SDRAMs D0-D3 : SDRAMs D0-D3 : SDRAMs D0-D3 CKE : SDRAMs D0-D3 N.C. VDDSPD VDD/VDDQ VREF VSS VDDID SPD D0-D3 D0-D3 D0-D3 CK0 CK1 2 loads 2 loads : SDRAMs D0-D3 ODT0 ODT : SDRAMs D0-D3 ODT1 ODT : SDRAMs D4-D7 Notes : 1. DQ wiring may differ from that described in this drawing. 2. DQ/DQS/DM/CKE/S relationships are maintained as shown. 3. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. SCL WP Serial PD A0 A1 SA0 SA1 A2 SDA REV 1.3 6

7 Serial Presence Detect (256MB 1 Rank, 32Mx16 DDR2 SDRAMs) (Part 1 of 2) Byte Description SPD Entry Value DDR2-533 DDR2-667 Serial PD Data Entry (Hexadecimal) DDR Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type DDR2-SDRAM 08 3 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Ranks, Package, and Height 1 rank, Height=30mm 60 6 Data Width of Assembly X Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 DDR DDR2 SDRAM Device Cycle Time at CL=5 3.75ns 3ns 3D DDR2 SDRAM Device Access Time (t ac) from Clock at CL=5 ±0.5ns ±0.45ns DIMM Configuration Type Non-Parity Refresh Rate/Type 7.8s/self Primary DDR2 SDRAM Width X Error Checking DDR2 SDRAM Device Width N/A Reserved Undefined DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks DDR2 SDRAM Device Attributes: Latencies Supported 3,4, DIMM Mechanical Characteristics <3.80mm DDR2 SDRAM DIMM Type Information Regular SODIMM (67.6mm) 21 DDR2 SDRAM Module Attributes: Normal DIMM DDR2 SDRAM Device Attributes: General Support weak driver Minimum Clock Cycle at CL=4 3.75ns 3.75ns 3D 3D 24 Maximum Data Access Time from Clock at CL=4 ±0.5ns ±0.5ns Minimum Clock Cycle Time at CL=3 5ns Maximum Data Access Time from Clock at CL=3 ±0.6ns Minimum Row Precharge Time (t RP) 15ns 3C 28 Minimum Row Active to Row Active delay (t RRD) 10ns Minimum RAS to CAS delay (t RCD) 15ns 3C 30 Minimum RAS Pulse Width (t RAS) 45ns 2D 31 Module Bank Density per Rank 256MB Address and Command Setup Time Before Clock (t IS) 0.25ns 0.2ns Address and Command Hold Time After Clock (t IH) 0.375ns 0.275ns Data Input Setup Time Before Clock (t DS) 0.1ns 0.1ns Data Input Hold Time After Clock (tdh) 0.225ns 0.175ns Write Recovery Time (t WR) 15ns 3C 37 Internal Write to Read Command delay (t WTR) 7.5ns 7.5ns 1E 1E 38 Internal Read to Precharge delay (t RTP) 7.5ns 1E 39 Reserved Undefined Extension of Byte 41 t RC and Byte 42 t RFC The number below a decimal point of trc and trfc are 0, trfc is less than 256ns Note REV 1.3 7

8 Serial Presence Detect (256MB 1 Rank, 32Mx16 DDR2 SDRAMs) (Part 2 of 2) Byte Description SPD Entry Value DDR2-533 DDR2-667 Serial PD Data Entry (Hexadecimal) DDR Minimum Core Cycle Time (t RC) 60ns 3C 42 Min. Auto Refresh Command Cycle Time (t RFC) 105ns Maximum Clock Cycle Time (t CK) 8ns 80 DDR Max. DQS-DQ Skew Factor (tqhs) 0.3ns 0.24ns 1E Read Data Hold Skew Factor (tqhs) 0.4ns 0.34ns PLL Relock Time N/A Tcasemax 0 C 6 C Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) DRAM Case Temperature Rise from Ambient due to Activate- Precharge/Mode Bits (DT0/Mode Bits) DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 118 C/W C 26 C 57 6B 45 C 56 C 2D C 37 C C 37 C 1F C 43 C 24 2B 22 C 27 C 16 1B 37 C 42 C 4A C 36 C C 54 C SPD Reversion Checksum for Byte 0-62 Checksum Data EB F Manufacturer s JEDEC ID Code NANYA 7F7F7F0B Module Manufacturing Location Manufacturing code Module Part number Module Part Number in ASCII Reserved Undefined -- NOTE: 1. NT256T64UH4A1FN-37B 4E E2D NT256T64UH4A1FN-3C 4E E2D Note -- 1 REV 1.3 8

9 Serial Presence Detect (512MB 2 Ranks, 32Mx16 DDR2 SDRAMs) (Part 1 of 2) Byte Description SPD Entry Value DDR2-533 DDR2-667 Serial PD Data Entry (Hexadecimal) DDR Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type DDR2-SDRAM 08 3 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Rank, Package, and Height 2 rank, Height=30mm 61 6 Data Width of this Assembly X Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 DDR DDR2 SDRAM Device Cycle Time at CL=5 3.75ns 3ns 3D DDR2 SDRAM Device Access Time from Clock at CL=5 ±0.5ns ±0.45ns DIMM Configuration Type Non-Parity/ECC Refresh Rate/Type 7.8s/self Primary DDR2 SDRAM Width X Error Checking DDR2 SDRAM Device Width N/A Reserved Undefined DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks DDR2 SDRAM Device Attributes: Latencies Supported 3,4, DIMM Mechanical Characteristics <3.80mm DDR2 SDRAM DIMM Type Information SODIMM (67.6mm) DDR2 SDRAM Module Attributes Normal DIMM DDR2 SDRAM Device Attributes: General Support weak driver Minimum Clock Cycle at CL=4 3.75ns 3.75ns 3D 3D 24 Maximum Data Access Time from Clock at CL=4 ±0.5ns ±0.5ns Minimum Clock Cycle Time at CL=3 5ns Maximum Data Access Time from Clock at CL=3 ±0.6ns Minimum Row Precharge Time (t RP) 15ns 3C 28 Minimum Row Active to Row Active delay (t RRD) 10ns Minimum RAS to CAS delay (t RCD) 15ns 3C 30 Minimum RAS Pulse Width (t RAS) 45ns 2D 31 Module Bank Density per Rank 256MB Address and Command Setup Time Before Clock (t IS) 0.25ns 0.2ns Address and Command Hold Time After Clock (t IH) 0.375ns 0.275ns Data Input Setup Time Before Clock (t DS) 0.1ns 0.1ns Data Input Hold Time After Clock (t DH) 0.225ns 0.175ns Write Recovery Time (t WR) 15ns 3C 37 Internal Write to Read Command delay (t WTR) 7.5ns 7.5ns 1E 1E 38 Internal Read to Precharge delay (t RTP) 7.5ns 1E 39 Reserved Undefined Extension of Byte 41 t RC and Byte 42 t RFC The number below a decimal point of t RC and t RFC are 0, t RFC is less than 256ns 00 Note REV 1.3 9

10 Serial Presence Detect (512MB 2 Ranks, 32Mx16 DDR2 SDRAMs) (Part 2 of 2) Byte Description SPD Entry Value DDR2-533 DDR2-667 Serial PD Data Entry (Hexadecimal) DDR2-533 DDR2-667 Note 41 Minimum Core Cycle Time (t RC) 60ns 3C 42 Min. Auto Refresh Command Cycle Time (t RFC) 105ns Maximum Clock Cycle Time (t CK) 8ns Max. DQS-DQ Skew Factor (t DQS) 0.3ns 0.24ns 1E Read Data Hold Skew Factor (t QHS) 0.4ns 0.34ns PLL Relock Time N/A Tcasemax 0 C 6 C Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) DRAM Case Temperature Rise from Ambient due to Activate- Precharge/Mode Bits (DT0/Mode Bits) DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 118 C/W C 26 C 57 6B 45 C 56 C 2D C 37 C C 37 C 1F C 43 C 24 2B 22 C 27 C 16 1B 37 C 42 C 4A C 36 C C 54 C SPD Revision Checksum for Byte 0-62 Checksum Data EC F Manufacturer s JEDEC ID Code NANYA 7F7F7F0B Module Manufacturing Location Manufacturing code Module Part number Module Part Number in ASCII Reserved Undefined -- NOTE: 1. NT512T64UH8A1FN-37B 4E E2D NT512T64UH8A1FN-3C 4E E2D REV

11 Absolute Maximum Ratings Symbol Parameter Rating Units V IN, V OUT Voltage on I/O pins relative to Vss -0.5 to +2.3 V V DD Voltage on VDD pins relative to Vss -1.0 to +2.3 V V DDQ Voltage on VDDQ pins relative to Vss -0.5 to +2.3 V V DDL Voltage on VDDL pins relative to Vss -0.5 to +2.3 V T STG Storage Temperature (Plastic) -55 to +100 C Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating temperature Conditions Symbol Parameter Rating Units Note T CASE Operating Temperature (Ambient) 0 to 95 C 1 Note: 1. Case temperature is measured at top and center side of any DRAMs. 2. t CASE > 85 C t REFI = 3.9 s DC Electrical Characteristics and Operating Conditions Symbol Parameter Min Max Units Notes VDD Supply Voltage V 1 VDDL DLL Supply Voltage V 1 VDDQ Output Supply Voltage V 1 VSS, VSSQ Supply Voltage, I/O Supply Voltage 0 0 V VREF Input Reference Voltage 0.49VDDQ 0.51VDDQ V 1, 2 VTT Termination Voltage VREF VREF V 3 Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-topeak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. Input AC/DC logic level Symbol Parameter Min Max Units Notes VIH (AC) Input High (Logic1) Voltage VREF V 1 VIL (AC) Input Low (Logic0) Voltage - VREF V 1 VIH (DC) Input High (Logic1) Voltage VREF VDDQ V VIL (DC) Input Low (Logic0) Voltage -0.3 VREF V 1 On Die Termination (ODT) Current Symbol Parameter Min Max Units EMRS(1) State IODTO IODTT Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING ma/dq A6=0, A2= ma/dq A6=1, A2= ma/dq A6=0, A2= ma/dq A6=1, A2=0 REV

12 Operating, Standby, and Refresh Currents T CASE = 0 C ~ 85 C; V DDQ = V DD = 1.8V ± 0.1V (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) Symbol Parameter/Condition PC PC Unit Notes IDD0 Operating Current: one bank; active/precharge; t RC = t RC (MIN); t CK = t CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle ma IDD1 IDD2P IDD2N Operating Current: one bank; active/read/precharge; Burst = 4; t RC = t RC (MIN); CL= 4; t CK = t CK (MIN); I OUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE V IL (MAX); t CK = t CK (MIN) Idle Standby Current: CS V IH (MIN); all banks idle; CKE V IH (MIN); t CK = t CK (MIN); address and control inputs changing once per clock cycle ma ma ma IDD2Q Precharge quiet standby current ma IDD3PF IDD3PS IDD3N IDD4R IDD4W Active Power-Down Standby Current: one bank active; power-down mode; CKE V IL (MAX); t CK = t CK (MIN); MRS(12)=0 Active Power-Down Standby Current: one bank active; power-down mode; CKE V IL (MAX); t CK = t CK (MIN); MRS(12)=1 Active Standby Current: one bank; active/precharge; CS V IH (MIN); CKE V IH (MIN); t RC = t RAS (MAX); t CK = t CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 4; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; t CK = t CK (MIN); I OUT = 0mA Operating Current: one bank; Burst = 4; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; t CK = t CK (MIN) ma ma ma ma ma IDD5 Auto-Refresh Current: t RC = t RFC (MIN) ma IDD6 Self-Refresh Current: CKE 0.2V ma IDD7 Note: Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t RC = t RC (min); I OUT = 0mA. Module IDD was calculated from component IDD. It may differ from the actual measurement ma REV

13 Operating, Standby, and Refresh Currents T CASE = 0 C ~ 85 C; V DDQ = V DD = 1.8V ± 0.1V (512MB, 2 Ranks, 32Mx16 DDR2 SDRAMs) Symbol Parameter/Condition PC PC Unit Notes IDD0 Operating Current: one bank; active/precharge; t RC = t RC (MIN); t CK = t CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle ma IDD1 IDD2P IDD2N Operating Current: one bank; active/read/precharge; Burst = 4; t RC = t RC (MIN); CL= 4; t CK = t CK (MIN); I OUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE V IL (MAX); t CK = t CK (MIN) Idle Standby Current: CS V IH (MIN); all banks idle; CKE V IH (MIN); t CK = t CK (MIN); address and control inputs changing once per clock cycle ma ma ma IDD2Q Precharge quiet standby current ma IDD3PF IDD3PS IDD3N IDD4R IDD4W Active Power-Down Standby Current: one bank active; power-down mode; CKE V IL (MAX); t CK = t CK (MIN); MRS(12)=0 Active Power-Down Standby Current: one bank active; power-down mode; CKE V IL (MAX); t CK = t CK (MIN); MRS(12)=1 Active Standby Current: one bank; active/precharge; CS V IH (MIN); CKE V IH (MIN); t RC = t RAS (MAX); t CK = t CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 4; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; t CK = t CK (MIN); I OUT = 0mA Operating Current: one bank; Burst = 4; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; t CK = t CK (MIN) ma ma ma ma ma IDD5 Auto-Refresh Current: t RC = t RFC (MIN) ma IDD6 Self-Refresh Current: CKE 0.2V ma IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t RC = t RC (min); I OUT = 0mA ma Note: Module IDD was calculated from component IDD. It may differ from the actual measurement. REV

14 AC Timing Specifications for DDR2 SDRAM Devices Used on Module (T CASE = 0 C ~ 85 C; V DDQ = 1.8V ± 0.1V; V DD = 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2) Symbol Parameter -37B -3C Min. Max. Min. Max. Unit Notes t AC DQ output access time from CK/ ns t DQSCK DQS output access time from CK/ ns t CH CK high-level width t CK t CL CK low-level width t CK t HP Minimum half clk period for any given cycle; defined by clk high (t CH) or clk low (t CL) time t CH or t CL - t CH or t CL - t CK t CK Clock Cycle Time ns t DH DQ and DM input hold time ps t DS DQ and DM input setup time ps t IPW Input pulse width t CK t DIPW DQ and DM input pulse width (each input) t CK t HZ Data-out high-impedance time from CK/ - t AC max - t AC max ns t LZ(DQ) Data-out low-impedance time from CK/ 2t AC min t AC max 2t AC min t AC max ns t LZ(DQS) DQS low-impedance time from CK/ t AC min t AC max t AC min t AC max ns t DQSQ DQS-DQ skew (DQS & associated DQ signals) ns t QHS Data hold Skew Factor ns t QH Data output hold time from DQS t HP - t QHS - t HP - t QHS - ns t DQSS Write command to 1st DQS latching transition t CK t DQSL,(H) t DSS t DSH DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) t CK t CK t CK t MRD Mode register set command cycle time t CK t WPST Write postamble t CK t WPRE Write preamble t CK t IH Address and control input hold time ps t IS Address and control input setup time ns t RPRE Read preamble t CK t RPST Read postamble t CK t Delay Minimum time clocks remains ON after CKE asynchronously drops Low t IS + t CK + t IH - t IS + t CK + t IH - ns t RFC Refresh to active/refresh command time ns REV

15 AC Timing Specifications for DDR2 SDRAM Devices Used on Module (T CASE = 0 C ~ 85 C; V DDQ = 1.8V ± 0.1V; V DD = 1.8V ± 0.1V, See AC Characteristics) (Part 2 of 2) Symbol t REFI Parameter Average Periodic Refresh Interval (85ºC < T CASE 95ºC) Average Periodic Refresh Interval (0ºC T CASE 85ºC) -37B -3C Min. Max. Min. Max. Unit s s Notes t RRD Active bank A to Active bank B command ns t CCD to t CK t WR Write recovery time ns WR Write recovery time with Auto-Precharge t WR/t CK t WR/t CK ns t DAL Auto precharge write recovery + precharge time WR +t RP - WR +t RP - t CK t WTR Internal write to read command delay ns t RTP Internal read to precharge command delay ns t XSNR Exit self refresh to a Non-read command t RFC t RFC ns t XSRD Exit self refresh to a Read command t CK t XP Exit precharge power down to any Non- read command t CK t XARD Exit active power down to read command t CK t XARDS Exit active power down to read command 6-AL - 7-AL - t CK t CKE CKE minimum pulse width t CK t OIT OCD drive mode output delay ns ODT t AOND ODT turn-on delay t CK t AON ODT turn-on t AC (min) t AC (max) +1 t AC(min) t AC(max) +0.7 ns t AONPD ODT turn-on (Power down mode) t AC(min) +2 2t CK + t AC(max)+1 tac(min) +2 2t CK + t AC(max)+1 ns t AOFD ODT turn-off delay t CK t AOF ODT turn-off t AC(min) t AC(max)+0.6 t AC(min) t AC(max)+0.6 ns t AOFPD ODT turn-off (Power down mode) t AC(min) t CK + t AC(max)+1 tac(min) t CK + t AC(max)+1 ns t ANPD ODT to power down entry latency t CK t AXPD ODT power down exit latency t CK Speed Grade Definition t RAS Row Active Time ns t RCD RAS to CAS delay ns t RC Row Cycle Time ns t RP Row Precharge Time ns REV

16 Package Dimensions (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) $#%! &'!"# () *+,-(,-./0123(.,1-(4 5,--(3.2--* 6,-)"+.-$,13-% Note: Device position is only for the reference REV

17 Package Dimensions (512MB 2 Ranks, 32Mx16 DDR2 SDRAMs) $#%! &'!"# () *+,-(,-./0123(.,1-(4 5,--(3.2--* 6,-)"+.-$,13-% Note: Device position is only for the reference REV

18 Revision Log Rev Date Modification /2005 Preliminary /2005 Add Part number in SPD code /2005 Official release /2005 AC timing update /2005 Update SPD code /2006 Update Package Dimensions. Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: Please visit our home page for more information: Printed in Taiwan 2005 REV