Huawei CH240 Compute Node V100R001. White Paper. Issue 08 Date HUAWEI TECHNOLOGIES CO., LTD.

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1 V100R001 Issue 08 Date HUAWEI TECHNOLOGIES CO., LTD.

2 2014. All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Notice The purchased products, services and features are stipulated by the contract made between Huawei and the customer. All or part of the products, services and features described in this document may not be within the purchase scope or the usage scope. Unless otherwise specified in the contract, all statements, information, and recommendations in this document are provided "AS IS" without warranties, guarantees or representations of any kind, either express or implied. The information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute a warranty of any kind, express or implied. Huawei Technologies Co., Ltd. Address: Website: Huawei Industrial Base Bantian, Longgang Shenzhen People's Republic of China i

3 About This Document About This Document Product Positioning This document describes the appearance, features, technical specifications, and configuration of the new-generation CH240 compute node of the HUAWEI E9000 server. Intended Audience This document is intended for: Huawei presales engineers Channel partner presales engineers Huawei enterprise presales engineers Change History Changes between document issues are cumulative. The latest document issue contains all the changes made in earlier issues. This issue is the eighth official release. Mode Deleted Modified Change Description "Tecal" is deleted from the product document. Maximum power consumption and Altitude in 1.7 Technical Specifications are updated. 1.5 Hardware Structure is updated, USB 2.0 port is added to the component figure and description. Issue 07 ( ) This issue is the seventh official release. ii

4 About This Document Mode Modified Change Description The table in 1.5 Hardware Structure is updated. 1.7 Technical Specifications is updated, and key components are added to 1.5 Hardware Structure. Multiple sections in 3 Component Selection are combined as one section. Issue 06 ( ) This issue is the sixth official release. Mode Modified Change Description Intel Xeon E (IvyBridge EP 4S) is added to the CPU models supported by the CH240. All information related to this addition is updated in this document. Issue 05 ( ) This issue is the fifth official release. Mode Modified Change Description The content in 3 Component Selection is modified. Issue 04 ( ) This issue is the fourth official release. Mode Modified Change Description The content in I/O Expansion is modified. Issue 03 ( ) This issue is the third official release. Mode Modified Change Description The content in 3 Component Selection is modified. iii

5 About This Document Issue 02 ( ) This issue is the second official release. Mode Modified Change Description The table of compatible dual in-line memory modules (DIMMs) in Memory is updated. The positions of 1.4 Ports and 1.3 Indicators are exchanged. Issue 01 ( ) This issue is the first official release. iv

6 Contents Contents About This Document...ii 1 Overview Functions Appearance Indicators Ports Hardware Structure Architecture Technical Specifications Features Component Selection Management Warranty Certifications...30 v

7 1 Overview 1 Overview About This Chapter 1.1 Functions This topic describes the basic functions and components of the CH Appearance This topic describes the appearance, front panel, installation position, and slot numbering of the CH Indicators This topic describes the indicators on the CH Ports This topic describes the ports on the CH240 and provides detailed information about the highdensity cable. 1.5 Hardware Structure This topic describes the components, mainboard layout, and connectors of the CH Architecture This topic describes the CH240 logical architecture. 1.7 Technical Specifications This topic describes specifications of the CH240. 1

8 1 Overview 1.1 Functions This topic describes the basic functions and components of the CH240. The CH240 compute node (CH240 for short) adopts the Intel new-generation Romley CPU. It is a full-width 4-socket compute node that provides large memory capacity, powerful computing capabilities, and flexible scalability. The CH240 is installed in a E9000 chassis and is managed by the management module MM910 in a centralized manner. The CH240 delivers outstanding computing performance and a large memory capacity. is designed for virtualization, cloud computing, high- performance computing, and cluster deployment to meet high-end enterprise service requirements. It is particularly suitable for applications with high performance requirements, such as image and signal processing, financial algorithms, scientific computing, and seismic processing. 1.2 Appearance This topic describes the appearance, front panel, installation position, and slot numbering of the CH240. Appearance Figure 1-1 shows the CH240 appearance. Figure 1-1 Appearance Installation Position 2

9 1 Overview The CH240 is installed in a full-width slot in the front of the E9000 chassis. A chassis can house a maximum of eight CH240s. Figure 1-2 shows the installation positions of the CH240s and slot numbers in the chassis. Figure 1-2 Installation positions and slot numbering Front Panel Figure 1-3 shows the front panel of a CH240. Figure 1-3 Front panel 1 Customization label 2 High-density port 3 Power button/indicator 4 UID button/indicator 5 HLY indicator 6 Ejector lever 7 Spring 8 Hard disk 9 Hard disk active indicator 10 Hard disk fault indicator 3

10 1 Overview 1.3 Indicators This topic describes the indicators on the CH240. You can learn about the status of the CH240 by observing the indicators. Table 1-1 describes the indicators on the CH240. Table 1-1 Indicators on the front panel Indicator Meaning Color State Description PWR Power button/ indicator Yellow and green Off: The compute node is not powered on. Blinking yellow: The power supply is locked, and the compute node cannot be powered on. The power button that locked of reason: When a compute node is being powered on, imana 200 does not start, and the power button on the panel is locked. Shield the power button in imana 200. Steady yellow: The compute node is to be powered on. Steady green: The compute node is properly powered on. NOTE If a compute node is powered on, you can hold down the power button for 6 seconds to forcibly power off the compute node. UID UID button/ indicator Blue The Unit Identification (UID) indicator helps locate a compute node in a rack. You can control the UID indicator status (off or on) by remotely using the MM910 or by manually pressing the UID indicator. Off: The compute node is not located or is not powered on. On: The compute node is located. NOTE If a compute node is powered on, you can hold down the button for 6 seconds to reset imana

11 1 Overview Indicator Meaning Color State Description HLY Health status indicator Red and green Off: The compute node is not powered on. Steady green: The compute node hardware is operating properly. Blinking red (at 1 Hz): A major alarm is generated for the compute node. Blinking red (at 4 Hz): A critical alarm is generated for the compute node. Blinking red (at 5 Hz): The compute node is not properly installed. NOTE It is difficult to distinguish a blinking frequency of 4 Hz from a blinking frequency of 5 Hz. When the HLY indicator is quickly blinking red, you are advised to check whether the device is securely inserted and then check whether a critical alarm is generated. Hard disk active indicator Green Off: The hard disk is not detected or is faulty. Blinking green: Data is being read from, written to the hard disk, or synchronized between hard disks. Steady green: The hard disk is inactive. Hard disk fault indicator Yellow Off: The hard disk is operating properly or hard disks cannot be detected in the RAID. Blinking yellow: The hard disk is being located, or the RAID is being reconstructed. Steady yellow: The hard disk is not detected or is faulty. 1.4 Ports This topic describes the ports on the CH240 and provides detailed information about the highdensity cable. Table 1-2 describes the ports on the CH240. 5

12 1 Overview Table 1-2 Port description Port Category Quantity Description High-density port - 1 The High-density port on the front panel connects to a high-density cable, which provides a DB15 video graphics array (VGA) video port, three USB 2.0 ports, and a RJ45 serial port. Figure 1-4 High-density cable 1 VGA port 2 Two USB ports 3 Serial port 4 One USB port 5 High-density port Hardware Structure This topic describes the components, mainboard layout, and connectors of the CH240. Figure 1-5 shows the components of the CH240. 6

13 Huawei CH240 Compute Node 1 Overview Figure 1-5 Components of the CH240 1 Dual inline-memory module (DIMM) 2 Heat sink 3 CPU 4 Mezz card 5 Mainboard 6 Hard disk tray 7 Hard disk 8 (Optional) USB flash drive 9 (Optional) Trusted platform module (TPM) 10 Redundant array of independent disks (RAID) controller card 11 ibbu 12 (Optional) USB 2.0 Table 1-3 describes the components of the CH240. 7

14 1 Overview Table 1-3 Component description Num ber Name Description 1 DIMM The CH240 can be configured with a maximum of 48 double data rate type 3 (DDR3) DIMMs. Each DDR3 DIMM provides a maximum memory capacity of 32 GB. Maximum memory speed: 1,600 MHz Memory protection: error-correcting code (ECC), mirroring, and sparing. DIMM type: registered DIMM (RDIMM) and load-reduced DIMM (LRDIMM) Mixing different types of DIMMs is not supported. RDIMM: up to 768 GB for 48 x 16 GB RDIMMs and four CPUs LRDIMM: up to 1536 GB for 48 x 32 GB LRDIMMs and four CPUs 2 Heat sink The heat sink is used to cool CPUs. Each CPU is configured with one heat sink. 3 CPU The mainboard supports one, two or four Intel Xeon E5-4600/4600 V2 (Sandy Bridge-EP 4S, IvyBridge EP 4S) CPUs of 95 W, 115 W, and 130 W, with a maximum of 12 cores per CPU. Each CPU integrates a memory controller for supporting four DDR3 memory channels. Each channel supports three DDR3 DIMMs of 1333 MHz, and 1600 MHz. Each CPU integrates a Peripheral Component Interconnect Express (PCIe) controller with 40 lanes and supports PCIe 3.0. Each CPU has two QuickPath buses. Every two CPUs are interconnected through a QuickPath bus at 8.0 GT/s. The maximum dominent frequency supported by the CPUs reaches 3.3 GHz. 4 Mezz card The mainboard provides two mezzanine card connectors to connecting to the slots of switch modules or pass through modules through the backplane. The upper mezz module is Mezz 1, and the lower one is Mezz 2. Mezz 1 connects to slots 2X and 3X. Mezz 2 connects to slots 1E and 4E. 8

15 1 Overview Num ber Name Description 5 Mainboard The mainboard holds the CPUs, DIMMs, hard disk interface modules, power control module, imana 200 (integrated management module), logic module, chipset and display adapter. 6 Hard disk tray Supports hard disks. The server chipset is the Platform Controller Hub (PCH) using the Intel C602 chip. A video chip with 64 MB display memory integrated into the FPGA. The maximum resolution is 1280 x 1024 at 60 Hz with 16 M colors. 7 Hard disk The compute node supports a maximum of eight 2.5-inch hard disk drives (HDDs) or SSDs. Mixed configuration of hard disk drives (HDDs) and SSDs is supported. The hard disk backplane provides eight Serial Attached SCSI (SAS) and Serial Advanced Technology Attachment (SATA) ports for connecting SAS and SATA hard disks. Each hard disk is hot-swappable and can be installed and removed separately. Up to 9.6 TB with fully configured 1.2 TB SAS hard disks Up to 8 TB with fully configured 1 TB SATA hard disks Up to 6.4 TB with fully configured 800 GB SSDs 8 (Optional) USB flash drive The mainboard provides a flash storage module with a maximum capacity of 8 GB as the startup media. 9 (Optional) TPM The Trusted Platform Module (TPM) is a security solution that complies with the Trusted Computing Group (TCG) standards. It enhances platform security by preventing viruses or unauthorized operations. 10 RAID controller card The RAID controller card connects to external hard disks to expand the storage capacity of the compute node. The hard disk backplane provides eight 6 Gbit/s Serial Attached SCSI (SAS) or Serial Advanced Technology Attachment (SATA) ports for connecting SAS disks, SATA disks. The mainboard supports RAID controller cards with the LSISAS2208 and LSISAS2308 chips. The LSISAS2208 RAID controller card supports RAID 0, 1, 5, 6, 10, 50, and 60. The LSISAS2308 RAID controller card supports RAID 0, 1, 1E, and ibbu When the LSISAS2208 or LSISAS2308 controller card is installed, you can install an ibbu to provide power-off protection at power failures. 9

16 1 Overview Num ber Name Description 12 (Optional) USB 2.0 The mainboard provides a built-in USB port for connecting to a USB 2.0 device with the dimensions of 66.1 mm x mm x 7.02 mm. Figure 1-6 shows the positions of the connectors and other components on the CH240 mainboard. Figure 1-6 Positions of the connectors and other components (2A1) 101 (2A2) 102 (2A3) 132 (2D3) 131 (2D2) 130 (2D1) 020 (1C1) 021 (1C2) 022 (1C3) 030 (1D1) 031 (1D2) 032 (1D3) 210 (3B1) 211 (3B2) 212 (3B3) 232 (3D3) 231 (3D2) 230 (3D1) 320 (4C1) 321 (4C2) 322 (4C3) 330 (4D1) 331 (4D2) 332 (4D3) 302 (4A3) 301 (4A2) 300 (4A1) 002 (1A3) 001 (1A2) 000 (1A1) 312 (4B3) 311 (4B2) 310 (4B1) 122 (2C3) 121 (2C2) 120 (2C1) 200 (3A1) 201 (3A2) 202 (3A3) 222 (3C3) 221 (3C2) 220 (3C1) CPU3 110 (2B1) 111 (2B2) 112 (2B3) CPU2 CPU1 012 (1B3) 011 (1B2) 010 (1B1) CPU HDD backpanel connector 2 HDD tray 3 Customer interface board 4 USB port 5 PCH(Platform Controller Hub) 6 BIOS battery 7 RAID card connector 8 USB flash drive connector 9 Mezz card connector 1 10 Mezz card connector 2 10

17 1 Overview 11 Mezz card tray 12 Positioning pin 13 Midplane signal connector 14 Midplane power connector 15 TPM card connector Architecture This topic describes the CH240 logical architecture. Figure 1-7 shows the CH240 logical architecture. The CH240 mainboard holds four next-generation Intel Sandy Bridge-EP or Ivy Bridge-EP CPUs. Each CPU integrates a double data rate type three (DDR3) memory controller and a Peripheral Component Interconnect Express (PCIe) controller. Every two CPUs are connected by a QuickPath Interconnect (QPI) bus at 8.0 GT/s. The CPU and bridge are connected by a Direct Media Interface (DMI) 2.0 interface at 5 GT/s. As PCH (Platform Controller Hub), the Patsburg-A is a next-generation Intel southbridge chip used on server platforms and supports external input/output (I/O) bus interfaces and bus expansion. The hard disk interface module consists of a redundant array of independent disks (RAID) card and a midplane where eight hard disk drives (HDDs) are located. The hard disk interface module connects to a CPU over the PCIe. The integrated management module (imana 200) is connected to the front plane through a video graphics array (VGA) interface. The imana 200 provides device management functions, such as powering on or off the CH240, querying slot IDs, detecting the power supply, and KVM over IP. 11

18 1 Overview Figure 1-7 CH240 logical architecture DIMM QPI CPU (2) CPU (3) DIMM QPI QPI DIMM QPI CPU (1) CPU (4) DIMM HDD/ SSD*8 SAS*4 SAS*4 RAID Card x8pcie DMI2 SAS*4 x16pcie x16pcie Mezz Card 1 Mezz Card 2 USB Patsburg -A VGA imana 1.7 Technical Specifications This topic describes specifications of the CH240. Table 1-4 describes the technical specifications of the CH240. Table 1-4 Technical Specifications Category Item Specifications Physical specifications Dimensions (H x W x D) Color Weight mm x 423 mm x mm (2.4 in. x in. x in.) Front panel: black Cover: silver white Net: 19.5 kg (43.00 lb) Packing materials: 3.6 kg (7.94 lb) 12

19 1 Overview Category Item Specifications Environmental specifications Temperature Operating temperature: 5 C to 40 C (41 F to 104 F) Storage temperature: -40 C to +65 C (-40 F to +149 F) Input power supply Power consumption Temperature change rate Humidity Altitude Rated input voltage Maximum power consumption 15 C/h (27 F/h) Operating humidity: 5% RH to 85% RH (noncondensing) Storage humidity: 5% RH to 95% RH (noncondensing) 900 m ( ft) at 40 C (104 F) When the device is used in an altitude of 900 m to 1800 m, the operating temperature decreases by 1 C (1.8 F) as the altitude increases by 300 m ( ft). 12 V DC 939 W 13

20 2 Features 2 Features Performance and Scalability The CH240 uses the Intel Xeon E5-4600/4600 V2 (Sandy Bridge-EP 4S, IvyBridge EP 4S) series processors. Each processor has up to 12 cores and a L3 cache of 20 MB at a dominant frequency of 3.3 GHz, with two 8 GT/s QuickPath Interconnect (QPI) links between processors. This enables the CH240 to provide optimal processing performance. Each CH240 supports one, two, or four processors, a maximum of 32 cores, and a maximum of 64 threads to maximize the concurrent execution of multithreaded applications. The intelligent autonegotiation function provided by Intel Turbo Boost Technology 2.0 enables the processor cores to run at maximum speeds during peak workloads by temporarily going beyond the processor thermal design power (TDP). Intel Hyper-Threading Technology boosts performance for multithreaded applications by enabling concurrent execution of multiple threads within each processor core (up to two threads per core). Intel Virtualization Technology integrates hardware-level virtualization functions to allow operating system (OS) vendors to better use hardware for addressing virtualization workloads. Intel Advanced Vector Extensions (Intel AVX) improves floating-point computing performance for computing-intensive applications. A total of 48 load-reduced DIMMs (LRDIMMs) provides quick speed, high availability, and a maximum memory capacity of 1,536 GB. The Intel Xeon E5-4600/4600 V2 (Sandy Bridge-EP 4S, IvyBridge EP 4S) series processors provide a maximum memory bandwidth of 51.2 GB/s in theory (64 bit/8 x 1600 MHz x 4 channels). The use of solid-state drives (SSDs) provides better I/O performance than using hard disk drives (HDDs) or using SSDs and HDDs. An SSD supports up to 100 times more input/ output operations per second (IOPS) than a typical HDD. The CH240 offers PCIe 3.0 I/O scalability that improves the maximum bandwidth by 60% (8 GT/s) compared with PCIe 2.0. Intel Integrated I/O enables the PCIe 3.0 controller to be integrated into the Intel Xeon E5 series processors. This shortens I/O latency and enhances overall system performance. 14

21 2 Features Availability and Serviceability The CH240 provides the memory mirroring and memory backup functions to avoid system downtime caused by uncorrectable memory errors. The CH240 supports hot-swappable hard disks to protect data and prolong system running time using redundant array of independent disks (RAID) redundancy. The UID and HLY indicators on the panel and the integrated management module (imana 200) web user interface (WebUI) display the status of key components to quickly lead the technical support personnel to failed (or failing) components. This simplifies maintenance, accelerates troubleshooting, and improves system availability. The CH240 supports SSDs which offer better reliability than HDDs, prolonging the system uptime. The integrated imana 200 module continuously monitors system parameters, triggers alarms, and performs recovery actions to minimize system downtime caused by failures. Manageability and Security The built-in imana management module monitors the server running status and provides remote management functions. An integrated industry-standard Unified Extensible Firmware Interface (UEFI) increases setting, configuring, and updating efficiencies, and simplifies error handling. The optional Trusted Platform Module (TPM) 1.2 provides advanced encryption functions, such as digital signatures and remote authentication. The industry-standard Advanced Encryption Standard New Instruction (AES NI) implements faster and stronger encryption. The Intel Execute Disable Bit (EDB) function in a supported OS prevents certain types of malicious buffer overflow attacks. Intel Trusted Execution Technology provides enhanced security by using hardware-based resistance against malicious software attacks, allowing an application to run in an isolated space that is protected from all other applications running on the OS. Energy Efficiency The Intel Xeon E5-4600/4600 V2 (Sandy Bridge-EP 4S, IvyBridge EP 4S) series processors provide better performance over the previous-generation processors while supporting the same TDP. Intel Intelligent Power Capability powers on and off a processor based on the site requirements to reduce power consumption. Low-voltage Intel Xeon processors consume less energy to satisfy demands of power and thermally constrained data centers and telecommunication environments. Low-voltage 1.35 V DDR3 registered DIMMs (RDIMMs) consume 15% less energy than 1.5 V DDR3 RDIMMs. SSDs consume 80% less power than HDDs. The CH240 uses hexagonal ventilation holes to enable higher ventilation density over round holes, remarkably increasing system cooling efficiency. 15

22 2 Features The efficient voltage regulator down (VRD) power supply units (PSUs) reduce the loss in DC/DC power conversion. The CH240 provides power capping and power control functions. 16

23 3 Component Selection 3 Component Selection This topic describes the software and hardware supported by the CH240. For details about the software and hardware that are compatible with the CH240, see Compatibility. CPU The mainboard supports one, two or four Intel Xeon E5-4600/4600 V2 (Sandy Bridge-EP 4S, IvyBridge EP 4S) CPUs of 95 W, 115 W, and 130 W, with a maximum of 12 cores per CPU. Each CPU integrates a memory controller for supporting four DDR3 memory channels. Each channel supports three DDR3 DIMMs of 1333 MHz, and 1600 MHz. Each CPU integrates a Peripheral Component Interconnect Express (PCIe) controller with 40 lanes and supports PCIe 3.0. Each CPU has two QuickPath buses. Every two CPUs are interconnected through a QuickPath bus at 8.0 GT/s. The maximum dominent frequency supported by the CPUs reaches 3.3 GHz. Memory The CH240 can be configured with a maximum of 48 double data rate type 3 (DDR3) DIMMs. Each DDR3 DIMM provides a maximum memory capacity of 32 GB. Memory Configuration Rules Observe the following rules to configure DIMMs: 1. The CH240 supports 8 GB, 16 GB, and 32 GB DIMMs with a maximum memory capacity of 1,536 GB in full configuration. 2. The CH240 can be configured with either registered DIMMs (RDIMMs) or load-reduced DIMMs (LRDIMMs) V and 1.35 V DIMMs cannot be used in the same compute node. 4. Each channel supports a maximum of eight ranks.(only for RDIMMs) NOTE A channel supports more than eight ranks for LRDIMMs, because a quad-rank LRDIMM generates the same electrical load as a single-rank RDIMM on a memory bus. 17

24 3 Component Selection 5. The maximum number of DIMMs that can be installed in a compute node depends on the processor type, DIMM type, number of ranks, and operating voltage. See "Maximum number of DIMMs" in Table 3-1 and Table 3-2. NOTE Number of DIMMs supported by each channel Number of ranks supported by each channel/ Number of ranks supported by each DIMM 6. All DIMMs in the compute node operate at the same speed, whichever of the following is the lowest: Memory speed supported by a specific processor For details about the lowest of the maximum operating speeds, see Maximum Operating Speed in Table 3-1 and Table 3-2. Table 3-1 DIMM configuration rules for Sandy Bridge CPUs Parameter RDIMM LRDI MM Rank Dual rank Quad rank Quad rank Rated speed (MHz) Rated voltage (V) Operating voltage (V) c Maximum number of DIMMs a Maximum DIMM capacity (GB) Maximum memory capacity (GB) Maximum memory capacity at the maximum operating speed (GB) b b 48 b b b b 768 b b b Maxim um operati ng speed (MHz) 1 DIMM s per channel 1333 Not support ed 1333 Not support ed

25 3 Component Selection Parameter RDIMM LRDI MM 2 DIMM s per channel 1333 Not support ed 1333 Not support ed DIMM s per channel Not support ed 1066 b Not support ed 1066 b 1066 b Not support ed 1066 b a: The maximum number of DIMMs is given for four-processor configuration. If only one processor is installed, the maximum number of DIMMs is 1/4 of the values given in this Table. b: The values with b indicate that all DIMM slots are occupied. c: The operating voltage of the DIMMs configured for Sandy Bridge CPUs varies depending on the number of DIMMs. If fewer than 32 DIMMs are configured, the operating voltage for each DIMM is 1.35 V. If more than 32 DIMMs are configured, the operating voltage for each DIMM is 1.5 V. Note: The table is for reference only. For details about the components that can be purchased, consult the local Hawaii sales representatives. Table 3-2 DIMM configuration rules for Ivy Bridge CPUs Parameter RDIMM LRDIMM Rank Dual rank Quad rank Quad rank Rated speed (MHz) Rated voltage (V) Operating voltage (V) Maximum number 48 b 48 b 48 b 48 b b of DIMMs a Maximum capacity per DIMM (GB) Maximum memory capacity (GB) Maximum memory capacity at the maximum operating speed (GB) b 768 b 768 b 768 b b b 19

26 3 Component Selection Parameter RDIMM LRDIMM Maximu m operatin g speed (MHz) One DIMM per channel Two DIMMs per channel Three DIMMs per channel 800 b 800 b 1066 b 1066 b Not support ed 1066 b a: The maximum number of DIMMs is given for four-processor configuration. If only one processor is installed, the maximum number of DIMMs is 1/4 of the values given in this Table. b: The values with b indicate that all DIMM slots are occupied. Note: The table is for reference only. For details about the components that can be purchased, consult the local Hawaii sales representatives. Memory Slot Configuration Rules Table 3-3 describes the DIMM slot installation sequence. For details about the DIMM slot numbers, see 1.5 Hardware Structure. Table 3-3 DIMM installation sequence Processor CPU 1 DIMM Installation Sequence 1A1, 1B1, 1C1, 1D1, 1A2, 1B2, 1C2, 1D2, 1A3, 1B3, 1C3, 1D3 CPU 1 and CPU 2 1A1, 2A1, 1B1, 2B1, 1C1, 2C1, 1D1, 2D1, 1A2, 2A2, 1B2, 2B2, 1C2, 2C2, 1D2, 2D2, 1A3, 2A3, 1B3, 2B3, 1C3, 2C3, 1D3, 2D3 CPU 1, CPU 2, CPU 3, and CPU 4 1A1, 2A1, 3A1, 4A1, 1B1, 2B1, 3B1, 4B1, 1C1, 2C1, 3C1, 4C1, 1D1, 2D1, 3D1, 4D1, 1A2, 2A2, 3A2, 4A2, 1B2, 2B2, 3B2, 4B2, 1C2, 2C2, 3C2, 4C2, 1D2, 2D2, 3D2, 4D2, 1A3, 2A3, 3A3, 4A3, 1B3, 2B3, 3B3, 4B3, 1C3, 2C3, 3C3, 4C3, 1D3, 2D3, 3D3, 4D3 The CH240 provides 48 double data rate 3 (DDR3) slots for installing DIMMs. Each processor integrates four memory channels. The memory channels for processor 1 are 1A, 1B, 1C, and 1D, those for processor 2 are 2A, 2B, 2C, and 2D, those for processor 3 are 3A, 3B, 3C, and 4C, and those for processor 4 are 4A, 4B, 4C, and 4D. Table 3-4 lists memory channels for each processor. 20

27 3 Component Selection 1A1, 1B1, 1C1, 1D1, 2A1, 2B1, 2C1, 2D1, 3A1, 3B1, 3C1, 3D1, 4A1, 4B1, 4C1, and 4D1 are the primary channels for t1a, 1B, 1C, 1D, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, 4A, 4B, 4C, and 4D respectively. Table 3-4 Memory channels for each processor Channel Location Memory Channel Composition CPU1 1A DIMM000 (1A1) DIMM001 (1A2) DIMM002 (1A3) 1B DIMM010 (1B1) DIMM011 (1B2) DIMM012 (1B3) 1C DIMM020 (1C1) DIMM021 (1C2) DIMM022 (1C3) 1D DIMM030 (1D1) DIMM031 (1D2) DIMM032 (1D3) CPU2 2A DIMM100 (2A1) DIMM101 (2A2) DIMM102 (2A3) 2B DIMM110 (2B1) DIMM111 (2B2) DIMM112 (2B3) 2C DIMM120 (2C1) DIMM121 (2C2) DIMM122 (2C3) 2D DIMM130 (2D1) DIMM131 (2D2) DIMM132 (2D3) CPU3 3A DIMM200 (3A1) DIMM201 (3A2) 21

28 3 Component Selection Channel Location Memory Channel Composition DIMM202 (3A3) 3B DIMM210 (3B1) DIMM211 (3B2) DIMM212 (3B3) 3C DIMM220 (3C1) DIMM221 (3C2) DIMM222 (3C3) 3D DIMM230 (3D1) DIMM231 (3D2) DIMM232 (3D3) CPU4 4A DIMM300 (4A1) DIMM301 (4A2) DIMM302 (4A3) 4B DIMM310 (4B1) DIMM311 (4B2) DIMM312 (4B3) 4C DIMM320 (4C1) DIMM321 (4C2) DIMM322 (4C3) 4D DIMM330 (4D1) DIMM331 (4D2) DIMM332 (4D3) Storage The compute node supports a maximum of eight 2.5-inch hard disk drives (HDDs) or SSDs. Mixed configuration of hard disk drives (HDDs) and SSDs is supported. The hard disk backplane provides eight Serial Attached SCSI (SAS) and Serial Advanced Technology Attachment (SATA) ports for connecting SAS and SATA hard disks. Each hard disk is hot-swappable and can be installed and removed separately. Up to 9.6 TB with fully configured 1.2 TB SAS hard disks Up to 8 TB with fully configured 1 TB SATA hard disks 22

29 3 Component Selection Up to 6.4 TB with fully configured 800 GB SSDs The mainboard supports RAID controller cards with the LSISAS2208 and LSISAS2308 chips. The LSISAS2208 RAID controller card supports RAID 0, 1, 5, 6, 10, 50, and 60. The LSISAS2308 RAID controller card supports RAID 0, 1, 1E, and 10. Table 3-5 describes the performances of different RAID levels, the minimum number of hard disks required, and hard disk utilization. Table 3-5 RAID level comparison RAID Level Reliability Read Performan ce Write Performan ce Minimum Number of Hard Disks Hard Disk Utilization RAID 0 Low High High 2 100% RAID 1 High Low Low 2 50% RAID 5 Medium High Medium 3 (N-1)/N RAID 6 Medium High Medium 4 (N-2)/N RAID 1E High Medium Medium 3 M/N RAID 10 High Medium Medium 4 M/N RAID 50 High High Medium 6 (N-M)/N RAID 60 High High Medium 8 (N-M*2)/N Note: N indicates the number of member hard disks in a RAID. M indicates the number of subgroups of a RAID. I/O Expansion Power Supply Peripherals The CH240 supports the following types of Peripheral Component Interconnect Express (PCIe) mezz modules for connecting to switch modules through the midplane. You can choose a mezz module based on the I/O card type and rate requirements. GE expansion card 10GE expansion card FC expansion card RoCE expansion card The CH240 is powered by the power supply units (PSUs) in the E9000 chassis, without any independent power supply. The CH240 supports the peripherals such as USB DVD-ROM drive and KVM. 23