REV /2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.

Transcription

1 Based on 128Mx8 (2GB) DDR3 SDRAM CDie Features Performance: Speed Sort PC38500 BE PC DIMM CAS Latency 7 9 CG Unit fck Clock Frequency MHz tck Clock Cycle ns fdq DQ Burst Frequency Mbps 204Pin Small Outline Dual InLine Memory Module (SODIMM) 2GB: 256Mx64 Unbuffered DDR3 SODIMM based on 128Mx8 DDR3 SDRAM ADie devices. Intended for 533MHz/667MHz applications Inputs and outputs are SSTL15 compatible V DD = V DDQ = 1.5V ± 0.075V SDRAMs have 8 internal banks for concurrent operation Differential clock inputs Data is read or written on both clock edges DRAM DLL aligns DQ and transitions with clock transitions. Address and control signals are fully synchronous to positive clock edge Gold contacts Serial Presence Detect Programmable Operation: DIMM Latency: 6,7,8,9 Burst Type: Sequential or Interleave Burst Length: BC4, BL8 Operation: Burst Read and Write Two different termination values (Rtt_Nom & Rtt_WR) 14/10/2 (row/column/rank) Addressing for 2GB Extended operating temperature rage Auto SelfRefresh option 2GB: SDRAMs are in 78ball BGA Package RoHS compliance Description M2N2G64CB8HC5N and M2N2G64CB8HC9N are unbuffered 204Pin Double Data Rate 3 (DDR3) Synchronous DRAM Small Outline Dual InLine Memory Module (SODIMM), organized as two ranks of 256Mx64 (2GB) highspeed memory array. Modules use sixteen 128Mx8 (2GB) 78ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All Elixir DDR3 SODIMMs provide a highperformance, flexible 8byte interface in a spacesaving footprint. The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves highspeed data transfer rates of 1066Mbps/1333Mbps. Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0A13 and I/O inputs BA0~BA2 using the mode register set cycle. The DIMM uses serial presencedetect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.2 1

2 Ordering Information Part Number Speed Organization Power Leads Note M2N2G64CB8HC5N BE DDR31066 PC MHz CL = 7) M2N2G64CB8HC5N CG DDR31333 PC MHz CL = 9) M2N2G64CB8HC9N BE DDR31066 PC MHz CL = 7) M2N2G64CB8HC9N CG DDR31333 PC MHz CL = 9) 256M x V Gold 256M x V Gold Pin Description 0, 1 Clock Inputs, positive line DQ0DQ63 Data input/output, Clock Inputs, negative line 07 Data strobes E0, E1 Clock Enable Data strobes complement Row Address Strobe 07 Data Masks Column Address Strobe Temperature event pin Write Enable Reset pin, Chip Selects V REFDQ, V REFCA Input/Output Reference A0A9, A11, A13 Address Inputs V DDSPD SPD and Temp sensor power A10/AP Address Input/AutoPrecharge SA0, SA1 Serial Presence Detect Address Inputs A12/ Address Input/Burst Chop Vtt Termination voltage BA0BA2 SDRAM Bank Address Inputs V SS Ground 0, 1 Active termination control lines V DD Core and I/O power SCL Serial Presence Detect Clock Input NC No Connect SDA Serial Presence Detect Data input/output REV 1.2 2

3 2GB DDR3 SDRAM SODIMM Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 V REFDQ 2 V SS 53 DQ19 54 V SS 105 V DD 106 V DD 155 V SS 156 V SS 3 V SS 4 DQ4 55 V SS 56 DQ A10/AP 108 BA1 157 DQ DQ46 5 DQ0 6 DQ5 57 DQ24 58 DQ BA DQ DQ47 7 DQ1 8 V SS 59 DQ25 60 V SS 111 V DD 112 V DD 161 V SS 162 V SS 9 V SS V SS DQ DQ DQ DQ53 13 V SS 14 V SS 65 V SS 66 V SS 117 V DD 118 V DD 167 V SS 168 V SS 15 DQ2 16 DQ6 67 DQ26 68 DQ A13/NC DQ3 18 DQ7 69 DQ27 70 DQ NC V SS 19 V SS 20 V SS 71 V SS 72 V SS 123 V DD 124 V DD 173 V SS 174 DQ54 21 DQ8 22 DQ12 73 E0 74 E1 125 NC 126 V REFCA 175 DQ DQ55 23 DQ9 24 DQ13 75 V DD 76 V DD 127 V SS 128 V SS 177 DQ V SS 25 V SS 26 V SS 77 NC 78 NC 129 DQ DQ V SS 180 DQ BA2 80 NC 131 DQ DQ DQ DQ V DD 82 V DD 133 V SS 134 V SS 183 DQ V SS 31 V SS 32 V SS 83 A12/ 84 A V SS DQ10 34 DQ14 85 A9 86 A V SS DQ11 36 DQ15 87 V DD 88 V DD 139 V SS 140 DQ V SS 190 V SS 37 V SS 38 V SS 89 A8 90 A6 141 DQ DQ DQ DQ62 39 DQ16 40 DQ20 91 A5 92 A4 143 DQ V SS 193 DQ DQ63 41 DQ17 42 DQ21 93 V DD 94 V DD 145 V SS 146 DQ V SS 196 V SS 43 V SS 44 V SS 95 A3 96 A2 147 DQ DQ SA A1 98 A0 149 DQ V SS 199 V DDSPD 200 SDA V SS 99 V DD 100 V DD 151 V SS SA1 202 SCL 49 V SS 50 DQ Vtt 204 Vtt 51 DQ18 52 DQ REV 1.2 3

4 Input/Output Functional Description Symbol Type Polarity Function 0, 1, E0, E1,,, 0, Input Input Input Input Input Input I/O Cross point Active High Active Low Active Low Active High Active High Cross point The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of and falling edge of. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR3 SDRAM signal when high and deactivates the signal when low. By deactivating the clocks, E low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue, Rank 0 is selected by ; Rank 1 is selected by When sampled at the positive rising edge of and falling edge of, signals,, define the operation to be executed by the SDRAM. Asserts ondie termination for DQ,,, and signals if enabled via the DDR3 SDRAM mode register. The data write masks, associated with one data byte. In Write mode, operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window. Signals are complements, and timing is relative to the cross point of respective and. If the module is to be operated in single ended strobe mode, all signals must be tied on the system board to VSS and DDR3 SDRAM mode registers programmed appropriately. BA0, BA1, BA2 Input Selects which DDR3 SDRAM internal bank of four or eight is activated. A0 A9 A10/AP A11 A12/ A13 Input DQ0 DQ63 Input Data Input/Output pins. During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of and falling edge of. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of and falling edge of. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0BAn inputs. If AP is low, then BA0BAn are used to define which bank to precharge. V DD, V DDSPD, V SS Supply Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module. V REFDQ, V REFCA Supply Reference voltage for SSTL15 inputs SDA I/O This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor. SA0 SA2 Input Address pins used to select the Serial Presence Detect and Temp sensor base address. Output The pin is reserved for use to flag critical module temperature. Input This signal resets the DDR3 SDRAM REV 1.2 4

5 Functional Block Diagram [2GB 2 Ranks, 128Mx8 DDR3 SDRAMs] 1 E1 1 0 E0 0 Vtt VDD Cterm Vtt VDD Cterm Vtt 3 3 DQ[24:31] D11 D3 D4 D DQ[32:39] E 1 1 DQ[8:15] D1 E 0 0 D0 E 2 2 DQ[16:23] D2 E E D9 E D8 E D10 E E D14 E D15 E D13 E E D6 6 6 DQ[48:55] E D7 7 7 DQ[56:63] E D5 5 5 DQ[40:47] E SCL SA0 SA1 SCL SA0 SA1 Notes : SCL A0 A1 A2 SCL A0 A1 A2 Temp Sensor SPD WP SDA SDA 1. DQ wiring may differ from that shown however, DQ,,, and relationships are maintained as shown. Vtt VDDSPD VREFCA VREFDQ VDD VSS 0 1 E0 E1 0 1 Vtt SPD / TS D0D15 D0D15 D0D15 D0D15, SPD, Temp sensor D0D7 D8D15 D0D7 D8D15 D0D7 D8D15 D0D7 D8D15 D0D7 D8D15 Temp Sensor D0D15 REV 1.2 5

6 Byte Serial Presence Detect Part 1 of 2 (2GB) 256Mx64 2Ranks DDR3 SODIMM based on 128Mx8, 1.5V DDR3 SDRAMs with SPD Description 0 CRC range, EEPROM bytes, bytes used SPD Entry Value Serial PD Data Entry (Hexadecimal) BE CG BE CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, 1 SPD revision Revision DRAM device type DDR3 SDRAM 0B 3 Module type (form factor) SODIMM 03 4 SDRAM Device density and banks 8 banks, 1Gb 02 5 SDRAM device row and column count 14 rows, 10 columns 11 6 Module minimum nominal voltage 1.5V 00 7 Module ranks and device DQ count 2 ranks, 8 bits 09 8 ECC tag and module memory Bus width Non ECC, 64bits 03 9 Fine timebase dividend/divisor (in ps) 2.5ps Medium timebase dividend 1ns Medium timebase divisor 8ns Minimum SDRAM cycle time (tmin) 1.875ns 1.5ns 0F 0C 92 Note 13 Reserved Undefined CAS latencies supported 6,7,8 6,7,8,9 1C 3C 15 CAS latencies supported Undefined Minimum CAS latency time (taamin) ns Minimum write recovery time (twrmin) 15ns Minimum to delay (trcdmin) ns Minimum Row Active to Row Active delay (trrdmin) 7.5ns 6ns 3C Minimum row Precharge delay (trpmin) ns Upper nibble for tras and trc 1, Minimum ActivetoPrecharge delay (trasmin) 37.5ns 36ns 2C Minimum ActivetoActive/Refresh delay (trcmin) ns ns Minimum refresh recovery delay (trfcmin) LSB (Combo bytes 24,25) Minimum refresh recovery delay (trfcmin) MSB 110ns Minimum internal WritetoRead command delay (twtrmin) 7.5ns 3C 27 Minimum internal ReadtoPrecharge command delay (trtpmin) 28 Minimum four active window delay (tfawmin) LSB (Combo byte 28, 29) Minimum four active window delay (tfawmin) MSB 37.5ns 30ns 2C F0 30 SDRAM device output drivers suported 31 SDRAM device thermal and refresh options 7.5ns R / 7, DLLOff Mode Support, Extended Temperature Range, ASR, 32 Module thermal sensor Non Thermal Sensor Support SDRAM device type Standard Monolithic Device Reserved Undefined 60 Module height (nominal) 29 < height 30 mm 0F 3C REV 1.2 6

7 Serial Presence Detect Part 2 of 2 (2GB) 256Mx64 2Ranks DDR3 SODIMM based on 128Mx8, 1.5V DDR3 SDRAMs with SPD Byte 61 Module thickness (Max) Description SPD Entry Value Serial PD Data Entry (Hexadecimal) BE CG BE CG Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, 62 Raw Card ID reference Raw Card F DRAM address mapping edge connector Undefined Reserved Undefined Module manufacture ID Nanya Technology 830B Module information Undefined CRC Undefined 503F Module part number ASCII values 146 Module die revision Undefined Module PCB revision Undefined DRAM device manufacturer ID Nanya Technology 830B Manufacturer reserved Undefined Customer reserved Undefined 11 Note REV 1.2 7

8 Environmental Requirements Symbol Parameter Rating Units Note T OPR Module Operating Temperature Range (ambient) 0 to 55 C 3 H OPR Operating Humidity (relative) 10 to 90 % 1 T STG Storage Temperature (Plastic) 55 to 100 C 1 H STG Storage Humidity (without condensation) 5 to 95 % 1 P BAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2 Note: 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. The component maximum case temperature shall not exceed the value specified in the component spec. Absolute Maximum DC Ratings Symbol Parameter Rating Units Note V DD Voltage on VDD pins relative to Vss 0.4 V ~ V V 1, 3 V DDQ Voltage on VDDQ pins relative to Vss 0.4 V ~ V V 1, 3 V IN, V OUT Voltage on I/O pins relative to Vss 0.4 V ~ V V 1 T STG Storage Temperature 55 to +100 C 1, 2 Note: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD512 standard. 3. VDD and VDDQ must be within 300 mv of each other at all times;and VREF must be not greater Operating temperature Conditions Symbol Parameter Rating Units Note T OPER Normal Operating Temperature Range 0 to 85 C 1, 2 Extended Temperature Range 85 to 95 C 1, 3 Note: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature. Full specifications are supported in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval trefi to 3.9 μs. It is also possible to specify a component with 1X refresh (trefi to 7.8μs) in the Extended Temperature Range. Please refer to supplier data sheet and/or the DIMM SPD for option availability. b) If SelfRefresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual SelfRefresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto SelfRefresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto SelfRefresh option availability, Extended Temperature Range support and trefi requirements in the Extended Temperature Range. REV 1.2 8

9 DC Electrical Characteristics and Operating Conditions Symbol Parameter Min Typ Max Units Notes VDD Supply Voltage V 1,2 VDDQ Output Supply Voltage V 1,2 Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. SingleEnded AC and DC Input Levels for Command and Address Symbol Parameter DDR31066 (BE) DDR31333 (CG) Min. Max. Min. Max. VIH.CA(DC) DC Input Logic High Vref VDD Vref VDD V 1 VIL.CA(DC) DC Input Logic Low VSS Vref VSS Vref V 1 VIH.CA(AC) AC Input Logic High Vref Note 2 Vref Note 2 V 1, 2 VIL.CA(AC) AC Input Logic Low Note 2 Vref Note 2 Vref V 1, 2 VIH.CA(AC150) AC Input Logic High Vref Note 2 V 1, 2 VIL.CA(AC150) AC Input Logic Low Note 2 Vref 0.15 V 1, 2 V RefCA(DC) Reference Voltage for ADD, CMD Inputs Units Note 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 Note: 1. For input only pins except RESET#. Vref = VrefCA(DC). 2. See Overshoot and Undershoot Specifications in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than VDD (for reference: approx. +/ 15 mv). 4. For reference: approx. VDD/2 +/ 15 mv. SingleEnded AC and DC Input Levels for DQ and Symbol Parameter DDR31066 (BE) DDR31333 (CG) Min. Max. Min. Max. VIH.DQ(DC) DC Input Logic High Vref VDD Vref VDD V 1 VIL.DQ(DC) DC Input Logic Low VSS Vref VSS Vref V 1 VIH.DQ(AC) AC Input Logic High Vref Note 2 Vref Note 2 V 1, 2, 5 VIL.DQ(AC) AC Input Logic Low Note 2 Vref Note 2 Vref 0.15 V 1, 2, 5 V RefDQ(DC) Reference Voltage for DQ, Inputs Units Note 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 Note: 1. For input only pins except RESET#. Vref = VrefDQ (DC). 2. See Overshoot and Undershoot Specifications in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than VDD (for reference: approx. +/ 15 mv). 4. For reference: approx. VDD/2 +/ 15 mv. 5. Singleended swing requirement for, # is 350 mv (peak to peak). Differential swing requirement for # is 700 mv (peak to peak). REV 1.2 9

10 Operating, Standby, and Refresh Currents T CASE = 0 C ~ 85 C; V DDQ = V DD = 1.5V ± 0.075V (2GB, 2Ranks, base on 128Mx8 DDR3 SDRAMs) Symbol Parameter/Condition DDR31066 DDR31333 Unit I DD0 Operating Current: one bank activate/precharge ma I DD1 Operating Current: one bank activate/read/precharge ma I DD2P(0) Precharge PowerDown Current Fast ExitMR0 bit A12= ma I DD2P(1) Precharge Power Down Current Slow ExitMR0 bit A12= ma I DD2N Precharge Standby Current ma I DD2Q Precharge Quiet Standby current ma I DD3P Active PowerDown Current Always Fast Exit ma I DD3N Active Standby Current ma I DD4W Operating Current: Burst Write ma I DD4R Operating Current: Burst Read ma I DD5B Burst Refresh Current ma I DD6 SelfRefresh Current Normal Temperature Range (085C) ma I DD7 All Bank Interleave Read Current ma REV

11 Speed Bins Speed Bin DDR31066(BE) DDR31333 (CG) CL nrcd nrp Unit Parameter Symbol Min Max Min Max Internal read command to first data taa ns ACT to internal read or write delay time trcd ns PRE command period trp ns ACT to ACT or REF command period trc ns ACT to PRE command period tras *tREFI 36 9*tREFI ns CWL=5 t(avg) ns CL = 6 CWL=6 t(avg) Reserved Reserved ns CWL=7, 8 t(avg) Reserved Reserved ns CWL=5 t(avg) Reserved Reserved ns CWL=6 t(avg) < <2.5 ns CL = 7 CWL=7 t(avg) Reserved Reserved ns CWL=8 t(avg) Reserved Reserved ns CWL=5 t(avg) Reserved Reserved ns CWL=6 t(avg) < <2.5 ns CL = 8 CWL=7 t(avg) Reserved Reserved ns CWL=8 t(avg) Reserved Reserved ns CWL=5, 6 t(avg) Reserved Reserved ns CL = 9 CWL=7 t(avg) Reserved 1.5 <1.875 ns CWL=8 t(avg) Reserved Reserved ns Supported CL settings 6,7,8 6,7,8,9 n Supported CWL Settings 6 6,7 n REV

12 AC Timing Specifications for DDR3 SDRAM Devices Used on Module Clock Timing Minimum Clock Cycle time (DLL off mode) DDR31066 DDR31333 Parameter Symbol Min Max Min Max Units t(dll_o FF) 8 8 ns Average high pulse width tch(avg) t(avg) Average low pulse width tcl(avg) t(avg) Absolute Clock Period t(abs) t(avg)min +tjit(per)min t(avg)max +tjit(per)max t(avg)min +tjit(per)min t(avg)max +tjit(per)max Absolute clock high pulse width tch(abs) ps Absolute clock low pulse width tcl(abs) ps Clock Period Jitter tjit(per) ps Clock Period Jitter during DLL locking period tjit(per,lck) ps Cycle to Cycle Period Jitter tjit(cc) ps Cycle to Cycle Period Jitter during DLL locking period tjit(cc,lck) ps Duty Cycle Jitter tjit(duty) ps Cumulative error across 2 cycles terr(2per) ps Cumulative error across 3 cycles terr(3per) ps Cumulative error across 4 cycles terr(4per) ps Cumulative error across 5 cycles terr(5per) ps Cumulative error across 6 cycles terr(6per) ps Cumulative error across 7 cycles terr(7per) ps Cumulative error across 8 cycles terr(8per) ps Cumulative error across 9 cycles terr(9per) ps Cumulative error across 10 cycles terr(10per) ps Cumulative error across n=11~50 cycles Data Timing terr(nper) terr(npr)min =(1+0.68In(n))*tJIT (per)min terr(npr)max =(1+0.68In(n))*tJIT (per)max terr(npr)min =(1+0.68In(n))*tJIT (per)min terr(npr)max =(1+0.68In(n))*tJIT (per)max, to DQ skew, per group, per access tq ps DQ output hold time from, tqh t(avg) DQ lowimpedance time from, tlz(dq) ps DQ highimpedance time from, thz(dq) ps Data setup time to, reference to Vih(ac) / Vil(ac) levels Data hold time to, reference to Vih(ac) / Vil(ac) levels Data hold time from, referenced to Vih(dc) / Vil(dc) levels tds(base) AC175 tds(base) AC150 tdh(base) DC ps ps ps DQ and Input pulse width for each input tdipw ps Data Strobe Timing, differential READ Preamble trpre t(avg), differential READ Postamble trpst t(avg), differential output high time tqsh t(avg), differential output low time tqsl t(avg), differential WRITE Preamble twpre t(avg), differential WRITE Postamble twpst t(avg), rising dege output access time from rising, t ps, lowimpedance time (Reference from RL1) tlz() ps, highimpedance time (Reference from RL + BL/2) thz() ps, differential input low pulse width tl t(avg), differential input high pulse width th t(avg) ps ps REV

13 Data Strobe Timing DDR31066 DDR31333 Parameter Symbol Min Max Min Max Units, rising edge to, rising edge ts t(avg), falling edge setup time to, rising edge tdss t(avg), falling edge hold time to, rising edge tdsh t(avg) Command and Address Timing DLL locking time tdllk n Internal READ Command to PRECHARGE Command delay trtp max(4n, 7.5ns) max(4n, 7.5ns) Delay from start of internal write transaction to internal read command twtr max(4n, 7.5ns) max(4n, 7.5ns) WRITE recovery time twr ns Mode Register Set command cycle time tmrd 4 4 n Mode Register Set command update delay tmod max(12n, 15ns) max(12n, 15ns) to command delay tccd 4 4 n Auto precharge write recovery + precharge time tdal(min) WR + roundup (trp/t(avg)) n MultiPurpose Register Recovery Time tmprr 1 1 ACTIVE to ACTIVE command period for 1KB page size trrd max(4n, 7.5ns) max(4n, 6ns) Four activate window for 1KB page size tfaw ns Command and Address setup time to, referenced to Vih(ac) / Vil(ac) levels tis(base) ps Command and Address hold time to, referenced to Vih(ac) / Vil(ac) levels tih(base) ps Calibrating Timing Powerup and RESET calibration time tinit n Normal operation Full calibration time toper n Normal operation Short calibration time tcs n Reset Timing Exit Reset from E HIGH to a valid command Self Refresh Timings Exit Self Refresh to commands not requiring a locked DLL txpr txs max(5n, trfc(min) + 10ns) max(5n, trfc(min) + 10ns) max(5n, trfc(min) + 10ns) max(5n, trfc(min) + 10ns) Exit Self Refresh to commands requiring a locked DLL txsdll tdllk(min) tdllk(min) n Minimum E low width for Self Refresh entry to exit timing Valid Clock Requirement after Self Refresh Entry (SRE) or PowerDown Entry (PDE) Valid Clock Requirement after Self Refresh Exit (SRX) or PowerDown Exit (PDX) or Reset Exit Power Down Timings Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL E minimum pulse width tesr te(min) + 1n te(min) + 1n tsre max(5n, 10ns) max(5n, 10ns) tsrx max(5n, 10ns) max(5n, 10ns) txp max(3n, 7.5ns) max(3n, 6ns) txpdll max(10n, 24ns) max(10n, 24ns) te max(3n, 5.625ns) max(3n, 5.625ns) Command pass disable delay tcpded 1 1 n Power Down Entry to Exit Timing tpd te(min) 9*tREFI te(min) 9*tREFI Timing of ACT command to Power Down entry tactpden 1 1 n Timing of PRE or PREA command to Power Down entry tprpden 1 1 n Timing of RD/RDA command to Power Down entry trdpden RL+4+1 RL+4+1 n Timing of WR command to Power Down entry (BL8OTF, WL+4+(tWR/t(a WL+4+(tWR/t(a twrpden n BL8MRS, BC4OTF) vg)) vg)) Timing of WRA command to Power Down entry (BL8OTF, twrapden WL+4+WR+1 WL+4+WR+1 n BL8MRS, BC4OTF) WL+2+(tWR/t(a WL+2+(tWR/t(a Timing of WR command to Power Down entry (BC4MRS) twrpden n vg)) vg)) Timing of WRA command to Power Down entry (BC4MRS) twrapden WL+2+WR+1 WL+2+WR+1 n Timing of REF command to Power down entry trefpden 1 1 n Timing of MRS command to Power Down entry tmrspden tmod(min) tmod(min) REV

14 Timings DDR31066 DDR31333 Parameter Symbol Min Max Min Max Units high time without write command or with write command and BC4 H4 4 4 n high time with Write command and BL8 H8 6 6 n Asynchronous RTT turnon delay (Power Down with DLL frozen) Asynchronous RTT turnoff delay (Power Down with DLL frozen) taonpd ns taofpd ns RTT turnon taon ps RTT_Nom and RTT_WR turnoff time from Loff reference taof t(avg) RTT dynamic change skew tadc t(avg) Write Leveling Timings First / rising edge after write leveling mode is programmed twlmrd n / delay after write leveling mode is programmed twlen n Write leveling setup time from rising, crossing to rising, crossing Write leveling setup hold from rising, crossing to rising, crossing twls ps twlh ps Write leveling output delay twlo ns Write leveling output error twloe ns REV

15 Package Dimensions [2GB 2 Ranks, 128Mx8 DDR3 SDRAMs, M2N2G64CB8HC5N] 2. 0 (0.079) / ( / 0.006) (2.504) 3. 8 max. ( max.) 6.0 (0.236) 20.0 (0.787) / 0.15 ( / 0.006) Detail A Detail B /0.1 ( / 0.004) 4.0 (0.157) 21.0 (0.827) (0.053) 3.0 (0.118 ) 39.0 (1.535) 2x O (0. 071) 0.25 max. (0.010 max.) 2.55 (0.100) 2x 4.0 +/ 0.1 ( / 0.004) 1.65 (0. 065) 1.0 (0.039 ) 0.6 (0.024) / ( / ) Detail A Detail B Units: Millimeters (Inches) Note: Device position and scale are only for reference. REV

16 Package Dimensions [2GB 2 Ranks, 128Mx8 DDR3 SDRAMs, M2N2G64CB8HC9N] 2. 0 (0.079) / ( / 0.006) (2.504) 3. 8 max. ( max.) 6.0 (0.236) 20.0 (0.787) / 0.15 ( / 0.006) Detail A Detail B /0.1 ( / 0.004) 4.0 (0.157) 21.0 (0.827) (0.053) 3.0 (0.118 ) 39.0 (1.535) 2x O (0. 071) 0.25 max. (0.010 max.) 2.55 (0.100) 2x 4.0 +/ 0.1 ( / 0.004) 1.65 (0. 065) 1.0 (0.039 ) 0.6 (0.024) / ( / ) Detail A Detail B Units: Millimeters (Inches) Note: Device position and scale are only for reference. REV

17 Revision Log Rev Date Modification /2009 Preliminary Edition /2010 Official Release /2010 Revision Updated /2010 Add Heat Sink Part Number REV