FPGA IMPLEMENTATION OF OPTIMIZED DDR SDRAM CONTROLLER

Transcription

1 FPGA IMPLEMENTATION OF OPTIMIZED DDR SDRAM CONTROLLER SANTHOSHIMA K G 1, SHILPA K 2 1. PG student VLSI Design & Embedded System SIT, Manglore 2. Dept. of Electronics and Communication Engg.SIT, Manglore santhoshikg742@gmail.com shil.pscies@gmail.com ABSTRACT Today SDRAM memory is used in many applications like smart phone, laptop because of its reduced area, speed, configurable latency and high performance and also it provides double data rate. It is important to provide the memory refresh, read, write signals and initialize the SDRAM memory by proper signals. For this purpose the controller is designed which controls the SDRAM memory by predefined set of command signals. In this paper the optimized controller is designed and implemented on FPGA, the optimization has been done in speed which is targeted for more than 150MHz. And also the design has been focused on both read and writes operation at the same time. The implementation has been done in Verilog by using Modelsim 6.3f and Xilinx ISE Keywords: DDR SDRAM controller, FPGA, simultaneous read & writes. A. Introduction All the electronic systems used for many applications at different criteria from video games for kids to satellite for navigation systems use high speed and high throughput memory which is main feature for all these system. The craze for smart phones has resulted is optimization of memory every time. Memory at the beginning which fetches only single data but nowadays the demand goes to high throughput; the Synchronous Dynamic RAM fetches two data for a single clock cycle which increases speed as well as throughput. The use of flip flops to retain the information but as the density of memory goes on increasing, and then area consumption also increases. So to avoid this DRAM s are used which is useful where memory density can be increased with less power consumption and reduced area. Any computational hardware or commonly computer system requires a minimum storage. The storage requirement can be fulfilled by two different classes of memories viz., Static RAM (SRAM) and Dynamic RAM (DRAM). A flip-flop is used in SRAM to retain the information. SRAM has drawback of low memory density and expensive. When there is a want for mass storage and is not time critical, the DRAMS can be employed in the storage. DRAM is an array of memory cells. In contrast with the structural design of SRAM, the architecture of DRAM packs additional memory cells into the memory. This is the basis for the bulky width of address lines. This cause s additional pin adds up to house increased address lines. Additional pin count poses signal integrity problem and high-priced. To avoid this complication, the address is owed into row and column address bus. Since restriction for the precharge and refresh mechanisms and address multiplexing, DRAM is typically slow. To equivalent the speed of microprocessor, there is a necessity of an additional hardware to go with the processor speed and response of the DRAM. The hardware may be named as a memory controller as it regulates the data into and out of DRAM. To compensate for low speed of operation, several DRAMs are spread over a period of time in parallel. While individual of each gadget is low, the parallel configuration of DRAMs enables more data access at the same time resulting in higher bandwidth. The high bandwidth permits DRAM to direct high throughput even though latency is still high. The pact to increase the bandwidth by means of parallel prototype of DRAM devices is replicated and 44

2 arranged as banks exterior to the integrated component. In the beginner stage of progress DRAMs implemented asynchronous protocol for interfacing and communication. This protocol is inherently slow. To reduce latency and to sustain the same bandwidth synchronous protocol is adopted in the design of DRAMs devices and hence they became synchronous DRAMs (SDRAMs). Synchronous DRAM (SDRAM) has turn into a conventional memory of choice in embedded system memory design due to its speed, burst access and pipeline features. In support of high-end applications by means of processors such as Motorola MPC 8260 or Intel Strong Arm, the interface to the SDRAM is supported by the processor s built-in peripheral module. However, for other applications, the system up market must design a controller to make available proper commands for SDRAM initialization, read/write accesses and memory refresh. In some cases, SDRAM is preferred because the earlier generations of DRAM (FP and EDO) are either endof-life or not an optional for new designs by the memory vendors. From the board design point of view, design using earlier generations of DRAM is to a great extent easier and more straightforward than using SDRAM except the system bus master provides the SDRAM interface module as mentioned above. This SDRAM controller orientation design, located between the SDRAM and the bus master, reduces the user s exertion to deal with the SDRAM command interface by providing a simple generic system interface to the bus master. Figure 1.1 shows the relationship of the controller between the bus master and SDRAM. The bus master can be moreover a microprocessor or a user s proprietary module interface. Figure 1.1 DDR SDRAM Controller systems In today's SDRAM market, there are two major types of SDRAM well-known by their data transfer rates. The most common single data rate (SDR) SDRAM transfers data on the rising edge of the clock. The double data rate (DDR) SDRAM which transfers data on both the rising and falling edge to double the data transfer throughput. With Microprocessors getting faster every year, memory architectures be required to improve to boost overall system performance. Subsequently Generation of SDRAM is DDR, or Double Data Rate. Like SDRAM, DDR is Synchronous with the System Clock, even if similar, in that both are Synchronous, the big difference between DDR and SDRAM is that DDR reads data on both the rising and falling edges of the clock signal, while SDRAM only carries information on the rising edge of a signal. This development allows the DDR module to transfer data twice as fast as SDRAM. As an example, as a replacement of a data rate of 133MHz, DDR memory transfers data at 266MHz.DDR modules, parallel to their SDRAM predecessors, similar in there. While motherboards intended to employ DDR are similar to those that use SDRAM, they are not backward compatible with motherboards that support SDRAM. In previous SDRAM based motherboards cannot use DDR, nor can use SDRAM on motherboards that are designed for DDR. B. Literature Survey Generally the controller placed between the CPU and memory bus so as to improve the performance and save energy. The modern standard memory bus clock varies from 100MHz to 200MHz, where as the standard I/O bus is still 33MHz PCI bus for commercial PCs. Hence this chapter gives the brief introduction of DDR SDRAM controller methodology utilized in different area and the results. Related Work In high-end video and multimedia processing applications require huge amounts of memory. The usage of conventiona1 dynamic RAM (SDRAM) is preferred [1]. [1] The DDR SDRAM parameters were provides 120 MHz clock speed (240 MHz data transport), 32 bit data bus, 4 banks, a burst length of 8 words (4 clock cycles) and a 64 ms refresh. These parameters were kept constant. [2] In this paper POPeye(probe of performance + eye) simulator has been used to evaluate DRAM performance. There are two DRAMS [2] evaluated DDR-DRAM and D-RDRAM (Direct-Rambus DRAM). 128Mbyte DDR-SDRAM module consists of eight 128Mbit DDR-SDRAM (16Mbit x 8bit) chips. Each DDR-SDRAM has 4 banks. The modules have the maximum bandwidth of 2.1 Gbyte/sec (=133MHz x 2 (Double Data Rate) x 45

3 64bit(I/O pins)) with 64bit bus at 133MHz.[2] 128Myte D-RDRAM module consists of eight 128Mbit RDRAM (256Kb 16bit 32banks) chips. Each RDRAM has 32 banks. The modules have the maximum bandwidth of 1.6 Gbyte/sec (=Dualoct(16bytes) 400MHz / 4 (4 t cycle )). [3] The indirect accessing method is introduced in DIMMnet-2, since it is not possible to connect the SO-DIMM modules on the DIMMnet-1. In this method, the host CPU can access the SO-DIMM modules on DIMMnet-2 board through the buffer on DIMMnet-2 network interface controller. Using this method, the clock for the memory slot is separated from the clock for on board SO-DIMM; thus, high frequency clocks can be used. Moreover, the network interface controller can be used to accelerate the complicated access to memory on DIMMnet-2.[4]In this paper the data received at the both edge are translated into 128 bits width at only rising edge of the clock. The PC-1600 DDR-SDRAM memory can be used and hence with the limitation of FPGA, the frequency is set to 100MHz. [4] RAID assist logic is capable of transferring 2GB/sec. Active power consumption is as low as 6W with a 1.5 volt supply. The SOC has been implemented in a 0.13 urn, 1.5 V nominal supply, bulk CMOS process. [5] DDR SDRAM controller is designed for high end high speed applications. A memory chip rating of 70ns means that it takes 70 nanoseconds to completely read and recharge each cell DRAMs are measured by storage capability and access time. Storage is rated in megabytes (8MB, 16 MB, etc). Access time is rated in nanoseconds (60ns, 70ns, 80ns, etc) and represents the amount of time to save or return information. With a 60ns DRAM, it would require 60 billionths of a second to save or return information. Can only execute either a read or write operation at one time. The capacitor in a dynamic RAM memory cell is like a leaky bucket. It needs to be refreshed periodically or it will discharge to 0. The speed it works at 150MHz and 5 Adders/subtractors, 6 counters and 150 registers have been used. The present work paper the optimized DDR SRAM controller has targeted to more than 150MHz, with less power consumption and also design has been focused on both read and write operation where as the in paper [3] is not possible. 46

4 C. Proposed Implementation DDR SDRAM Controller Fig 3.1: Functional block diagram of DDR SDRAM controller The designed building block shown in fig 3.1 of the DDR controller consists of three modules, the main control module, the signal generation module and the data path module. The Main control module has two state machines and a refresh counter, which generates proper istate and cstate outputs according to the system interface control signals. The signal generation module generates the address and command signals required for DDR based on istate and cstate. The data path module performs the data latching and dispatching of the data between the Processor and DDR. The DDR SDRAM uses double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit wide, one-clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock- cycle data transfers at the I/O pins. Fig 3.2: Data flow module The figure 3.2 shows the data flow module its inputs and outputs as shown in the figure. The data flow design between the SDRAM and the system interface. The element in this orientation design interfaces between the SDRAM with 16-bit bidirectional data bus and the bus master with 32-bit bidirectional data bus. The consumer is supposed to be able to modify this module toward system bus requirements. The data flow module performs the data latching and dispatching of the data between the processor and DDR. This block always registers the write data from the user interface and prepares to transfer it over to the 2x clock domain. The always block also takes data from the read capture portion of this module and clocks it into the 1x clock domain, adjusting for CAS latency. This block always takes the user write data from the 1x clock domain, transfers it to the 2x clock domain and multiplexes down to half the data width (running at 2x the rate). This always block captures the read data from the SDRAM devices and generates the DQS signal for write to SDRAM operations. 2. Control Module 1. Data Flow Module Fig 3.3 Control state module 47

5 This module decodes the commands from the CMD input to individual command lines, NOP, READA, WRITEA, REFRESH, PRECHARGE, and LOAD_MODE. ADDR is register in order to keep it aligned with decoded command. This block always processes the LOAD_REG1 and LOAD_REG2 commands. The register data comes in on SADDR and is distributed to the various registers. II. Command FSM The block generates the command acknowledge, CMD_ACK, for the Commands that are handled by this module, LOAD_REG1,2, and it lets the command acknowledgement from the lower module pass through when necessary. This block always implements the refresh timer. The timer is a 16bit down counter and a REF_REQ is generated whenever the counter reaches the count of zero. After reaching zero, the counter reloads with the value that was loaded into the refresh period register with the LOAD_REG2 command. The simple state diagram for initial and command FSM of control module given in Fig (3.4.1) and (3.4.2) respectively. I. Initial FSM Fig 3.4.2: State diagram of the Command FSM CONCLUSION The current work the optimized DDR SDRAM controller has besieged to more than 150MHz, with less power consumption and also design has been focused on both read and writes operation. The research on optimized DDR SDRAM controller is still going on. REFERENCE Fig 3.4.1: State diagram of the Initial FSM 1. Heithecker, S. and Ernst, R., Traffic Shaping for An FPGA Based SDRAM Controller with Complex QoS Requirements, Design Automation Conference 2005,June 2005, pp Kangmin Lee, Chi- Weon Yoon, Ramchan Woo, Jeong- Him Kook, Ja-I1 Koo'", Tae-Sung Jung*, and Hoi-Jim Yoo, A Comparative Performance Analysis of a DDR- SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye Simulator, 2001 IEEE. 3. Deepali S h a r m a, S hruti bhargava, M a h e n d r a Vucha, Design and VLSI Implementation of DDR SDRAM Controller for High Speed Applications, (IJCSIT) International Journal of Computer Science and Information Technologies, Vol. 2 (4), 2011, Akira Kitamura, Yoshihiro Hamada, Yasuo Miyabe, Tetsu Izawa, etc.., Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board, Proceedings of the Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies, 2005IEEE. 5. By Gerard Boudon, Alan Wall, Joe Foster, Barry Wolford, John Fakiris, A 800 MHz PowerPC SOC with PCI-X DDFU66, DDRII-667, and RAID Assist, 2004 IEEE. 48