Massimo Bernaschi Istituto Applicazioni del Calcolo Consiglio Nazionale delle Ricerche.
|
|
- Oliver Short
- 7 years ago
- Views:
Transcription
1 Massimo Bernaschi Istituto Applicazioni del Calcolo Consiglio Nazionale delle Ricerche
2 Performance There are two main measurements of performance. Execution time is what we ll focus on. Throughput is important for operating systems. } Performance is mainly driven by the algorithm; } However the SAME algorithm may be implemented in different ways that may have a dramatic impact on the performance } How do we measure performance? } Timers } Profilers
3 Many possible definitions of performance } Every computer vendor will select one that makes them look good. How do you make sense of conflicting claims? Q: Why do end users need a new performance metric? A: End users who rely only on megahertz as an indicator for performance do not have a complete picture of PC processor performance and may pay the price of missed expectations. 3
4 Basis of Comparison When comparing systems, need to fix the workload Which workload? Workload Pros Cons Actual Target Workload Full Application Benchmarks Small Kernel or Synthetic Benchmarks Micro benchmarks Representative Portable Widely used Realistic Easy to run Useful early in design Identify peak capability and potential bottlenecks Very specific Non-portable Difficult to run/measure Less representative Easy to fool Real application performance may be much below peak 4
5 The components of execution time } Execution time can be divided into two parts. User time is spent running the application program itself. System time is when the application calls operating system code. } The distinction between user and system time is not always clear, especially under different operating systems. } The Unix time command shows both. salary.125 > time distill 05-examples.ps Distilling 05-examples.ps (449,119 bytes) 10.8 seconds (0:11) 449,119 bytes PS => 94,999 bytes PDF (21%) 10.61u 0.98s 0: % User time Wall clock time (including other processes) System time CPU usage = (User + System) / Total 5
6 Three Components of CPU Performance CPU time X,P = Instructions executed P * CPI X,P * Clock cycle time X Cycles Per Instruction 6
7 Instructions Executed } Instructions executed: } We are not interested in the static instruction count, or how many lines of code are in a program. } Instead we care about the dynamic instruction count, or how many instructions are actually executed when the program runs. } There are three lines of code below, but the number of instructions executed would be XXXX?. li $a0, 1000 Ostrich: sub $a0, $a0, 1 bne $a0, $0, Ostrich 7
8 CPI } The average number of clock cycles per instruction, or CPI, is a function of the machine and program. } The CPI depends on the actual instructions appearing in the } } program. It also depends on the CPU implementation. } Do not confuse architecture with implementation! In an ideal world each instruction would take one cycle, making CPI = 1. } The CPI can be >1 due to memory stalls and slow instructions. } The CPI can be <1 on machines that execute more than 1 instruction per cycle (superscalar). 8
9 Execution time, again CPU time X,P = Instructions executed P * CPI X,P * Clock cycle time X } } The easiest way to remember this is match up the units: Seconds Instructions Clock cycles Seconds = * * Program Program Instructions Clock cycle Make things faster by making any component smaller!! Program Compiler ISA Organization Technology Instruction Executed CPI } Clock Cycle TIme Often easy to reduce one component by increasing another 9
10 Improving CPI } Many processor design techniques we ll see improve CPI } Often they only improve CPI for certain types of instructions n CPI = Σ CPI F where F = I i i i i i = 1 Instruction Count } Fi = Fraction of instructions of type i First Law of Performance: Make the common case fast 10
11 Time measure and profiling } Many different ways to measure time and profile a code: } A very simple approach: #include <sys/time.h> #define TIMER_DEF struct timeval temp_1, temp_2 #define TIMER_START gettimeofday(&temp_1, (struct timezone*)0) #define TIMER_STOP gettimeofday(&temp_2, (struct timezone*)0) #define TIMER_ELAPSED ((temp_2.tv_sec-temp_1.tv_sec)*1.e6+(temp_2.tv_usec-temp_1.tv_usec)) It is easy when there are just a few points to be checked } Example: matrix-matrix product (mm.c) } Test with and without optimization(-o3) } 11
12 Time measure and profiling (2) } Profilers help to collect timings and show the corresponding results } Classic (Linux) profile (does not work on Mac Osx!). } gprof } requires compilation AND linking with the pg option } } } cc o mm pg mm.c./mm gprof mm } Many modern alternatives: } Linux perf tool } Intel Architecture Code Analyser (IACA) } Valgrind cachegrind 12
13 Perf (1) } Modern processors and operating systems have performance counters, which track performance-affecting events, such as the number of context switches or cache misses. Linux provides perf_event subsystem which allows to read these counters and use them to hunt performance problems. } perf utility makes it even easier. } perf list lists available performance counters } perf top reports system-wide statistics on performance events } perf stat runs a program and reports the total number of performance events for that program. 13
14 Perf (2) } perf record runs a program and records a detailed information about performance events. } perf report allows to browse information collected by perf record. } To get summary statistics for a program: } perf stat -e <counter1> myapp args... } If you specify instructions and cycles, perf will compute average number of instructions per cycle (IPC): } perf stat -e instructions -e cycles myapp args... } Remember: } The higher is IPC the better. } If IPC < 1,you need to work on it. 14
15 Perf (3) } If you specify branches and branch-misses, perf will compute percent of mispredicted branches: } perf stat -e branches -e branch-misses myapp args. } Targets for percent of mispredicted branches: } The less branches are mispredicted the better } If more than 5% of branches are mispredicted, you need to look at it. } To compute percent of cache misses: } perf stat -e cache-references -e cache-misses myapp args... } Targets for percent of cache misses: } The less cache references are missed the better } If >10% of cache references are missed, investigate it. 15
16 Valgrind (1) } Valgrind is a framework which allows to intercept execution of specific classes of instructions (like loads and stores). } There are a number of tools built on top of valgrind for research and analysis. } Cachegrind utility simulates processor caches and provides information on the number of cache misses. } Unlike perf utility, cachegrind allows to change size and other parameters of simulated caches and analyse how it affects cache miss rate. 16
17 Valgrind (2) } A program myapp can be launched under cachegrind with command } valgrind --tool=cachegrind myapp args } cachegrind parameters -I1, -D1, and -LL allow to change parameters of simulated caches: valgrind --tool=cachegrind --D1=65536,8,64 myapp args... 17
18 3 possible compilers } GNU Compilers Collection (gcc/g++) } Default compiler on Linux } Produces very fast code } Clang C/C++ Compilers (clang/clang++) } Default compiler on Mac OS X and FreeBSD } Much better error reporting than gcc } Usually produces slower code than gcc, but sometimes can be faster } Compiler options, pragmas, and other extensions compatible with gcc } Intel C/C++ Compilers (icc/icpc) } Better error reporting than gcc } For Intel processors often produces faster code than gcc } More or less compatible with gcc 18
19 Basic optimization options } -O0 enable only optimizations which do not mess up debugging } -O2 enable all basic optimizations for performance } -O3 = -O2 + speculative optimizations } -Os optimize for code size } For large code bases this results in faster code than -O3 19
20 Machine-specific optimization options (gcc and clang) } -march=<cpu> use all instructions available on <cpu>. Valid <cpu> values: } core2 for Intel Core 2 and Xeon processors of the same generation (Harpertown, Clovertown). For 45nm Core 2. processors (and Harpertown Xeons) you should also specify -msse4.1 because they additionally support SSE4.1 instruction set. } corei7 for Intel Nehalem and Westmere: firrst generation Core-i7 processors and Xeon 5500 and 5600 series. } corei7-avx for Intel Sandy Bridge processors (aka second-generation Core-i7). } core-avx-i for Intel Ivy Bridge processors (aka third-generation Core-i7). } core-avx2 for Intel Haswell processors (aka fourth-generation Core-i7). } bdver1 for AMD Bulldozer processors (Opteron 3200, 4200, and 6200 series). } bdver2 for AMD Piledriver processors (Trinity APUs, Opteron 3300, 4300, and 6300 series). } native for the CPU you compile on (sometimes misdetects CPU). 20
21 Inter-Procedural Optimization } Postpones code generation until linking stage when all information about the program is available. } Different options for different compilers: } -ipo for Intel Compiler. } -flto for GNU and Clang compilers. } These options must be specified during both compilation and linking. 21
22 Profile-Guided Optimization } Often there is not enough information in compilation time to properly optimize the code. Profile-Guided Optimization allows the compiler to collect information from program runs, and then use this information to improve optimization quality. } Using PGO with GNU Compilers 1. Compile your program with -fprofile-generate parameter } gcc ${CFLAGS} -fprofile-generate -o myapp myapp.c 2. Run the program on representative input }./myapp testdata.input 3. Compile your program again with -fprofile-use parameter } gcc ${CFLAGS} -fprofile-use -o myapp myapp.c 22
Multi-Threading Performance on Commodity Multi-Core Processors
Multi-Threading Performance on Commodity Multi-Core Processors Jie Chen and William Watson III Scientific Computing Group Jefferson Lab 12000 Jefferson Ave. Newport News, VA 23606 Organization Introduction
More informationCS3813 Performance Monitoring Project
CS3813 Performance Monitoring Project Owen Kaser October 8, 2014 1 Introduction In this project, you should spend approximately 20 hours to experiment with Intel performance monitoring facilities, and
More informationPerformance Counter. Non-Uniform Memory Access Seminar Karsten Tausche 2014-12-10
Performance Counter Non-Uniform Memory Access Seminar Karsten Tausche 2014-12-10 Performance Counter Hardware Unit for event measurements Performance Monitoring Unit (PMU) Originally for CPU-Debugging
More informationChapter 2. Why is some hardware better than others for different programs?
Chapter 2 1 Performance Measure, Report, and Summarize Make intelligent choices See through the marketing hype Key to understanding underlying organizational motivation Why is some hardware better than
More informationUnit 4: Performance & Benchmarking. Performance Metrics. This Unit. CIS 501: Computer Architecture. Performance: Latency vs.
This Unit CIS 501: Computer Architecture Unit 4: Performance & Benchmarking Metrics Latency and throughput Speedup Averaging CPU Performance Performance Pitfalls Slides'developed'by'Milo'Mar0n'&'Amir'Roth'at'the'University'of'Pennsylvania'
More informationLecture 3: Evaluating Computer Architectures. Software & Hardware: The Virtuous Cycle?
Lecture 3: Evaluating Computer Architectures Announcements - Reminder: Homework 1 due Thursday 2/2 Last Time technology back ground Computer elements Circuits and timing Virtuous cycle of the past and
More informationPerf Tool: Performance Analysis Tool for Linux
/ Notes on Linux perf tool Intended audience: Those who would like to learn more about Linux perf performance analysis and profiling tool. Used: CPE 631 Advanced Computer Systems and Architectures CPE
More informationAchieving Nanosecond Latency Between Applications with IPC Shared Memory Messaging
Achieving Nanosecond Latency Between Applications with IPC Shared Memory Messaging In some markets and scenarios where competitive advantage is all about speed, speed is measured in micro- and even nano-seconds.
More informationUsing Power to Improve C Programming Education
Using Power to Improve C Programming Education Jonas Skeppstedt Department of Computer Science Lund University Lund, Sweden jonas.skeppstedt@cs.lth.se jonasskeppstedt.net jonasskeppstedt.net jonas.skeppstedt@cs.lth.se
More informationPerformance Monitoring of the Software Frameworks for LHC Experiments
Proceedings of the First EELA-2 Conference R. mayo et al. (Eds.) CIEMAT 2009 2009 The authors. All rights reserved Performance Monitoring of the Software Frameworks for LHC Experiments William A. Romero
More informationLecture 11: Multi-Core and GPU. Multithreading. Integration of multiple processor cores on a single chip.
Lecture 11: Multi-Core and GPU Multi-core computers Multithreading GPUs General Purpose GPUs Zebo Peng, IDA, LiTH 1 Multi-Core System Integration of multiple processor cores on a single chip. To provide
More informationMulti-core architectures. Jernej Barbic 15-213, Spring 2007 May 3, 2007
Multi-core architectures Jernej Barbic 15-213, Spring 2007 May 3, 2007 1 Single-core computer 2 Single-core CPU chip the single core 3 Multi-core architectures This lecture is about a new trend in computer
More informationThe Impact of Memory Subsystem Resource Sharing on Datacenter Applications. Lingia Tang Jason Mars Neil Vachharajani Robert Hundt Mary Lou Soffa
The Impact of Memory Subsystem Resource Sharing on Datacenter Applications Lingia Tang Jason Mars Neil Vachharajani Robert Hundt Mary Lou Soffa Introduction Problem Recent studies into the effects of memory
More informationRecommended hardware system configurations for ANSYS users
Recommended hardware system configurations for ANSYS users The purpose of this document is to recommend system configurations that will deliver high performance for ANSYS users across the entire range
More informationA Study of Performance Monitoring Unit, perf and perf_events subsystem
A Study of Performance Monitoring Unit, perf and perf_events subsystem Team Aman Singh Anup Buchke Mentor Dr. Yann-Hang Lee Summary Performance Monitoring Unit, or the PMU, is found in all high end processors
More informationFull and Para Virtualization
Full and Para Virtualization Dr. Sanjay P. Ahuja, Ph.D. 2010-14 FIS Distinguished Professor of Computer Science School of Computing, UNF x86 Hardware Virtualization The x86 architecture offers four levels
More information! Metrics! Latency and throughput. ! Reporting performance! Benchmarking and averaging. ! CPU performance equation & performance trends
This Unit CIS 501 Computer Architecture! Metrics! Latency and throughput! Reporting performance! Benchmarking and averaging Unit 2: Performance! CPU performance equation & performance trends CIS 501 (Martin/Roth):
More informationSystem Requirements Table of contents
Table of contents 1 Introduction... 2 2 Knoa Agent... 2 2.1 System Requirements...2 2.2 Environment Requirements...4 3 Knoa Server Architecture...4 3.1 Knoa Server Components... 4 3.2 Server Hardware Setup...5
More informationSystem/Networking performance analytics with perf. Hannes Frederic Sowa <hannes@stressinduktion.org>
System/Networking performance analytics with perf Hannes Frederic Sowa Prerequisites Recent Linux Kernel CONFIG_PERF_* CONFIG_DEBUG_INFO Fedora: debuginfo-install kernel for
More informationSTUDY OF PERFORMANCE COUNTERS AND PROFILING TOOLS TO MONITOR PERFORMANCE OF APPLICATION
STUDY OF PERFORMANCE COUNTERS AND PROFILING TOOLS TO MONITOR PERFORMANCE OF APPLICATION 1 DIPAK PATIL, 2 PRASHANT KHARAT, 3 ANIL KUMAR GUPTA 1,2 Depatment of Information Technology, Walchand College of
More informationMore on Pipelining and Pipelines in Real Machines CS 333 Fall 2006 Main Ideas Data Hazards RAW WAR WAW More pipeline stall reduction techniques Branch prediction» static» dynamic bimodal branch prediction
More informationDebugging & Profiling with Open Source SW Tools
Debugging & Profiling with Open Source SW Tools Ivan Giro*o igiro*o@ictp.it Informa(on & Communica(on Technology Sec(on (ICTS) Interna(onal Centre for Theore(cal Physics (ICTP) What is Debugging?! Iden(fying
More informationSolution: start more than one instruction in the same clock cycle CPI < 1 (or IPC > 1, Instructions per Cycle) Two approaches:
Multiple-Issue Processors Pipelining can achieve CPI close to 1 Mechanisms for handling hazards Static or dynamic scheduling Static or dynamic branch handling Increase in transistor counts (Moore s Law):
More informationGenerations of the computer. processors.
. Piotr Gwizdała 1 Contents 1 st Generation 2 nd Generation 3 rd Generation 4 th Generation 5 th Generation 6 th Generation 7 th Generation 8 th Generation Dual Core generation Improves and actualizations
More informationEC 362 Problem Set #2
EC 362 Problem Set #2 1) Using Single Precision IEEE 754, what is FF28 0000? 2) Suppose the fraction enhanced of a processor is 40% and the speedup of the enhancement was tenfold. What is the overall speedup?
More informationWindows Server Performance Monitoring
Spot server problems before they are noticed The system s really slow today! How often have you heard that? Finding the solution isn t so easy. The obvious questions to ask are why is it running slowly
More informationStACC: St Andrews Cloud Computing Co laboratory. A Performance Comparison of Clouds. Amazon EC2 and Ubuntu Enterprise Cloud
StACC: St Andrews Cloud Computing Co laboratory A Performance Comparison of Clouds Amazon EC2 and Ubuntu Enterprise Cloud Jonathan S Ward StACC (pronounced like 'stack') is a research collaboration launched
More informationPSE Molekulardynamik
OpenMP, bigger Applications 12.12.2014 Outline Schedule Presentations: Worksheet 4 OpenMP Multicore Architectures Membrane, Crystallization Preparation: Worksheet 5 2 Schedule 10.10.2014 Intro 1 WS 24.10.2014
More informationPOWER8 Performance Analysis
POWER8 Performance Analysis Satish Kumar Sadasivam Senior Performance Engineer, Master Inventor IBM Systems and Technology Labs satsadas@in.ibm.com #OpenPOWERSummit Join the conversation at #OpenPOWERSummit
More informationMemory Access Control in Multiprocessor for Real-time Systems with Mixed Criticality
Memory Access Control in Multiprocessor for Real-time Systems with Mixed Criticality Heechul Yun +, Gang Yao +, Rodolfo Pellizzoni *, Marco Caccamo +, Lui Sha + University of Illinois at Urbana and Champaign
More informationQEMU, a Fast and Portable Dynamic Translator
QEMU, a Fast and Portable Dynamic Translator Fabrice Bellard Abstract We present the internals of QEMU, a fast machine emulator using an original portable dynamic translator. It emulates several CPUs (x86,
More informationVMware Server 2.0 Essentials. Virtualization Deployment and Management
VMware Server 2.0 Essentials Virtualization Deployment and Management . This PDF is provided for personal use only. Unauthorized use, reproduction and/or distribution strictly prohibited. All rights reserved.
More informationSequential Performance Analysis with Callgrind and KCachegrind
Sequential Performance Analysis with Callgrind and KCachegrind 2 nd Parallel Tools Workshop, HLRS, Stuttgart, July 7/8, 2008 Josef Weidendorfer Lehrstuhl für Rechnertechnik und Rechnerorganisation Institut
More informationCPU Performance. Lecture 8 CAP 3103 06-11-2014
CPU Performance Lecture 8 CAP 3103 06-11-2014 Defining Performance Which airplane has the best performance? 1.6 Performance Boeing 777 Boeing 777 Boeing 747 BAC/Sud Concorde Douglas DC-8-50 Boeing 747
More informationOverview on Modern Accelerators and Programming Paradigms Ivan Giro7o igiro7o@ictp.it
Overview on Modern Accelerators and Programming Paradigms Ivan Giro7o igiro7o@ictp.it Informa(on & Communica(on Technology Sec(on (ICTS) Interna(onal Centre for Theore(cal Physics (ICTP) Mul(ple Socket
More informationThe ROI from Optimizing Software Performance with Intel Parallel Studio XE
The ROI from Optimizing Software Performance with Intel Parallel Studio XE Intel Parallel Studio XE delivers ROI solutions to development organizations. This comprehensive tool offering for the entire
More informationMetrics for Success: Performance Analysis 101
Metrics for Success: Performance Analysis 101 February 21, 2008 Kuldip Oberoi Developer Tools Sun Microsystems, Inc. 1 Agenda Application Performance Compiling for performance Profiling for performance
More informationBasics of VTune Performance Analyzer. Intel Software College. Objectives. VTune Performance Analyzer. Agenda
Objectives At the completion of this module, you will be able to: Understand the intended purpose and usage models supported by the VTune Performance Analyzer. Identify hotspots by drilling down through
More informationHardware performance monitoring. Zoltán Majó
Hardware performance monitoring Zoltán Majó 1 Question Did you take any of these lectures: Computer Architecture and System Programming How to Write Fast Numerical Code Design of Parallel and High Performance
More informationPerformance monitoring at CERN openlab. July 20 th 2012 Andrzej Nowak, CERN openlab
Performance monitoring at CERN openlab July 20 th 2012 Andrzej Nowak, CERN openlab Data flow Reconstruction Selection and reconstruction Online triggering and filtering in detectors Raw Data (100%) Event
More informationReal-Time Scheduling 1 / 39
Real-Time Scheduling 1 / 39 Multiple Real-Time Processes A runs every 30 msec; each time it needs 10 msec of CPU time B runs 25 times/sec for 15 msec C runs 20 times/sec for 5 msec For our equation, A
More informationIntroducing the IBM Software Development Kit for PowerLinux
Introducing the IBM Software Development Kit for PowerLinux Wainer S. Moschetta IBM, PowerLinux SDK Team Leader wainersm@br.ibm.com 1 2009 IBM Acknowledgments The information in this presentation was created
More informationPerformance evaluation
Performance evaluation Arquitecturas Avanzadas de Computadores - 2547021 Departamento de Ingeniería Electrónica y de Telecomunicaciones Facultad de Ingeniería 2015-1 Bibliography and evaluation Bibliography
More informationPerformance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 64 Architecture
Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 64 Architecture Dong Ye David Kaeli Northeastern University Joydeep Ray Christophe Harle AMD Inc. IISWC 2006 1 Outline Motivation
More informationInstruction Set Architecture. or How to talk to computers if you aren t in Star Trek
Instruction Set Architecture or How to talk to computers if you aren t in Star Trek The Instruction Set Architecture Application Compiler Instr. Set Proc. Operating System I/O system Instruction Set Architecture
More informationIntroduction 1 Performance on Hosted Server 1. Benchmarks 2. System Requirements 7 Load Balancing 7
Introduction 1 Performance on Hosted Server 1 Figure 1: Real World Performance 1 Benchmarks 2 System configuration used for benchmarks 2 Figure 2a: New tickets per minute on E5440 processors 3 Figure 2b:
More informationIntel DPDK Boosts Server Appliance Performance White Paper
Intel DPDK Boosts Server Appliance Performance Intel DPDK Boosts Server Appliance Performance Introduction As network speeds increase to 40G and above, both in the enterprise and data center, the bottlenecks
More informationPerformance Application Programming Interface
/************************************************************************************ ** Notes on Performance Application Programming Interface ** ** Intended audience: Those who would like to learn more
More informationParallel Processing using the LOTUS cluster
Parallel Processing using the LOTUS cluster Alison Pamment / Cristina del Cano Novales JASMIN/CEMS Workshop February 2015 Overview Parallelising data analysis LOTUS HPC Cluster Job submission on LOTUS
More informationLinux Performance Optimizations for Big Data Environments
Linux Performance Optimizations for Big Data Environments Dominique A. Heger Ph.D. DHTechnologies (Performance, Capacity, Scalability) www.dhtusa.com Data Nubes (Big Data, Hadoop, ML) www.datanubes.com
More informationLS-DYNA Best-Practices: Networking, MPI and Parallel File System Effect on LS-DYNA Performance
11 th International LS-DYNA Users Conference Session # LS-DYNA Best-Practices: Networking, MPI and Parallel File System Effect on LS-DYNA Performance Gilad Shainer 1, Tong Liu 2, Jeff Layton 3, Onur Celebioglu
More informationADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM
ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM 1 The ARM architecture processors popular in Mobile phone systems 2 ARM Features ARM has 32-bit architecture but supports 16 bit
More informationSIDN Server Measurements
SIDN Server Measurements Yuri Schaeffer 1, NLnet Labs NLnet Labs document 2010-003 July 19, 2010 1 Introduction For future capacity planning SIDN would like to have an insight on the required resources
More informationFigure 1: Graphical example of a mergesort 1.
CSE 30321 Computer Architecture I Fall 2011 Lab 02: Procedure Calls in MIPS Assembly Programming and Performance Total Points: 100 points due to its complexity, this lab will weight more heavily in your
More informationUnderstanding the Performance of an X550 11-User Environment
Understanding the Performance of an X550 11-User Environment Overview NComputing's desktop virtualization technology enables significantly lower computing costs by letting multiple users share a single
More informationIntel Application Software Development Tool Suite 2.2 for Intel Atom processor. In-Depth
Application Software Development Tool Suite 2.2 for Atom processor In-Depth Contents Application Software Development Tool Suite 2.2 for Atom processor............................... 3 Features and Benefits...................................
More informationWindows XP Professional x64 Edition for HP Workstations - FAQ
1. What is Microsoft Windows XP Professional x64 Edition? Windows XP Professional x64 Edition is the client version of the Microsoft 64-bit operating system that executes on 64-bit extensions systems.
More informationThe Art of Workload Selection
The Art of Workload Selection 5-1 Overview Services Exercised Example: Timesharing Systems Example: Networks Example: Magnetic Tape Backup System Level of Detail Representativeness Timeliness Other Considerations
More informationBuilding Embedded Systems
All Rights Reserved. The contents of this document cannot be reproduced without prior permission of the authors. Building Embedded Systems Chapter 5: Maintenance and Debugging Andreas Knirsch andreas.knirsch@h-da.de
More informationECLIPSE Performance Benchmarks and Profiling. January 2009
ECLIPSE Performance Benchmarks and Profiling January 2009 Note The following research was performed under the HPC Advisory Council activities AMD, Dell, Mellanox, Schlumberger HPC Advisory Council Cluster
More informationLattice QCD Performance. on Multi core Linux Servers
Lattice QCD Performance on Multi core Linux Servers Yang Suli * Department of Physics, Peking University, Beijing, 100871 Abstract At the moment, lattice quantum chromodynamics (lattice QCD) is the most
More informationPAPI - PERFORMANCE API. ANDRÉ PEREIRA ampereira@di.uminho.pt
1 PAPI - PERFORMANCE API ANDRÉ PEREIRA ampereira@di.uminho.pt 2 Motivation Application and functions execution time is easy to measure time gprof valgrind (callgrind) It is enough to identify bottlenecks,
More informationPERFORMANCE ENHANCEMENTS IN TreeAge Pro 2014 R1.0
PERFORMANCE ENHANCEMENTS IN TreeAge Pro 2014 R1.0 15 th January 2014 Al Chrosny Director, Software Engineering TreeAge Software, Inc. achrosny@treeage.com Andrew Munzer Director, Training and Customer
More informationCPS221 Lecture: Operating System Structure; Virtual Machines
Objectives CPS221 Lecture: Operating System Structure; Virtual Machines 1. To discuss various ways of structuring the operating system proper 2. To discuss virtual machines Materials: 1. Projectable of
More informationIntroduction to GPU hardware and to CUDA
Introduction to GPU hardware and to CUDA Philip Blakely Laboratory for Scientific Computing, University of Cambridge Philip Blakely (LSC) GPU introduction 1 / 37 Course outline Introduction to GPU hardware
More informationSawmill Log Analyzer Best Practices!! Page 1 of 6. Sawmill Log Analyzer Best Practices
Sawmill Log Analyzer Best Practices!! Page 1 of 6 Sawmill Log Analyzer Best Practices! Sawmill Log Analyzer Best Practices!! Page 2 of 6 This document describes best practices for the Sawmill universal
More informationOperating System Impact on SMT Architecture
Operating System Impact on SMT Architecture The work published in An Analysis of Operating System Behavior on a Simultaneous Multithreaded Architecture, Josh Redstone et al., in Proceedings of the 9th
More informationGary Frost AMD Java Labs gary.frost@amd.com
Analyzing Java Performance Using Hardware Performance Counters Gary Frost AMD Java Labs gary.frost@amd.com 2008 by AMD; made available under the EPL v1.0 2 Agenda AMD Java Labs Hardware Performance Counters
More information2
1 2 3 4 5 For Description of these Features see http://download.intel.com/products/processor/corei7/prod_brief.pdf The following Features Greatly affect Performance Monitoring The New Performance Monitoring
More informationAddressing The problem. When & Where do we encounter Data? The concept of addressing data' in computations. The implications for our machine design(s)
Addressing The problem Objectives:- When & Where do we encounter Data? The concept of addressing data' in computations The implications for our machine design(s) Introducing the stack-machine concept Slide
More informationA Study on the Scalability of Hybrid LS-DYNA on Multicore Architectures
11 th International LS-DYNA Users Conference Computing Technology A Study on the Scalability of Hybrid LS-DYNA on Multicore Architectures Yih-Yih Lin Hewlett-Packard Company Abstract In this paper, the
More informationComputer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.
Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.tw Review Computers in mid 50 s Hardware was expensive
More informationDELL. Virtual Desktop Infrastructure Study END-TO-END COMPUTING. Dell Enterprise Solutions Engineering
DELL Virtual Desktop Infrastructure Study END-TO-END COMPUTING Dell Enterprise Solutions Engineering 1 THIS WHITE PAPER IS FOR INFORMATIONAL PURPOSES ONLY, AND MAY CONTAIN TYPOGRAPHICAL ERRORS AND TECHNICAL
More informationSeveral tips on how to choose a suitable computer
Several tips on how to choose a suitable computer This document provides more specific information on how to choose a computer that will be suitable for scanning and postprocessing of your data with Artec
More informationAbstract: Motivation: Description of proposal:
Efficient power utilization of a cluster using scheduler queues Kalyana Chadalvada, Shivaraj Nidoni, Toby Sebastian HPCC, Global Solutions Engineering Bangalore Development Centre, DELL Inc. {kalyana_chadalavada;shivaraj_nidoni;toby_sebastian}@dell.com
More informationMAQAO Performance Analysis and Optimization Tool
MAQAO Performance Analysis and Optimization Tool Andres S. CHARIF-RUBIAL andres.charif@uvsq.fr Performance Evaluation Team, University of Versailles S-Q-Y http://www.maqao.org VI-HPS 18 th Grenoble 18/22
More informationSystem Structures. Services Interface Structure
System Structures Services Interface Structure Operating system services (1) Operating system services (2) Functions that are helpful to the user User interface Command line interpreter Batch interface
More informationPerformance Analysis of Dual Core, Core 2 Duo and Core i3 Intel Processor
Performance Analysis of Dual Core, Core 2 Duo and Core i3 Intel Processor Taiwo O. Ojeyinka Department of Computer Science, Adekunle Ajasin University, Akungba-Akoko Ondo State, Nigeria. Olusola Olajide
More informationChapter 1 Computer System Overview
Operating Systems: Internals and Design Principles Chapter 1 Computer System Overview Eighth Edition By William Stallings Operating System Exploits the hardware resources of one or more processors Provides
More informationWeek 1 out-of-class notes, discussions and sample problems
Week 1 out-of-class notes, discussions and sample problems Although we will primarily concentrate on RISC processors as found in some desktop/laptop computers, here we take a look at the varying types
More informationOracle Database Scalability in VMware ESX VMware ESX 3.5
Performance Study Oracle Database Scalability in VMware ESX VMware ESX 3.5 Database applications running on individual physical servers represent a large consolidation opportunity. However enterprises
More informationSequential Performance Analysis with Callgrind and KCachegrind
Sequential Performance Analysis with Callgrind and KCachegrind 4 th Parallel Tools Workshop, HLRS, Stuttgart, September 7/8, 2010 Josef Weidendorfer Lehrstuhl für Rechnertechnik und Rechnerorganisation
More informationA Performance Monitor based on Virtual Global Time for Clusters of PCs
A Performance Monitor based on Virtual Global Time for Clusters of PCs Michela Taufer Scripps Institute & UCSD Dept. of CS San Diego, USA Thomas Stricker Cluster 2003, 12/2/2003 Hong Kong, SAR, China Lab.
More informationOperating Systems. 05. Threads. Paul Krzyzanowski. Rutgers University. Spring 2015
Operating Systems 05. Threads Paul Krzyzanowski Rutgers University Spring 2015 February 9, 2015 2014-2015 Paul Krzyzanowski 1 Thread of execution Single sequence of instructions Pointed to by the program
More informationOn Benchmarking Popular File Systems
On Benchmarking Popular File Systems Matti Vanninen James Z. Wang Department of Computer Science Clemson University, Clemson, SC 2963 Emails: {mvannin, jzwang}@cs.clemson.edu Abstract In recent years,
More informationORACLE VIRTUAL DESKTOP INFRASTRUCTURE
ORACLE VIRTUAL DESKTOP INFRASTRUCTURE HIGHLY SECURE AND MOBILE ACCESS TO VIRTUALIZED DESKTOP ENVIRONMENTS KEY FEATURES Centralized virtual desktop management and hosting Facilitates access to VDI desktops
More informationANDROID DEVELOPER TOOLS TRAINING GTC 2014. Sébastien Dominé, NVIDIA
ANDROID DEVELOPER TOOLS TRAINING GTC 2014 Sébastien Dominé, NVIDIA AGENDA NVIDIA Developer Tools Introduction Multi-core CPU tools Graphics Developer Tools Compute Developer Tools NVIDIA Developer Tools
More informationAnalysis of VDI Storage Performance During Bootstorm
Analysis of VDI Storage Performance During Bootstorm Introduction Virtual desktops are gaining popularity as a more cost effective and more easily serviceable solution. The most resource-dependent process
More informationDelivering Quality in Software Performance and Scalability Testing
Delivering Quality in Software Performance and Scalability Testing Abstract Khun Ban, Robert Scott, Kingsum Chow, and Huijun Yan Software and Services Group, Intel Corporation {khun.ban, robert.l.scott,
More informationEmbedded Software Development
Linköpings Tekniska Högskola Institutionen för Datavetanskap (IDA), Software and Systems (SaS) TDDI11, Embedded Software 2010-04-22 Embedded Software Development Host and Target Machine Typical embedded
More informationfarmerswife Contents Hourline Display Lists 1.1 Server Application 1.2 Client Application farmerswife.com
Contents 2 1 System requirements 2 1.1 Server Application 3 1.2 Client Application.com 1 1 Ensure that the computers on which you are going to install the Server and Client applications meet the system
More information64-Bit versus 32-Bit CPUs in Scientific Computing
64-Bit versus 32-Bit CPUs in Scientific Computing Axel Kohlmeyer Lehrstuhl für Theoretische Chemie Ruhr-Universität Bochum March 2004 1/25 Outline 64-Bit and 32-Bit CPU Examples
More informationPerformance brief for IBM WebSphere Application Server 7.0 with VMware ESX 4.0 on HP ProLiant DL380 G6 server
Performance brief for IBM WebSphere Application Server.0 with VMware ESX.0 on HP ProLiant DL0 G server Table of contents Executive summary... WebSphere test configuration... Server information... WebSphere
More informationNon-Volatile Memory Programming on the Agilent 3070
Non-Volatile Memory Programming on the Agilent 3070 Paul Montgomery Agilent Technologies Cleveland, Ohio paul_montgomery@agilent.com BACKGROUND The trend in non-volatile memory, like the general trend
More informationCompiler-Assisted Binary Parsing
Compiler-Assisted Binary Parsing Tugrul Ince tugrul@cs.umd.edu PD Week 2012 26 27 March 2012 Parsing Binary Files Binary analysis is common for o Performance modeling o Computer security o Maintenance
More informationPipelining Review and Its Limitations
Pipelining Review and Its Limitations Yuri Baida yuri.baida@gmail.com yuriy.v.baida@intel.com October 16, 2010 Moscow Institute of Physics and Technology Agenda Review Instruction set architecture Basic
More informationAn Oracle White Paper August 2012. Oracle WebCenter Content 11gR1 Performance Testing Results
An Oracle White Paper August 2012 Oracle WebCenter Content 11gR1 Performance Testing Results Introduction... 2 Oracle WebCenter Content Architecture... 2 High Volume Content & Imaging Application Characteristics...
More informationDIABLO TECHNOLOGIES MEMORY CHANNEL STORAGE AND VMWARE VIRTUAL SAN : VDI ACCELERATION
DIABLO TECHNOLOGIES MEMORY CHANNEL STORAGE AND VMWARE VIRTUAL SAN : VDI ACCELERATION A DIABLO WHITE PAPER AUGUST 2014 Ricky Trigalo Director of Business Development Virtualization, Diablo Technologies
More informationCS:APP Chapter 4 Computer Architecture. Wrap-Up. William J. Taffe Plymouth State University. using the slides of
CS:APP Chapter 4 Computer Architecture Wrap-Up William J. Taffe Plymouth State University using the slides of Randal E. Bryant Carnegie Mellon University Overview Wrap-Up of PIPE Design Performance analysis
More informationScaling to Millions of Simultaneous Connections
Scaling to Millions of Simultaneous Connections Rick Reed WhatsApp Erlang Factory SF March 30, 2012 1 About... Joined WhatsApp in 2011 New to Erlang Background in performance of C-based systems on FreeBSD
More information