Implementations of CNN-based image processing and adaptive optic system on FPGA
|
|
- Marvin Sparks
- 8 years ago
- Views:
Transcription
1 Implementations of CNN-based image processing and adaptive optic system on FPGA Ph.D. Theses Zoltán Kincses Supervisor: Péter Szolgay (DSc) University of Pannonia Doctoral School of Information Science and Technology Veszprém 2012
2 1. Introduction, problem statement The CNN (Cellular Neural Array) consists of a rectangular array of fully equivalent analogue processing elements, so-called cells. Cells can only communicate with their neighbors (3x3, 5x5, 7x7) using programmable connections. The strength of the synaptic connections is defined by the weighting factors (templates), which essentially define the program of the CNN structure. Two groups of the templates can be distinguished: linear and nonlinear templates. Linear templates contain only constant values. Nonlinear templates are nonlinear functions of some parameters of the actual cell (input, output, state) or some parameters of the actual and neighboring cell (difference). Therefore, in case of linear templates, the state, the input or the output of the cell should be weighted with the actual template value. However, in case of nonlinear templates, nonlinear template values defined by the nonlinearity are the weighted values of the state, the input or the output of the actual cell. Basically, four implementations of the CNN were developed. These are the analog VLSI (Very Large Scale Integration), the emulated digital VLSI, the optical implementations, and the software simulation. Analog VLSI implementations (Ace400, Ace4K, Ace16k, Xenon, Eye-Ris) have the highest computational speed (8-9 TerraOP), but their accuracy is relatively low and these devices are very sensitive to the small fluctuations of supply voltage and temperature, and only linear templates can be used. In emulated digital VLSI implementations, the ASIC (Application Specific Integrated Circuits) (for example: CASTLE processor) and the FPGA (Field Programmable Gate Array) (for example: FALCON) based implementations can be distinguished. These implementations are slower than the analogue ones, but they are more flexible, easily configurable, they have a shorter design cycle time, they are surface optimized (low dissipated performance), and they are suitable for digital platforms. Optical implementations (for example: POAC, Programmable Optical Array Computer) support extremely high speed and high resolution image processing, realizing the feedback is complicated, it requires a large silicon area, and only linear templates can be used. Software simulation (for example: SimCNN, MatCNN) is the simplest, most flexible implementation of the CNN, in which floating point calculation and 1
3 nonlinear templates can be used, but it is very slow when using the commercially available 2-, 3-, or 4-core desktop computers, even in case of optimized program codes (Intel Core i5, AMD Phenom X2- X4). In the era of software simulation, multiprocessor array computers, which give a much faster solution than the processors used in desktop computers, are increasingly coming to the front. Such a processor is for example the Cell Broadband Engine (CBEA, shortly Cell), which was designed for the Sony PlayStation 3 by the collaboration of IBM, Sony and Toshiba. This array processor consists of one 64 bit PowerPC and eight 128 bit SIMD (Single Instruction Multiple Data) instruction set RISC (Reduced Instruction Set Computing) cores. The IBM Blade Center QS20 system contains two Cell processors communicating via a high bandwidth interface, and its maximal computing performance is 400 GFLOPS (Floatingpoint Operation Per Second). In one Blade center house, seven QS20s can be connected. With this configuration, a 2.8 TFOLPS computational performance can be achieved. Using the newest generations of IBM Blade Center, QS22 blades, a 6.4 TFLOPS single and 3 TFLOPS double precision computing speed can be reached. In the field of the spatiotemporal effects of physics/chemistry, problems where the relationship between the output, input and state variables are nonlinear have a high importance. Such problems are the Euler or Navier-Stokes partial differential equations, which describe non-viscid or viscid fluid flows. Although several studies proved the effectiveness of the application of the CNN to solve partial differential equations, nonlinear templates should be used to solve problems mentioned above. In addition, there are several problems in the field of image processing too, where nonlinear templates should be used in the CNN-based solution. Such problems are the Median-filter, or the computation of the Sum of Absolute Differences (SAD), which is used in the block based motion estimation to determine the optimal fit of the actual and reference image. For the CNN-based solution of both tasks, 3x3 nonlinear D-type templates are required (the relation of the input and the state is nonlinear). However, the present analog/hybrid CNN implementations do not support nonlinear templates. One possible way to be able to handle nonlinear templates 2
4 is extending the capabilities of the emulated digital FALCON processor. I intend to investigate the possibility of the CNN-based solution of nonlinear partial differential equations and the possibility to implement different image processing tasks such as SAD operator using FPGA. This issue is important because the SAD operator is not only usable in the field of block based motion estimation, but it can also be used in one of the most important part of the AO (Adaptive Optic) system, namely in the FPGA based HS (Hartmann-Shack) wavefront sensor. The wavefront of the incoming light distorted by the rapidly changing turbulent media can be dynamically compensated by the AO systems using deformable mirrors (Micro- Electro-Mechanical Systems (MEMs)) or other actuator devices. Wavefront distortion data is measured by the wavefront sensor. The performance of an image processing system can be drastically increased by using an AO system. 3
5 2. Performed investigations, employed methods I studied the CNN Template Library v3.1, and I gave a classification of the nonlinear templates. Using this classification, I investigated the existing FALCON emulated digital CNN-UM implementation, and extended its capabilities to handle two types of nonlinearity. I optimized the area requirement and investigated the performance of the new architecture in case of different computational precisions, and compared it to the original architecture. I used a C-based high level hardware description language called Handle-C, and the Celoxica DK Design Suite development platform to implement the architecture. I implemented the architecture on an RC-203 development board which contains a Xilinx Virtex-II 3000 FPGA designed by the Celoxica. Further on, I implemented the architecture using the VHDL (Very High Speed Integrated Circuit Hardware Description Language) hardware description language in the Xilinx Foundation ISE (Integrated Software Environment) development platform, and tested it using the ModelSim VHDL simulator. I also tested the area requirement and computational performance of this VHDL-based architecture, using some models of the Xilinx Virtex FPGA family (Virtex-6 and Virtex-7). These investigations were required because there are architectural differences in this family (6 input LUT since the Virtex- 5 family), and I investigated the effects of these modifications to the area and performance parameters of the architecture. Area requirement and computational performance of the architectures are carried out by using the Xilinx Foundation ISE tools. In the second half of my research, I dealt with the implementation of an FPGA-based HS wavefront sensor. A compact FPGA-based adaptive optic system was developed in MTA- SZTAKI, which can be seen in Figure 1. The system has three main parts: a high speed CMOS (Complementary Metal-Oxide Semiconductor) sensor, a very high speed LCOS (Liquid Crystal on Silicon) display, and an FPGA, which is responsible for controlling and computing tasks. 4
6 Philips LCOS display Xilinx Spartan-3 FPGA Cypress USB controller Lenslet Micron CMOS sensor Samsung memories Figure 1. Structure of the compact adaptive optic system Distortions of the wavefront of the incoming light is sensed by the CMOS sensor and the FPGA (HS wavefront sensor). Based on these data, the required corrections are computed by the FPGA and are finally displayed by the LCOS display, removing the distortions of the wavefront of the incoming light. I used the SAD operator to implement the FPGA-based wavefront sensor. I designed a nonlinear template which realizes the SAD operator, and implemented it on a nonlinear template runner emulated digital CNN-UM as a wavefront sensor. I optimized the area requirement of this architecture, and investigated its maximal reachable computation performance in case of different size of SAD operators. To improve the performance of the architecture, the special hardware requirement of the adaptive optic board was taken into account. Since the performance of the architecture was below the expectations, I redesigned the architecture and implemented a high-speed architecture which was specialized for this task. Area requirement and computational performance of this architecture was also tested, and compared to other similar systems. The emulated digital CNN-UM-based and the specialized wavefront sensor architecture was designed using the VHDL hardware description language. The ModelSim VHDL simulator and the Xilinx Foundation ISE tool were used during testing and implementation. Although I conducted my investigations using a Xilinx development environment, the VHDL description of the architecture is universal. 5
7 3. New scientific results 1. Thesis group: Implementation of nonlinear template runner emulated digital CNN-UM on FPGA Using present CNN implementations except for the slow software simulation there are no possibilities to use nonlinear templates. In case of some tasks which can be solved by a CNN (for example: gradient intensity estimation, grayscale contour detection), this inadequacy can be eliminated, because nonlinear B templates can be decomposed into a series of linear templates. Naturally, this substitution is more complicated than applying one nonlinear template, even if the result is the same. However, template decomposition cannot be used in case of several tasks (median filter, the previously mentioned SAD operator, grayscale erosion/dilation, histogram generation), where nonlinear A or D-type templates should be applied. Therefore, the only way to solve these tasks is the application of nonlinear templates. In the course of studying the CNN Template Library v3.1, I classified the nonlinear templates based on the nonlinearity defined by the nonlinear template values into two groups. These are the zero- and first-order nonlinear templates. A template is called a zeroorder nonlinear template if the nonlinear function of the template only contains constant sections. A template is called a first-order nonlinear template if the nonlinear function of the template contains first-order linear functions of the variables. I extended the FALCON emulated digital CNN-UM architecture to handle zero- and first-order nonlinear templates taking into account their special requirements. I measured the area requirement and computational speed of these architectures and compared them to the results of the original linear FALCON architecture and the software simulation (MatCNN, Intel Core i5 M GHz). My investigations show that the computational performance of the zeroand first-order FALCON processor is significantly higher than the performance of the software simulation. 6
8 1.1. Implementation of the zero-order nonlinear template runner emulated digital CNN-UM architecture on FPGA I gave the extension of the FALCON emulated digital CNN- UM for the application of zero-order nonlinear templates. I redesigned the template-handling part of the FALCON processor, to make it able to store the constant values of the sections of the zeroorder nonlinearity, and based on these values, to determine the nonlinear template values. I analyzed the area requirement and computating performance of the extended architecture in case of different FPGA families (Virtex-II, Virtex-4, Virtex-6, Virtex-7). I showed that in case of Virtex-6 XC6VS475T and Virtex-7 XC7VX9800T type FPGAs, 168 processors can be implemented on Virtex-6 and 300 processors can be implemented on Virtex-7 independently from the bit width of the state value. I showed that the maximal computational performance is million celliterations/second when implementing a 168 zero-order FALCON processor on Virtex-6 FPGA using 18 bit state width, and the Virtex- 7 FPGA is almost 2-times (1.786) faster. Compared these results to the software simulation, where the maximal computational performance is 13 million celliterations/second, the performance is increased by 3 orders of magnitude Implementation of first-order nonlinear template runner emulated digital CNN-UM architecture on FPGA I gave the extension of the FALCON emulated digital CNN- UM for the application of first-order nonlinear templates. In this case, the template memory of the FALCON processor is also extended with the appropriate adder and multiplier circuits to be able to determine the nonlinear template values. I analyzed the area requirement and computing speed of the extended architecture in case of different FPGA families (Virtex-II, Virtex-4, Virtex-6, Virtex-7). I showed that in case of Virtex-6 XC6VSX475T and Virtex-7 XC7VX9800T type FPGAs, first-order FALCON processors can be implemented on Virtex-6 and first-order FALCON processors can be implemented on Virtex-7, depending on the bit width of the state value. I showed that the maximal computational 7
9 performance is million celliterations/second when implementing 112 first-order FALCON processors using 18 bit state width on Virtex-6 FPGA, while the Virtex-7 FPGA is almost 2-times (1.786) faster. In this case, both FPGAs offer 3 orders of magnitude higher performance compared to the software simulation where the maximal computing speed is 9 million celliterations/second. 2. Thesis group: Implementing a SAD operator-based wavefront sensor architecture on an FPGA-based adaptive optic system. AO systems have a great importance in the field of astronomy. However, it is also becoming increasingly important in the field of military and medicine (ophthalmology). Therefore, these systems can be applied in fields where the goal is creating pictures with high exposition time and high resolution. The rapidly changing turbulent media can modify or distort the wavefront (the wavefront is a line or surface of the points which are in the same phase) of the incoming light. The performance of the imaging system is significantly deteriorated by this phenomenon. The goal of the adaptive optic system is to eliminate the distortions of the wavefront. The adaptive optic system is built up of two main components, the adaptive mirror and the wavefront sensor. Distortions of the wavefront are continuously measured by the wavefront sensor. Based on these measurements, the control system can modify the surface of the adaptive mirror continuously, to compensate the distortions of the wavefront. The HS wavefront sensor, which is frequently applied in adaptive optic systems, is basically built up of two parts, the lenslet array and the CCD (Charge-Coupled Device) or CMOS sensor. In a HS sensor, the image of the incoming pupil is projected on a lenslet array. Each lens of the array forms a miniature image of the source object and divides the incoming aperture into sub-apertures. The images of these sub-apertures are detected by the CCD or CMOS sensor. The shifts of these images from the reference positions (positions without aberrations) specify the local wavefront slopes at the locations of the corresponding sub-apertures (the wavefront is regarded locally flat but tilted). The overall shape of the wavefront extended for the whole pupil can be reconstructed by assembling all these local tilted surfaces with the adaptive optic system. 8
10 For a point source object (such as a star), simple quad-cell based HS sensors can measure these shifts. However, in the case of extended objects (the Sun or the Moon), these shifts can be determined only with a higher resolution sensor from the correlations between the sub-aperture images and the reference sub-aperture images. In this case, a higher computational speed is required, moreover, correcting ability of the adaptive optic system is better if the delay between sensing the wavefront and correction is smaller than the evolution time of the medium being corrected for. To eliminate these problems, a novel FPGA-based compact adaptive optic system was developed in MTA-SZTAKI (Figure 1). My task was to implement the wavefront sensor part of this system. Considering the limitation of the FPGA devices and the special parameterization of the mandatory wavefront sensors, the Sum of Absolute Differences (SAD) method was chosen to implement the required correlation-like processing. First, the SAD values of the picture are calculated, and the minimum of them is determined. With this method, the displacement of the images of all sub-apertures is determined with respect to a reference image Nonlinear template runner emulated digital CNN-UM as SAD-based wavefront sensor architecture. I gave the implementation of the SAD operator-based wavefront sensor on the FALCON architecture extended with nonlinear templates, and I investigated the effectiveness of this architecture. I showed that the general and dedicated resource requirement of the SAD operator runner FALCON processor is essentially the same as the original first-order FALCON processor. It only requires one additional BlockRAM. I showed that using the Spartan-3 XC3S4000 FPGA on the adaptive optic card, the number of implementable extended FALCON processors is 8. Using all these processors, a 320 million celliterations/second computing performance can be reached in case of 3x3 pixels sub-apertures and 5x5 pixels reference image. I showed that when the sub-aperture size is increased to 16x16 (commonly used in real applications), only 3 extended FALCON processors can be implemented, and the maximal computing performance is 120 million celliterations/second. In order to improve 9
11 the computational performance of the architecture and to suit the requirement of the adaptive optic board, I redesigned the architecture to create a high speed special purpose architecture Optimal implementation of SAD operator based wavefront sensor on FPGA-based adaptive optic card. I gave the optimized FPGA-based implementation of the SAD operator-based wavefront sensor architecture. I analyzed the area requirement and computational speed of the architecture in case of different kinds of FPGA families (Virtex-II, Virtex-4, Virtex- 6, Virtex-7). I showed that the general and dedicated resource requirement of the SAD unit, which is the central part of the wavefront sensor, is increasing quadratically according to the size of the sub-apertures. I showed that in case of Spartan-3 XC3S4000 FPGA using one 120MHz SAD unit x8 pixels and x32 pixels sized subapertures can be processed in real time. I showed that using the significantly larger Virtex-7 XC7V2000T FPGA, where the clock frequency of the SAD unit can reach the 300Mhz, the whole CMOS surface can be processed in real time. I showed that in case of 8x8 pixels and 16x16 pixel sized sub-apertures, the AT (Area Time) parameter of my system is 29%, and 22% better respectively than the traditional correlation-based system. Compared to other SAD based architectures, my architecture shows superior performance (in case of 16x16 pixels sub-aperture: slice and 496 clock cycles facing 9478 slice and 1600 clock cycles). 10
12 4. Application of the new experimental results i) Using the nonlinear template runner emulated digital FALCON architecture, it is possible to solve partial differential equations which describe processes with different spatiotemporal dynamics. The extended FALCON processor is able to solve PDEs, which describe viscid and non-viscid fluid flow at least 3 orders of magnitude faster than software simulation. In addition, the processor can be parametrized arbitrarily according to the problem needed to be solved. Since the extended FALOCN processor was implemented using VHDL hardware description language, the architecture can be implemented on arbitrary Xilinx FPGAs. In the field of image processing, the basic part of the digital video compression is motion estimation. One implementation method is the block-based motion estimation, where the optimal fit of the two images should be determined. For example, using the SAD operator this optimal fitting position can be determined. The SAD operator can be calculated by using my nonlinear template runner emulated digital FALCON processor. Not only the SAD operator, but different nonlinear templates can also be implemented, for example the Median-filter or Erosion/Dilation templates. ii) In astronomy, the observation of extended objects such as the Sun with large telescopes requires high resolution correlation based HS sensors to measure the distortions of the wavefront of the incoming light wave. The variations of the wavefront follow the variations of the atmosphere. In the visible region of the wavelength, these variations are millisecond length. The implemented wavefront sensor needs to follow these variations. The FPGA-based AO system developed in MTA-SZTAKI contains the required high resolution HS sensor and can compensate distortions in real time. Thanks to this the system well applicable in the field of astronomical observation of extended objects (Figure 2.). The turbulent nature of the atmosphere also deteriorates the performance of the remote control of satellites, so the system can also be applied in this field. 11
13 Figure 2. The AO system in astrology High performance telescopes are also used in the military applications, for different monitoring tasks. In case of these telescopes, similarly to the telescopes in astrology, the distortion of the wavefront of the incoming light wave also causes problem, which deteriorate the resolution of the telescopes. In order to improve the resolution of these telescopes, this AO system can also be used. In the field of medical imaging in ophthalmology, the pictures of the retina of the living human is also deteriorated by the imperfect human eyepiece. The distortions are caused by the eyepiece can also be eliminated by the help of the AO system. (Figure 3.). Figure 3. The AO system in the ophthalmology 12
14 In microscopy, the aberrations generated by the sample on the object table can also be eliminated by the proposed AO system (Figure 4.). Figure 4. Adaptive optics in microscopy 13
15 5. List of publications Journal papers: Z. Nagy, L. Kék, Z. Kincses, A. Kiss, P. Szolgay: Toward Exploitation of Cell Multi-processor Array in Time-Consuming Applications by Using CNN Model (International Journal of Circuit Theory and Applications, Wiley, Vol. 36., Special Issue: Cellular Wave Computing Architecture, July-September pp IF: , ISSN: ) Z. Kincses, L. Orzó, Z. Nagy, Gy, Mező, P. Szolgay: High-speed, SAD based wavefront sensor architecture implementation on FPGA (Journal of Signal Processing Systems, Springer, DOI: /s , 2011, IF: , Vol. 63, pp , ISSN: ) International conference papers: Z. Kincses, Z. Nagy, P. Szolgay: "Implementation of nonlinear template runner emulated digital CNN-UM on FPGA" (CNNA 2006, Turkey, Istambul, August 28-30) Z. Nagy, L. Kék, Z. Kincses, P. Szolgay: "CNN model on Cell multiprocessor array" (ECCTD 2007, Spain, Sevilla, August ) Z. Nagy, L. Kék, Z. Kincses, A. Kiss, P. Szolgay: "Toward Exploitation of Cell Multi-processor Array in Time-Consuming Applications by Using CNN Model" (CNNA 2008, Spain, Santiago de Compostela, July ). Z. Kincses, Z. Nagy, L. Orzó, P. Szolgay, Gy. Mező: "Implementation of a parallel SAD based wavefront sensor architecture on FPGA" (ECCTD 2009, Turkey, Antalya, August ) 14
16 Z. Kincses, Zs. Vörösházi, Z. Nagy, P. Szolgay, P. Szolgay, T. Laviniu, A. Gacsádi: Investigation of area and speed trade-offs in FPGA implementation of an image correlation algorithm (CNNA 2012, Turin, Italy, August ) Hungarian conference papers: Z. Kincses (2009): "High-speed, SAD based wavefront sensor architecture implementation on FPGA", Proceedings of the 7th PhD Mini-Symposium, University of Pannonia, Veszprém Kincses Z. (2008), "Toward Exploitation of Cell Multi-processor Array in Time-Consuming Applications by Using CNN Model", Proceedings of the 6th PhD Mini-Symposium, University of Pannonia, Veszprém Kincses Z. (2007), "CNN model on Cell multiprocessor array", Proceedings of the 5th PhD Mini-Symposium, University of Pannonia, Veszprém 15
Implementation of emulated digital CNN-UM architecture on programmable logic devices and its applications
Implementation of emulated digital CNN-UM architecture on programmable logic devices and its applications Theses of the Ph.D. dissertation Zoltán Nagy Scientific adviser: Dr. Péter Szolgay Doctoral School
More informationInvestigation of emulated-digital CNN-UM architectures: Retina model and Cellular Wave-Computing Architecture implementation on FPGA
University of Pannonia Information Science and Technology Doctoral School Investigation of emulated-digital CNN-UM architectures: Retina model and Cellular Wave-Computing Architecture implementation on
More informationAnalogic Computers Ltd. CNN Technology. - introduction, tools and application examples-
CNN Technology - introduction, tools and application examples- Outline Introduction to CNN Array structure and the analog core cell CNN Universal Machine CNN implementations Analog mixed-signal VLSI Emulated
More informationSEISMIC WAVE PROPAGATION MODELLING ON EMULATED DIGITAL CNN-UM ARCHITECTURE
PERIODICA POLYTECHNICA SER. EL. ENG. VOL. 49, NO. 3 4, PP. 183 193 (005) SEISMIC WAVE PROPAGATION MODELLING ON EMULATED DIGITAL CNN-UM ARCHITECTURE Péter KOZMA 1, Zoltán NAGY 1 and Péter SZOLGAY 1, 1 Department
More informationA Computer Vision System on a Chip: a case study from the automotive domain
A Computer Vision System on a Chip: a case study from the automotive domain Gideon P. Stein Elchanan Rushinek Gaby Hayun Amnon Shashua Mobileye Vision Technologies Ltd. Hebrew University Jerusalem, Israel
More informationImplementation of Canny Edge Detector of color images on CELL/B.E. Architecture.
Implementation of Canny Edge Detector of color images on CELL/B.E. Architecture. Chirag Gupta,Sumod Mohan K cgupta@clemson.edu, sumodm@clemson.edu Abstract In this project we propose a method to improve
More informationModelling, Extraction and Description of Intrinsic Cues of High Resolution Satellite Images: Independent Component Analysis based approaches
Modelling, Extraction and Description of Intrinsic Cues of High Resolution Satellite Images: Independent Component Analysis based approaches PhD Thesis by Payam Birjandi Director: Prof. Mihai Datcu Problematic
More informationChapter 6 Telescopes: Portals of Discovery. How does your eye form an image? Refraction. Example: Refraction at Sunset.
Chapter 6 Telescopes: Portals of Discovery 6.1 Eyes and Cameras: Everyday Light Sensors Our goals for learning:! How does your eye form an image?! How do we record images? How does your eye form an image?
More informationVideo-Rate Stereo Vision on a Reconfigurable Hardware. Ahmad Darabiha Department of Electrical and Computer Engineering University of Toronto
Video-Rate Stereo Vision on a Reconfigurable Hardware Ahmad Darabiha Department of Electrical and Computer Engineering University of Toronto Introduction What is Stereo Vision? The ability of finding the
More informationDevelopment of a high-resolution, high-speed vision system using CMOS image sensor technology enhanced by intelligent pixel selection technique
Development of a high-resolution, high-speed vision system using CMOS image sensor technology enhanced by intelligent pixel selection technique Kenji Tajima *a, Akihiko Numata a, Idaku Ishii b a Photron
More informationAdaptive Optics Testbed for the Visible High Resolution Imaging
Adaptive Optics Testbed for the Visible High Resolution Imaging Young Soo Choi*, Jae Eun Yoo, Seung Soo Kim Agency for Defense Development, Yuseung P.O Box 35-3, Daejeon, 305-600, Republic of Korea Won
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationLesson 7: SYSTEM-ON. SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY. Chapter-1L07: "Embedded Systems - ", Raj Kamal, Publs.: McGraw-Hill Education
Lesson 7: SYSTEM-ON ON-CHIP (SoC( SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY 1 VLSI chip Integration of high-level components Possess gate-level sophistication in circuits above that of the counter,
More informationDesign Cycle for Microprocessors
Cycle for Microprocessors Raúl Martínez Intel Barcelona Research Center Cursos de Verano 2010 UCLM Intel Corporation, 2010 Agenda Introduction plan Architecture Microarchitecture Logic Silicon ramp Types
More informationHardware-Aware Analysis and. Presentation Date: Sep 15 th 2009 Chrissie C. Cui
Hardware-Aware Analysis and Optimization of Stable Fluids Presentation Date: Sep 15 th 2009 Chrissie C. Cui Outline Introduction Highlights Flop and Bandwidth Analysis Mehrstellen Schemes Advection Caching
More informationA General Framework for Tracking Objects in a Multi-Camera Environment
A General Framework for Tracking Objects in a Multi-Camera Environment Karlene Nguyen, Gavin Yeung, Soheil Ghiasi, Majid Sarrafzadeh {karlene, gavin, soheil, majid}@cs.ucla.edu Abstract We present a framework
More informationNEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.
CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache
More informationSoC Curricula at Tallinn Technical University
SoC Curricula at Tallinn Technical University Margus Kruus, Kalle Tammemäe, Peeter Ellervee Tallinn Technical University Phone: +372-6202250, Fax: +372-6202246 kruus@cc.ttu.ee nalle@cc.ttu.ee lrv@cc.ttu.ee
More informationA+ Guide to Managing and Maintaining Your PC, 7e. Chapter 1 Introducing Hardware
A+ Guide to Managing and Maintaining Your PC, 7e Chapter 1 Introducing Hardware Objectives Learn that a computer requires both hardware and software to work Learn about the many different hardware components
More informationAN IMPROVED DESIGN OF REVERSIBLE BINARY TO BINARY CODED DECIMAL CONVERTER FOR BINARY CODED DECIMAL MULTIPLICATION
American Journal of Applied Sciences 11 (1): 69-73, 2014 ISSN: 1546-9239 2014 Science Publication doi:10.3844/ajassp.2014.69.73 Published Online 11 (1) 2014 (http://www.thescipub.com/ajas.toc) AN IMPROVED
More informationVarious Technics of Liquids and Solids Level Measurements. (Part 3)
(Part 3) In part one of this series of articles, level measurement using a floating system was discusses and the instruments were recommended for each application. In the second part of these articles,
More informationImage processing in the military technology
AARMS Vol. 2, No. 2 (2003) 221 231 INFORMATICS ROBOTICS Image processing in the military technology TIBOR BUZÁSI Ministry of Defence, Technology Agency, Budapest, Hungary At the Ministry of Defence, Technology
More informationCancellation of Load-Regulation in Low Drop-Out Regulators
Cancellation of Load-Regulation in Low Drop-Out Regulators Rajeev K. Dokania, Student Member, IEE and Gabriel A. Rincόn-Mora, Senior Member, IEEE Georgia Tech Analog Consortium Georgia Institute of Technology
More informationChoosing a digital camera for your microscope John C. Russ, Materials Science and Engineering Dept., North Carolina State Univ.
Choosing a digital camera for your microscope John C. Russ, Materials Science and Engineering Dept., North Carolina State Univ., Raleigh, NC One vital step is to choose a transfer lens matched to your
More informationImplementation of Modified Booth Algorithm (Radix 4) and its Comparison with Booth Algorithm (Radix-2)
Advance in Electronic and Electric Engineering. ISSN 2231-1297, Volume 3, Number 6 (2013), pp. 683-690 Research India Publications http://www.ripublication.com/aeee.htm Implementation of Modified Booth
More informationReconfigurable System-on-Chip Design
Reconfigurable System-on-Chip Design MITCHELL MYJAK Senior Research Engineer Pacific Northwest National Laboratory PNNL-SA-93202 31 January 2013 1 About Me Biography BSEE, University of Portland, 2002
More informationDEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS
DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS U. Pogliano, B. Trinchera, G.C. Bosco and D. Serazio INRIM Istituto Nazionale di Ricerca Metrologica Torino (Italia)
More informationInternational Journal of Electronics and Computer Science Engineering 1482
International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant
More informationForce measurement. Forces VECTORIAL ISSUES ACTION ET RÉACTION ISOSTATISM
Force measurement Forces VECTORIAL ISSUES In classical mechanics, a force is defined as "an action capable of modifying the quantity of movement of a material point". Therefore, a force has the attributes
More informationLMS is a simple but powerful algorithm and can be implemented to take advantage of the Lattice FPGA architecture.
February 2012 Introduction Reference Design RD1031 Adaptive algorithms have become a mainstay in DSP. They are used in wide ranging applications including wireless channel estimation, radar guidance systems,
More informationGlitch Free Frequency Shifting Simplifies Timing Design in Consumer Applications
Glitch Free Frequency Shifting Simplifies Timing Design in Consumer Applications System designers face significant design challenges in developing solutions to meet increasingly stringent performance and
More informationA Scalable Large Format Display Based on Zero Client Processor
International Journal of Electrical and Computer Engineering (IJECE) Vol. 5, No. 4, August 2015, pp. 714~719 ISSN: 2088-8708 714 A Scalable Large Format Display Based on Zero Client Processor Sang Don
More informationİSTANBUL AYDIN UNIVERSITY
İSTANBUL AYDIN UNIVERSITY FACULTY OF ENGİNEERİNG SOFTWARE ENGINEERING THE PROJECT OF THE INSTRUCTION SET COMPUTER ORGANIZATION GÖZDE ARAS B1205.090015 Instructor: Prof. Dr. HASAN HÜSEYİN BALIK DECEMBER
More informationWhitepaper. Image stabilization improving camera usability
Whitepaper Image stabilization improving camera usability Table of contents 1. Introduction 3 2. Vibration Impact on Video Output 3 3. Image Stabilization Techniques 3 3.1 Optical Image Stabilization 3
More information9/14/2011 14.9.2011 8:38
Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer
More informationApplications of algorithms for image processing using programmable logic
Applications of algorithms for image processing using programmable logic Presented by: Nikolay Nenov, M. Sc. Ph. D. Student at the Technical University of Sofia E-mail: nenov@mail.bg Research director:
More informationFPGA Music Project. Matthew R. Guthaus. Department of Computer Engineering, University of California Santa Cruz http://vlsida.soe.ucsc.
Department of Computer Engineering, University of California Santa Cruz http://vlsida.soe.ucsc.edu Biographic Info 2006 PhD, University of Michigan in Electrical Engineering 2003-2005 Statistical Physical
More informationOpto-Mechanical I/F for ANSYS
Abstract Opto-Mechanical I/F for ANSYS Victor Genberg, Keith Doyle, Gregory Michels Sigmadyne, Inc., 803 West Ave, Rochester, NY 14611 genberg@sigmadyne.com Thermal and structural output from ANSYS is
More informationCMOS Binary Full Adder
CMOS Binary Full Adder A Survey of Possible Implementations Group : Eren Turgay Aaron Daniels Michael Bacelieri William Berry - - Table of Contents Key Terminology...- - Introduction...- 3 - Design Architectures...-
More informationSAD computation based on online arithmetic for motion. estimation
SAD computation based on online arithmetic for motion estimation J. Olivares a, J. Hormigo b, J. Villalba b, I. Benavides a and E. L. Zapata b a Dept. of Electrics and Electronics, University of Córdoba,
More informationA Survey of Video Processing with Field Programmable Gate Arrays (FGPA)
A Survey of Video Processing with Field Programmable Gate Arrays (FGPA) Heather Garnell Abstract This paper is a high-level, survey of recent developments in the area of video processing using reconfigurable
More informationLLRF. Digital RF Stabilization System
LLRF Digital RF Stabilization System Many instruments. Many people. Working together. Stability means knowing your machine has innovative solutions. For users, stability means a machine achieving its full
More informationFPGA. AT6000 FPGAs. Application Note AT6000 FPGAs. 3x3 Convolver with Run-Time Reconfigurable Vector Multiplier in Atmel AT6000 FPGAs.
3x3 Convolver with Run-Time Reconfigurable Vector Multiplier in Atmel AT6000 s Introduction Convolution is one of the basic and most common operations in both analog and digital domain signal processing.
More informationAdaptive Optics Phoropters
Adaptive Optics Phoropters Scot S. Olivier Adaptive Optics Group Leader Physics and Advanced Technologies Lawrence Livermore National Laboratory Associate Director NSF Center for Adaptive Optics Adaptive
More informationBasler. Line Scan Cameras
Basler Line Scan Cameras High-quality line scan technology meets a cost-effective GigE interface Real color support in a compact housing size Shading correction compensates for difficult lighting conditions
More informationImplementation and Design of AES S-Box on FPGA
International Journal of Research in Engineering and Science (IJRES) ISSN (Online): 232-9364, ISSN (Print): 232-9356 Volume 3 Issue ǁ Jan. 25 ǁ PP.9-4 Implementation and Design of AES S-Box on FPGA Chandrasekhar
More informationImpedance 50 (75 connectors via adapters)
VECTOR NETWORK ANALYZER PLANAR TR1300/1 DATA SHEET Frequency range: 300 khz to 1.3 GHz Measured parameters: S11, S21 Dynamic range of transmission measurement magnitude: 130 db Measurement time per point:
More informationDIGITAL-TO-ANALOGUE AND ANALOGUE-TO-DIGITAL CONVERSION
DIGITAL-TO-ANALOGUE AND ANALOGUE-TO-DIGITAL CONVERSION Introduction The outputs from sensors and communications receivers are analogue signals that have continuously varying amplitudes. In many systems
More informationDigital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
More informationHardware and Software
Hardware and Software 1 Hardware and Software: A complete design Hardware and software support each other Sometimes it is necessary to shift functions from software to hardware or the other way around
More informationInvestigation of Color Aliasing of High Spatial Frequencies and Edges for Bayer-Pattern Sensors and Foveon X3 Direct Image Sensors
Investigation of Color Aliasing of High Spatial Frequencies and Edges for Bayer-Pattern Sensors and Foveon X3 Direct Image Sensors Rudolph J. Guttosch Foveon, Inc. Santa Clara, CA Abstract The reproduction
More informationFPGA Implementation of Human Behavior Analysis Using Facial Image
RESEARCH ARTICLE OPEN ACCESS FPGA Implementation of Human Behavior Analysis Using Facial Image A.J Ezhil, K. Adalarasu Department of Electronics & Communication Engineering PSNA College of Engineering
More informationGo Faster - Preprocessing Using FPGA, CPU, GPU. Dipl.-Ing. (FH) Bjoern Rudde Image Acquisition Development STEMMER IMAGING
Go Faster - Preprocessing Using FPGA, CPU, GPU Dipl.-Ing. (FH) Bjoern Rudde Image Acquisition Development STEMMER IMAGING WHO ARE STEMMER IMAGING? STEMMER IMAGING is: Europe's leading independent provider
More informationIntroduction to Digital System Design
Introduction to Digital System Design Chapter 1 1 Outline 1. Why Digital? 2. Device Technologies 3. System Representation 4. Abstraction 5. Development Tasks 6. Development Flow Chapter 1 2 1. Why Digital
More informationAccuracy of SpotOptics wavefront sensors. June 2010 Version 4.0
Accuracy of SpotOptics wavefront sensors June Version 4.0 1 1 Basic concepts: accuracy, precision and repeatability Repeatability is not the same as accuracy You can have high repeatability but low accuracy
More informationExtended Resolution TOA Measurement in an IFM Receiver
Extended Resolution TOA Measurement in an IFM Receiver Time of arrival (TOA) measurements define precisely when an RF signal is received, necessary in the identification of type and mode of RF and radar
More informationFraunhofer Institute for Telecommunications
Fraunhofer Institute for Telecommunications Heinrich-Hertz-Institut SCUBE-ICT Emerging Berlin opportunities under FP7-ICT Call 5 Minsk, 25.-26.06.2009 Einsteinufer 37 10587 Berlin Germany Phone: Fax: email:
More informationRefractive Index Measurement Principle
Refractive Index Measurement Principle Refractive index measurement principle Introduction Detection of liquid concentrations by optical means was already known in antiquity. The law of refraction was
More informationdspace DSP DS-1104 based State Observer Design for Position Control of DC Servo Motor
dspace DSP DS-1104 based State Observer Design for Position Control of DC Servo Motor Jaswandi Sawant, Divyesh Ginoya Department of Instrumentation and control, College of Engineering, Pune. ABSTRACT This
More informationNutaq. PicoDigitizer 125-Series 16 or 32 Channels, 125 MSPS, FPGA-Based DAQ Solution PRODUCT SHEET. nutaq.com MONTREAL QUEBEC
Nutaq PicoDigitizer 125-Series 16 or 32 Channels, 125 MSPS, FPGA-Based DAQ Solution PRODUCT SHEET QUEBEC I MONTREAL I N E W YO R K I nutaq.com Nutaq PicoDigitizer 125-Series The PicoDigitizer 125-Series
More informationDigital to Analog Converter. Raghu Tumati
Digital to Analog Converter Raghu Tumati May 11, 2006 Contents 1) Introduction............................... 3 2) DAC types................................... 4 3) DAC Presented.............................
More information7a. System-on-chip design and prototyping platforms
7a. System-on-chip design and prototyping platforms Labros Bisdounis, Ph.D. Department of Computer and Communication Engineering 1 What is System-on-Chip (SoC)? System-on-chip is an integrated circuit
More informationThe infrared camera NEC Thermo tracer TH7102WL (1) (IR
PERIODICUM BIOLOGORUM UDC 57:61 VOL. 108, No 4,????, 2006 CODEN PDBIAD ISSN 0031-5362 Original scientific paper ThermoWEB-Remote Control and Measurement of Temperature over the Web D. KOLARI] K. SKALA
More informationReconfigurable Architecture Requirements for Co-Designed Virtual Machines
Reconfigurable Architecture Requirements for Co-Designed Virtual Machines Kenneth B. Kent University of New Brunswick Faculty of Computer Science Fredericton, New Brunswick, Canada ken@unb.ca Micaela Serra
More informationUsers Manual Model #93711. English
Users Manual Model #93711 English Congratulations on your purchase of the Celestron NexImage 5 Solar System imaging camera. Your NexImage camera comes with the following: + NexImage 5 Camera + 1.25 nose
More informationNetworking Virtualization Using FPGAs
Networking Virtualization Using FPGAs Russell Tessier, Deepak Unnikrishnan, Dong Yin, and Lixin Gao Reconfigurable Computing Group Department of Electrical and Computer Engineering University of Massachusetts,
More informationThe Scientific Data Mining Process
Chapter 4 The Scientific Data Mining Process When I use a word, Humpty Dumpty said, in rather a scornful tone, it means just what I choose it to mean neither more nor less. Lewis Carroll [87, p. 214] In
More informationStep Response of RC Circuits
Step Response of RC Circuits 1. OBJECTIVES...2 2. REFERENCE...2 3. CIRCUITS...2 4. COMPONENTS AND SPECIFICATIONS...3 QUANTITY...3 DESCRIPTION...3 COMMENTS...3 5. DISCUSSION...3 5.1 SOURCE RESISTANCE...3
More informationAdvances in scmos Camera Technology Benefit Bio Research
Advances in scmos Camera Technology Benefit Bio Research scmos camera technology is gaining in popularity - Why? In recent years, cell biology has emphasized live cell dynamics, mechanisms and electrochemical
More informationWhite paper. CCD and CMOS sensor technology Technical white paper
White paper CCD and CMOS sensor technology Technical white paper Table of contents 1. Introduction to image sensors 3 2. CCD technology 4 3. CMOS technology 5 4. HDTV and megapixel sensors 6 5. Main differences
More informationThe Evolution of Computer Graphics. SVP, Content & Technology, NVIDIA
The Evolution of Computer Graphics Tony Tamasi SVP, Content & Technology, NVIDIA Graphics Make great images intricate shapes complex optical effects seamless motion Make them fast invent clever techniques
More informationDigital Systems Design! Lecture 1 - Introduction!!
ECE 3401! Digital Systems Design! Lecture 1 - Introduction!! Course Basics Classes: Tu/Th 11-12:15, ITE 127 Instructor Mohammad Tehranipoor Office hours: T 1-2pm, or upon appointments @ ITE 441 Email:
More informationOptimising the resource utilisation in high-speed network intrusion detection systems.
Optimising the resource utilisation in high-speed network intrusion detection systems. Gerald Tripp www.kent.ac.uk Network intrusion detection Network intrusion detection systems are provided to detect
More informationParallelized Architecture of Multiple Classifiers for Face Detection
Parallelized Architecture of Multiple s for Face Detection Author(s) Name(s) Author Affiliation(s) E-mail Abstract This paper presents a parallelized architecture of multiple classifiers for face detection
More informationAC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD)
AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD) Samuel Lakeou, University of the District of Columbia Samuel Lakeou received a BSEE (1974) and a MSEE (1976)
More informationDESIGN CHALLENGES OF TECHNOLOGY SCALING
DESIGN CHALLENGES OF TECHNOLOGY SCALING IS PROCESS TECHNOLOGY MEETING THE GOALS PREDICTED BY SCALING THEORY? AN ANALYSIS OF MICROPROCESSOR PERFORMANCE, TRANSISTOR DENSITY, AND POWER TRENDS THROUGH SUCCESSIVE
More informationA New, High-Performance, Low-Power, Floating-Point Embedded Processor for Scientific Computing and DSP Applications
1 A New, High-Performance, Low-Power, Floating-Point Embedded Processor for Scientific Computing and DSP Applications Simon McIntosh-Smith Director of Architecture 2 Multi-Threaded Array Processing Architecture
More informationFrom Concept to Production in Secure Voice Communications
From Concept to Production in Secure Voice Communications Earl E. Swartzlander, Jr. Electrical and Computer Engineering Department University of Texas at Austin Austin, TX 78712 Abstract In the 1970s secure
More informationComparing Digital and Analogue X-ray Inspection for BGA, Flip Chip and CSP Analysis
Comparing Digital and Analogue X-ray Inspection for BGA, Flip Chip and CSP Analysis David Bernard & Steve Ainsworth Dage Precision Industries Abstract Non-destructive testing during the manufacture of
More informationHigh-Level Synthesis for FPGA Designs
High-Level Synthesis for FPGA Designs BRINGING BRINGING YOU YOU THE THE NEXT NEXT LEVEL LEVEL IN IN EMBEDDED EMBEDDED DEVELOPMENT DEVELOPMENT Frank de Bont Trainer consultant Cereslaan 10b 5384 VT Heesch
More informationon an system with an infinite number of processors. Calculate the speedup of
1. Amdahl s law Three enhancements with the following speedups are proposed for a new architecture: Speedup1 = 30 Speedup2 = 20 Speedup3 = 10 Only one enhancement is usable at a time. a) If enhancements
More informationMixed Precision Iterative Refinement Methods Energy Efficiency on Hybrid Hardware Platforms
Mixed Precision Iterative Refinement Methods Energy Efficiency on Hybrid Hardware Platforms Björn Rocker Hamburg, June 17th 2010 Engineering Mathematics and Computing Lab (EMCL) KIT University of the State
More informationRF Measurements Using a Modular Digitizer
RF Measurements Using a Modular Digitizer Modern modular digitizers, like the Spectrum M4i series PCIe digitizers, offer greater bandwidth and higher resolution at any given bandwidth than ever before.
More informationMECE 102 Mechatronics Engineering Orientation
MECE 102 Mechatronics Engineering Orientation Mechatronic System Components Associate Prof. Dr. of Mechatronics Engineering Çankaya University Compulsory Course in Mechatronics Engineering Credits (2/0/2)
More informationC8051F020 Utilization in an Embedded Digital Design Project Course. Daren R. Wilcox Southern Polytechnic State University Marietta, Georgia
C8051F020 Utilization in an Embedded Digital Design Project Course Daren R. Wilcox Southern Polytechnic State University Marietta, Georgia Abstract In this paper, the utilization of the C8051F020 in an
More informationThe Department of Electrical and Computer Engineering (ECE) offers the following graduate degree programs:
Note that these pages are extracted from the full Graduate Catalog, please refer to it for complete details. College of 1 ELECTRICAL AND COMPUTER ENGINEERING www.ece.neu.edu SHEILA S. HEMAMI, PHD Professor
More informationLEVERAGING FPGA AND CPLD DIGITAL LOGIC TO IMPLEMENT ANALOG TO DIGITAL CONVERTERS
LEVERAGING FPGA AND CPLD DIGITAL LOGIC TO IMPLEMENT ANALOG TO DIGITAL CONVERTERS March 2010 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com
More informationOverview. Proven Image Quality and Easy to Use Without a Frame Grabber. Your benefits include:
Basler runner Line Scan Cameras High-quality line scan technology meets a cost-effective GigE interface Real color support in a compact housing size Shading correction compensates for difficult lighting
More informationSystem-Level Display Power Reduction Technologies for Portable Computing and Communications Devices
System-Level Display Power Reduction Technologies for Portable Computing and Communications Devices Achintya K. Bhowmik and Robert J. Brennan Intel Corporation 2200 Mission College Blvd. Santa Clara, CA
More informationISSCC 2003 / SESSION 9 / TD: DIGITAL ARCHITECTURE AND SYSTEMS / PAPER 9.3
ISSCC 2003 / SESSION 9 / TD: DIGITAL ARCHITECTURE AND SYSTEMS / PAPER 9.3 9.3 Ultra-High Resolution Image Capturing and Processing for Digital Cinematography Albert Theuwissen 1, John Coghill, Lucian Ion,
More informationHow an electronic shutter works in a CMOS camera. First, let s review how shutters work in film cameras.
How an electronic shutter works in a CMOS camera I have been asked many times how an electronic shutter works in a CMOS camera and how it affects the camera s performance. Here s a description of the way
More informationMeasuring Laser Power and Energy Output
Measuring Laser Power and Energy Output Introduction The most fundamental method of checking the performance of a laser is to measure its power or energy output. Laser output directly affects a laser s
More informationRF Energy Harvesting Circuits
RF Energy Harvesting Circuits Joseph Record University of Maine ECE 547 Fall 2011 Abstract This project presents the design and simulation of various energy harvester circuits. The overall design consists
More informationDIODE LASER BASED PHOTOACOUSTIC SYSTEM FOR ATMOSPHERIC WATER VAPOR MEASUREMENTS
SUMMARY OF PHD THESIS DIODE LASER BASED PHOTOACOUSTIC SYSTEM FOR ATMOSPHERIC WATER VAPOR MEASUREMENTS MIKLÓS SZAKÁLL Consultants: Dr. Gábor Szabó professor, member of the Hungarian Academy of Science Dr.
More informationChapter 2 Basic Structure of Computers. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 Basic Structure of Computers Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Functional Units Basic Operational Concepts Bus Structures Software
More informationInteractive Level-Set Deformation On the GPU
Interactive Level-Set Deformation On the GPU Institute for Data Analysis and Visualization University of California, Davis Problem Statement Goal Interactive system for deformable surface manipulation
More informationA PC-BASED TIME INTERVAL COUNTER WITH 200 PS RESOLUTION
35'th Annual Precise Time and Time Interval (PTTI) Systems and Applications Meeting San Diego, December 2-4, 2003 A PC-BASED TIME INTERVAL COUNTER WITH 200 PS RESOLUTION Józef Kalisz and Ryszard Szplet
More informationBARE PCB INSPECTION BY MEAN OF ECT TECHNIQUE WITH SPIN-VALVE GMR SENSOR
BARE PCB INSPECTION BY MEAN OF ECT TECHNIQUE WITH SPIN-VALVE GMR SENSOR K. Chomsuwan 1, S. Yamada 1, M. Iwahara 1, H. Wakiwaka 2, T. Taniguchi 3, and S. Shoji 4 1 Kanazawa University, Kanazawa, Japan;
More informationSynchronization of sampling in distributed signal processing systems
Synchronization of sampling in distributed signal processing systems Károly Molnár, László Sujbert, Gábor Péceli Department of Measurement and Information Systems, Budapest University of Technology and
More informationELEC 5260/6260/6266 Embedded Computing Systems
ELEC 5260/6260/6266 Embedded Computing Systems Spring 2016 Victor P. Nelson Text: Computers as Components, 3 rd Edition Prof. Marilyn Wolf (Georgia Tech) Course Topics Embedded system design & modeling
More information