Jz4730 Multimedia Application Processor. Data Sheet

Transcription

1 Jz4730 Multimedia Application Processor Data Sheet Revision: 1.3 Date: Jul. 2007

2 Jz4730 Multimedia Application Processor Data Sheet Copyright ngenic Semiconductor Co. Ltd All rights reserved. Release history Date Revision Change Apr First release Aug Change ball assignment and some DC parameter tables - Add solder process description Jun PN description format change Jul Eliminate DMA pins, GP12 replaced by CHP_MDE Disclaimer This documentation is provided for use with ngenic products. No license to ngenic property rights is granted. ngenic assumes no liability, provides no warranty either expressed or implied relating to the usage, or intellectual property right infringement except as provided for by ngenic Terms and Conditions of Sale. ngenic products are not designed for and should not be used in any medical or life sustaining or supporting equipment. All information in this document should be treated as preliminary. ngenic may make changes to this document without notice. Anyone relying on this documentation should contact ngenicfor the current documentation and errata. ngenic Semiconductor Co., Ltd. Room 801C, Creative E, No.1 B/D ShangDi East Road, Haidian District, Beijing , China Tel: Fax: Http: //

3 Content Content 1 verview Block Diagram Features CPU core Memory sub-system Clock generation and power management n-chip peripherals Characteristic Packaging and out nformation verview Solder Process Package , 2, 3, Electrical Specifications Absolute Maximum Ratings Recommended operating conditions DC Specifications Consumption Specifications Reset and AC Timing Specifications n Timing Hardware Reset Timing Copyright ngenic Semiconductor Co., Ltd. All rights reserved. i

4 Content Tables Table 2-1 EMC s (81; 9 GP shared)...14 Table 2-2 PCMCA/CF s (6; all GP shared)...16 Table 2-3 LCDC s (24; all GP shared)...16 Table 2-4 2C s (2)...17 Table 2-5 SCC s (4; all GP shared)...17 Table 2-6 UART s (10; all GP shared)...17 Table 2-7 SS s (5; all GP shared)...18 Table 2-8 DMA s ()...18 Table 2-9 PWM s (2; all GP shared)...18 Table 2-10 UHC s (7; 2 GP shared)...19 Table 2-11 MAC s (17; 13 GP shared)...19 Table 2-12 CM s (12; all GP shared)...20 Table 2-13 PS2 Keyboard s (2; all GP shared)...20 Table 2-14 AC97/2S s (6; all GP shared)...20 Table 2-15 MSC s (6; all GP shared)...21 Table 2-16 GP s (15)...21 Table 2-17 JTAG s (5)...22 Table 2-18 System s (11)...22 Table 2-19 Not connected s (9)...22 Table 2-20 /Core/PLL/USB power supplies (28)...23 Table 3-1 Absolute Maximum Ratings...24 Table 3-2 Recommended operating conditions for power supplies...24 Table 3-3 Recommended operating conditions for VDD1 supplied pins in 3.3V application...25 Table 3-4 Recommended operating conditions for VDD1 supplied pins in 1.8V application...25 Table 3-5 Recommended operating conditions for VDD2 supplied pins...25 Table 3-6 Recommended operating conditions for VDDUSB pins...25 Table 3-7 Recommended operating conditions for others...25 Table 3-8 DC characteristics for VDD1 supplied pins in 3.3V application...26 Table 3-9 DC characteristics for VDD1 supplied pins in 1.8V application...26 Table 3-10 DC characteristics for VDD2 supplied pins...27 Table 3-11 DC characteristics for VDDUSB pins...27 Table 3-12 Dynamic Consumption Specifications...28 Table 3-13 Static Consumption Specifications...28 Table n Timing Parameters...29 Table 3-15 RESETP_ to RESETUT_ Timing Parameters...30 ii Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

5 Content Figures Figure 2-1 Jz4730 package Figure 2-2 Jz4730 pin to ball assignment Figure 3-1 -n Timing Diagram Figure 3-2 Hardware Reset Timing Diagram Copyright ngenic Semiconductor Co., Ltd. All rights reserved. iii

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7 verview 1 verview Jz4730 is a multimedia application processor targeting for handheld devices like smart-phone, PMP. ncorporate the XBurst CPU core based on leading micro-architecture technology, this processor provides high integration, high performance and low power consumption solution for embedded device. XBurst is a high performance and power-efficient 32-bit RSC core with 16K -Cache and 16K D-Cache in this processor, operating at speeds up to 336MHz. The memory interface supports a variety of memory types that allow flexible design requirements, include the glueless connection to NAND Flash for cost sensitive applications. n-chip modules such as LCD controller, AC97/2S controller and camera interface offer designers a rich suite of peripherals for multimedia application. WLAN, Bluetooth and expansion options are provided through the PCMCA/CF, USB, and MMC/SD host controllers. And the other peripherals such as UART, SP, smart card controller and Ethernet controller as well as general system resources provide enough computing and connectivity capability for many applications. 1.1 Block Diagram Memory Controller SRAM/Flash NAND Flash SDRAM controller PCMCA/CF DMA Controller Bridge MAC AHB BUS APB BUS USB1.1 Host/device XBurst CPU (16K $, 16K D$) LCD Controller Camera F GP PWM*2 2C SP *2 UART*4 Smart Card Controller AC97/2S MMC/SD JTAG PLL 12M SC Clock Divider and Distribution Management nterrupt Controller Real Time Clock Timer Watch Dog Figure 1-1 Jz4730 Diagram Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 5

8 verview 1.2 Features CPU core XBurst RSC instruction set to support Linux and WinCE XBurst 8-stage pipeline micro-architecture up to 336MHz 16K -Cache, 16K D-Cache 32-entry dual-pages joint-tlb, 4 entry nstruction TLB and 4 entry data TLB Hardware Debug support via JTAG port Memory sub-system Static memory interface Direct interface to SRAM, RM, Burst RM, and NR Flash Six chip-select pin for static memory, each can be configured separately Support 8, 16 or 32 bits data width The size and base address of static memory banks are programmable NAND Flash interface Support on CS3, sharing with static memory bank 3 Support all 8-bit/16-bit NAND Flash devices regardless of density and organization Hardware ECC generation Support automatic boot up from NAND Flash devices Synchronous DRAM nterface 2 banks with programmable size and base address 32-bit and 16-bit data bus width is supported Multiplexes row/column addresses according to SDRAM capacity Two-bank or four-bank SDRAM is supported Supports auto-refresh and self-refresh functions Supports power-down mode to minimize the power consumption of SDRAM Supports page mode PC Card nterface Fully compliant with the release of March 1997 of PC Card standard (16-bit PC Card) DMA transfer support Supports two PCMCA or CF socket Direct Memory Access Controller Eight independent DMA channels Transfer data units: 8-bit, 16-bit, 32-bit, 16-byte or 32-byte Transfer requests can be: auto-request within DMA; on-chip peripheral module request; and external request nterrupt on transfer completion or transfer error Supports two transfer modes: single mode or block mode The Jz4730 processor system supports little endian only 6 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

9 verview Clock generation and power management n-chip oscillator circuit ne n-chip phase-locked loops (PLL) with programmable multiple-ratio. nternal counter are used to ensure PLL stabilize time PLL on/off is programmable by software CLK, PCLK, SCLK, MCLK and LCLK frequency can be changed separately for software by setting division ratio Supports six low-power modes and function: NRMAL mode; DZE mode; DLE mode; SLEEP mode; HBERNATE mode; and MDULE-STP function n-chip peripherals General-Purpose / ports Total GP pin number is 128 Each pin can be configured as general-purpose input or output or multiplexed with internal chip functions Each pin can act as a interrupt source and has configurable rising/falling edge or high/low level detect manner, and can be masked independently Each pin can be configured as open-drain when output nterrupt controller Total 28 maskable interrupt sources from on-chip peripherals and external request through GP ports nterrupt source and pending registers for software handling Unmasked interrupts can wake up the chip in sleep or standby mode perating system timer Provide three separate channels 32-bit counter with auto-reload function Generate interrupt when the down counter underflows Six counting clock sources: RTCCLK (real time clock), EXTAL (external clock input), φ/4, φ/16, φ/64 and φ/256. (φ is the internal clock for on-chip peripheral) Watchdog timer 32-bit counter with RTC clock Generate power-on reset Pulse Width Modulator (PWM) Period control through a 6-bit clock divider and a 10-bit period counter 10-bit pulse counter LCD controller Single-panel display in active mode, and single- or dual-panel displays in passive mode Up to 64K colors in active mode, and up to 4096 colors in passive mode Display size up to pixels bits internal palette RAM Support TU601/656 data format Camera interface module nput image size up to pixels Supports CCR656 data format Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 7

10 verview image data receive FF with DMA support AC97/2S controller Supports 16, 18 and 20 bit sample for AC-link format, and 8, 16, 18, 20 and 24 bit for 2S/MSB-Justified format DMA transfer mode support Programmable utput channels and nput channels or Fixed mode for AC-link format down mode and two wake-up mode support for AC-link format Programmable nterrupt function support MMC/SD/SD controller Compliant with The MultiMediaCard System Specification version 3.3 Compliant with SD Memory Card Specification version 1.01 and SD Card Specification version 1.0 with 1 command channel and 4 data channels 20~80 Mbps maximum data rate Supports up to 10 cards (including one SD card) Maskable hardware interrupt for SD / interrupt, internal status, and FF status 2C bus interface nly supports single master mode Supports 2C standard-mode and F/S-mode up to 400 khz Double-buffered for receiver and transmitter Supports general call address and START byte format after START condition Synchronous serial interface Supports three formats: T s SSP, National Microwire, and Motorola s SP Configurable 2-17 (or multiples of them) bits data transfer Full-duplex/transmit-only/receive-only operation Supports normal transfer mode or nterval transfer mode Programmable transfer order: MSB first or LSB first 17-bit width, 16-level deep transmit-ff and receive-ff Programmable divider/prescaler for SS clock Back-to-back character transmission/reception mode Four UART 5, 6, 7 or 8 data bit operation with 1 or 1.5 or 2 stop bits, programmable parity (even, odd, or none) 16x8bit FF for transmit and 16x11bit FF for receive data Programmable baud rate up to 230.4Kbps nterrupt support for transmit, receive (data ready or timeout), and line status Supports DMA transfer mode Provide complete serial port signal for modem control functions Support slow infrared asynchronous interface (rda) 8 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

11 verview Two smart card controller Compliant with S/EC standard , supports both normal smart card and UM card interface Support asynchronous character (T = 0)/ block (T = 1) communication modes 8-bit, 16-level FF, and programmable SCC_CLK output clock frequency nterrupt support for data communication and error handling USB host interface pen Host Controller nterface (HC)-compatible and USB Revision 1.1-compatible USB device interface Compliant with USB protocol revision 1.1 Supports suspend/resume and remote wakeup Supports 8 physical endpoints and 9 logic endpoints Supports bulk, isochronous, interrupt and control transaction Ethernet MAC interface Compliant with EEE802.3, 802.3u 10/100 Mbps data transfer rates with full and half duplex modes EEE802.3 compliant M interface to talk to an external PHY VLAN support 2K bytes Tx buffers, and 2K bytes Rx buffers Supports DMA engine using burst mode Supports remote wake-up frame and magic packet frame Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 9

12 verview 1.3 Characteristic tem Characteristic Process Technology 0.18um CMS supply voltage /: 3.3 ± 0.3V Core: 1.8 ± 0.2 Package 256 BGA 17mm * 17mm perating frequency 336 MHz consumption 336MHz 10 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

13 Packaging and out nformation 2 Packaging and out nformation 2.1 verview Jz4730 processor is offered in a 256-pin LFBGA package, which is 17mm x 17mm outline, 20 x 20 matrix ball grid array and 0.8mm pitch, show in Figure 2-1. The Jz4730 pin to ball assignment is show in Figure 2-2. The detailed pin description is listed in Table 2-1 ~ Table Solder Process Jz4730 package is lead-free. t s reflow profile follows the PC/JEDEC lead-free reflow profile as contained in J-STD-020C. Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 11

14 Packaging and out nformation 2.3 Package Top View Side View Notes: Bottom View 1. 5 Dimension is measured at the maximum solder ball diameter, parallel to primary datum C 2. 6 Primary datum C and seating plane are defined by the spherical crowns of the solder balls 3. Package outline 20 x 20 matrix, 17.00mm x 17.00mm x 1.40mm, 0.70mm mold cap, 0.46mm ball, 0.80mm pitch, laminate substrate Figure 2-1 Jz4730 package 12 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

15 Packaging and out nformation Figure 2-2 Jz4730 pin to ball assignment Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 13

16 Packaging and out nformation 1, 2, 3, Loc Cell Table 2-1 EMC s (81; 9 GP shared) 14 Copyright ngenic Semiconductor Co., Ltd. All rights reserved. D0 C16 8mA D0: Memory data bus bit 0 VDD1 D1 B16 8mA D1: Memory data bus bit 1 VDD1 D2 A16 8mA D2: Memory data bus bit 2 VDD1 D3 D17 8mA D3: Memory data bus bit 3 VDD1 D4 C17 8mA D4: Memory data bus bit 4 VDD1 D5 B17 8mA D5: Memory data bus bit 5 VDD1 D6 A17 8mA D6: Memory data bus bit 6 VDD1 D7 C18 8mA D7: Memory data bus bit 7 VDD1 D8 B18 8mA D8: Memory data bus bit 8 VDD1 D9 A18 8mA D9: Memory data bus bit 9 VDD1 D10 B19 8mA D10: Memory data bus bit 10 VDD1 D11 A19 8mA D11: Memory data bus bit 11 VDD1 D12 A20 8mA D12: Memory data bus bit 12 VDD1 D13 B20 8mA D13: Memory data bus bit 13 VDD1 D14 C19 8mA D14: Memory data bus bit 14 VDD1 D15 C20 8mA D15: Memory data bus bit 15 VDD1 D16 J18 8mA D16: Memory data bus bit 16 VDD1 D17 J19 8mA D17: Memory data bus bit 17 VDD1 D18 J20 8mA D18: Memory data bus bit 18 VDD1 D19 K18 8mA D19: Memory data bus bit 19 VDD1 D20 K19 8mA D20: Memory data bus bit 20 VDD1 D21 K20 8mA D21: Memory data bus bit 21 VDD1 D22 L18 8mA D22: Memory data bus bit 22 VDD1 D23 L19 8mA D23: Memory data bus bit 23 VDD1 D24 L20 8mA D24: Memory data bus bit 24 VDD1 D25 M17 8mA D25: Memory data bus bit 25 VDD1 D26 M18 8mA D26: Memory data bus bit 26 VDD1 D27 M19 8mA D27: Memory data bus bit 27 VDD1 D28 M20 8mA D28: Memory data bus bit 28 VDD1 D29 N17 8mA D29: Memory data bus bit 29 VDD1 D30 N18 8mA D30: Memory data bus bit 30 VDD1 D31 N19 8mA D31: Memory data bus bit 31 VDD1 A0 A10 2mA A0: Static memory address bit 0 VDD1 A1 C11 2mA A1: Static memory address bit 1 VDD1 A2 E17 12mA A2: Static/SDRAM memory address bit 2 VDD1 A3 E18 12mA A3: Static/SDRAM memory address bit 3 VDD1 A4 E19 12mA A4: Static/SDRAM memory address bit 4 VDD1 A5 E20 12mA A5: Static/SDRAM memory address bit 5 VDD1 A6 F17 12mA A6: Static/SDRAM memory address bit 6 VDD1 A7 F18 12mA A7: Static/SDRAM memory address bit 7 VDD1 A8 F19 12mA A8: Static/SDRAM memory address bit 8 VDD1 A9 F20 12mA A9: Static/SDRAM memory address bit 9 VDD1

17 Loc Cell Packaging and out nformation A10 G17 12mA A10: Static/SDRAM memory address bit 10 VDD1 A11 G18 12mA A11: Static/SDRAM memory address bit 11 VDD1 A12 G19 12mA A12: Static/SDRAM memory address bit 12 VDD1 A13 G20 12mA A13: Static/SDRAM memory address bit 13 VDD1 A14 H18 12mA A14: Static/SDRAM memory address bit 14 VDD1 A15 H19 12mA A15: Static/SDRAM memory address bit 15 VDD1 A16 H20 12mA A16: Static/SDRAM memory address bit 16 VDD1 A17 B11 2mA A17: Static memory address bit 17 VDD1 A18 A11 2mA A18: Static memory address bit 18 VDD1 A19 D12 2mA A19: Static memory address bit 19 VDD1 A20 C12 2mA A20: Static memory address bit 20 VDD1 A21 B12 2mA A21: Static memory address bit 21 VDD1 A22 A12 2mA A22: Static memory address bit 22 VDD1 A23 C13 2mA A23: Static memory address bit 23 VDD1 A24 B13 2mA A24: Static memory address bit 24 VDD1 A25 A13 2mA A25: Static memory address bit 25 VDD1 DCS0_ B14 8mA DCS0_: SDRAM chip select 0 VDD1 DCS1_ GP82 C14 8mA, DCS1_: SDRAM chip select 1 GP82: GP 82 VDD1 RAS_ B15 8mA RAS_: SDRAM row address strobe VDD1 CAS_ C15 8mA CAS_: SDRAM column address strobe VDD1 CKE D15 8mA CKE: SDRAM clock enable VDD1 RDWR_ D18 12mA RDWR_: SDRAM write enable, 1 read; 0 write VDD1 CK A14 12mA CK: SDRAM clock VDD1 CS0_ B9 2mA CS0_: Static memory chip select 0 VDD1 CS1_ GP83 CS2_ GP84 CS3_ GP85 CS4_ GP86 CS5_ GP87 RD_ PE_ WE_ PWE_ WE0_ PW_ WE1_ PR_ WE2_ PREG_ C9 A8 B8 C8 A7 B10 C10 A15 D16 D19 2mA 2mA 8mA 8mA 8mA CS1_: Static memory chip select 1 GP83: GP 83 CS2_: Static memory chip select 2 GP84: GP 84 CS3_: Static memory chip select 3 GP85: GP 85 CS4_: Static memory chip select 4 GP86: GP 86 CS5_: Static memory chip select 5 GP87: GP 87 RD_: Static memory read strobe PE_: PCMCA memory read strobe WE_: Static memory write strobe PWE_: PCMCA memory write strobe WE0_: SDRAM/Static memory byte 0 write enable PW_: PCMCA write strobe WE1_: SDRAM/Static memory byte 1 write enable PR_: PCMCA read strobe WE2_: SDRAM/Static memory byte 2 write enable PREG_: PCMCA register select VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 WE3_ D20 8mA WE3_: SDRAM/Static memory byte 3 write enable VDD1 WAT_ PWAT_ FRE_ GP79 FWE_ GP80 A9 C7 B7 pull-up, Schmitt WAT_: Slow static memory/device wait signal PWAT_: PCMCA wait signal FRE_: NAND flash read enable GP79: GP 79 FWE_: NAND flash write enable GP80: GP 80 VDD1 VDD1 VDD1 Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 15

18 Packaging and out nformation Loc Cell FRB_ GP81 D7 FRB_: NAND flash ready/busy GP81: GP 81 VDD1 Table 2-2 PCMCA/CF s (6; all GP shared) Loc Cell S16_ GP92 N20 S16_: PCMCA address 16 bit select GP92: GP 92 VDD1 PSKTSEL GP91 P20 PSKTSEL: PCMCA socket select GP91: GP 91 VDD1 PCE1_ GP90 P19 PCE1_: PCMCA card enable 1 GP90: GP 90 VDD1 PCE2_ GP93 P18 PCE2_: PCMCA card enable 2 GP93: GP 93 VDD1 NPACK_ GP88 R18 NPACK_: PCMCA NPACK_ signal GP88: GP 88 VDD1 PBVD2 GP89 R19 PBVD2: PCMCA BVD2 signal GP89: GP 89 VDD1 Table 2-3 LCDC s (24; all GP shared) Loc Cell LCD_D0 GP40 J3 LCD_D0: LCD data bit 0 GP40: GP 40 VDD2 LCD_D1 GP41 H2 LCD_D1: LCD data bit 1 GP41: GP 41 VDD2 LCD_D2 GP42 G1 LCD_D2: LCD data bit 2 GP42: GP 42 VDD2 LCD_D3 GP43 J4 LCD_D3: LCD data bit 3 GP43: GP 43 VDD2 LCD_D4 GP44 G2 LCD_D4: LCD data bit 4 GP44: GP 44 VDD2 LCD_D5 GP45 H3 LCD_D5: LCD data bit 5 GP45: GP 45 VDD2 LCD_D6 GP46 F1 LCD_D6: LCD data bit 6 GP46: GP 46 VDD2 LCD_D7 GP47 E1 LCD_D7: LCD data bit 7 GP47: GP 47 VDD2 LCD_D8 GP48 G3 LCD_D8: LCD data bit 8 GP48: GP 48 VDD2 LCD_D9 GP49 F2 LCD_D9: LCD data bit 9 GP49: GP 49 VDD2 LCD_D10 GP50 D1 LCD_D10: LCD data bit 10 GP50: GP 50 VDD2 LCD_D11 GP51 F3 LCD_D11: LCD data bit 11 GP51: GP 51 VDD2 16 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

19 Packaging and out nformation Loc Cell LCD_D12 GP52 D2 LCD_D12: LCD data bit 12 GP52: GP 52 VDD2 LCD_D13 GP53 E2 LCD_D13: LCD data bit 13 GP53: GP 53 VDD2 LCD_D14 GP54 C1 LCD_D14: LCD data bit 14 GP54: GP 54 VDD2 LCD_D15 GP55 E3 LCD_D15: LCD data bit 15 GP55: GP 55 VDD2 LCD_VSYNC GP56 J1 LCD_VSYNC: LCD frame clock/vertical sync GP56: GP 56 VDD2 LCD_HSYNC GP57 J2 LCD_HSYNC: LCD line clock/horizonal sync GP57: GP 57 VDD2 LCD_PCLK GP58 H1 LCD_PCLK: LCD pixel clock GP58: GP 58 VDD2 LCD_DE GP59 K3 LCD_DE: STN AC bias drive/non-stn data enable GP59: GP 59 VDD2 LCD_SPL GP60 K2 LCD_SPL: LCD SPL output for special TFT panel GP60: GP 60 VDD2 LCD_CLS GP61 K1 LCD_CLS: LCD CLS output for special TFT panel GP61: GP 61 VDD2 LCD_PS GP62 L1 LCD_PS: LCD PS output for special TFT panel GP62: GP 62 VDD2 LCD_REV GP63 L2 LCD_REV: LCD REV output for special TFT panel GP63: GP 63 VDD2 Table 2-4 2C s (2) Loc Cell 2C_SDA Y4 open-drain 2C_SDA: 2C serial data VDD2 2C_SCK V5 open-drain 2C_SCK: 2C serial clock VDD2 Table 2-5 SCC s (4; all GP shared) Loc Cell SCC0_DATA GP64 V12 SCC0_DATA: SCC 0 data GP64: GP 64 VDD2 SCC0_CLK GP66 W12 SCC0_CLK: SCC 0 clock GP66: GP 66 VDD2 SCC1_DATA GP65 W13 SCC1_DATA: SCC 1 data GP65: GP 65 VDD2 SCC1_CLK GP67 Y13 SCC1_CLK: SCC 1 clock GP67: GP 67 VDD2 Loc Table 2-6 UART s (10; all GP shared) Cell Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 17

20 Packaging and out nformation Loc Cell UART0_TXD GP127 R20 UART0_TXD: UART 0 transmitting data GP127: GP 127 VDD2 UART0_RXD GP126 U20 UART0_RXD: UART 0 receiving data GP126: GP 126 VDD2 UART1_TXD GP25 T20 UART1_TXD: UART 1 transmitting data GP25: GP 25 VDD2 UART1_RXD GP24 T18 UART1_RXD: UART 1 receiving data GP24: GP 24 VDD2 UART2_TXD GP125 V20 UART2_TXD: UART 2 transmitting data GP125: GP 125 VDD2 UART2_RXD GP111 T19 UART2_RXD: UART 2 receiving data GP111: GP 111 VDD2 UART3_TXD GP21 U18 UART3_TXD: UART 3 transmitting data GP21: GP 21 VDD2 UART3_RXD GP16 U19 UART3_RXD: UART 3 receiving data GP16: GP 16 VDD2 UART3_RTS_ GP23 V18 UART3_RTS_: UART 3 RTS_ (request to send) signal GP23: GP 23 VDD2 UART3_CTS_ GP17 W20 UART3_CTS_: UART 3 CTS_ (clear to send) signal GP17: GP 17 VDD2 Table 2-7 SS s (5; all GP shared) Loc Cell SS_CLK GP72 Y8 SS_CLK: SS clock output GP72: GP 72 VDD2 SS_CE1_ GP73 V8 SS_CE1_: SS chip enable 1 GP73: GP 73 VDD2 SS_DT GP74 W8 SS_DT: SS data output GP74: GP 74 VDD2 SS_DR GP75 U8 SS_DR: SS data input GP75: GP 75 VDD2 SS_CE2_ SP_GPC GP76 Y7 SS_CE2_: SS chip enable 2 SS_GPC: SS general-purpose control signal GP76: GP 76 VDD2 Table 2-8 DMA s () Loc Cell VDD2 VDD2 VDD2 VDD2 Table 2-9 PWM s (2; all GP shared) Loc Cell 18 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

21 Packaging and out nformation Loc Cell PWM0 GP94 Y11 PWM0: PWM 0 output GP94: GP 94 VDD2 PWM1 GP95 V11 PWM1: PWM 1 output GP95: GP 95 VDD2 Table 2-10 UHC s (7; 2 GP shared) Loc Cell USB_CLK GP28 R3 USB_CLK: USB 48MHz clock input GP28: GP 28 VDD2 VC0 T1 Schmitt VC0: overcurrent for USB port 0 VDD2 PPWR0 GP29 T2 DPLS0 A U1 USB 1.1 PHY DMNS0 A U2 USB 1.1 PHY DPLS1 A T3 USB 1.1 PHY DMNS1 A T4 USB 1.1 PHY PPWR0: power enable for USB port 0 GP29: GP 29 DPLS0: USB 1.1 data plus port 0 DMNS0: USB 1.1 data minus port 0 DPLS0: USB 1.1 data plus port 1 DMNS0: USB 1.1 data minus port 1 VDD2 VDDusb VDDusb VDDusb VDDusb M_CL GP115 M_CRS GP116 Loc D5 B4 Table 2-11 MAC s (17; 13 GP shared) Cell M_CL: Ethernet collision GP115: GP 115 M_ CRS: Ethernet carrier sense GP116: GP 116 VDD2 VDD2 M_TX_CLK A1 M_TX_CLK: Ethernet transmit clock VDD2 M_TX_EN GP112 M_TXD0 GP117 M_TXD1 GP118 M_TXD2 GP119 M_TXD3 GP120 D3 C2 B2 F4 C3 M_TX_EN: Ethernet transmit enable GP121: GP 121 M_TXD0: Ethernet transmit data bit 0 GP117: GP 117 M_TXD1: Ethernet transmit data bit 1 GP118: GP 118 M_TXD2: Ethernet transmit data bit 2 GP119: GP 119 M_TXD3: Ethernet transmit data bit 3 GP120: GP 120 VDD2 VDD2 VDD2 VDD2 VDD2 M_RX_CLK A4 M_RX_CLK: Ethernet receive clock VDD2 M_RX_DV GP113 M_RX_ER GP114 M_RXD0 GP121 M_RXD1 GP122 M_RXD2 GP123 C5 A3 C4 D4 B3 M_RX_DV: Ethernet receive data valid GP113: GP 113 M_RX_ER: Ethernet receive error GP114: GP 114 M_RXD0: Ethernet receive data bit 0 GP121: GP 121 M_RXD1: Ethernet receive data bit 1 GP122: GP 122 M_RXD2: Ethernet receive data bit 2 GP123: GP 123 VDD2 VDD2 VDD2 VDD2 VDD2 Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 19

22 Packaging and out nformation M_RXD3 GP124 Loc E4 Cell M_RXD3: Ethernet receive data bit 3 GP124: GP 124 VDD2 M_MDC A2 2mA M_MDC: Ethernet management clock VDD2 M_MD B1 2mA M_MD: Ethernet management data VDD2 Table 2-12 CM s (12; all GP shared) Loc Cell CM_D0 GP0 M1 CM_D0: CM data input bit 0 GP0: GP 0 VDD2 CM_D1 GP1 M2 CM_D1: CM data input bit 1 GP1: GP 1 VDD2 CM_D2 GP2 M3 CM_D2: CM data input bit 2 GP2: GP 2 VDD2 CM_D3 GP3 M4 CM_D3: CM data input bit 3 GP3: GP 3 VDD2 CM_D4 GP4 N1 CM_D4: CM data input bit 4 GP4: GP 4 VDD2 CM_D5 GP5 N2 CM_D5: CM data input bit 5 GP5: GP 5 VDD2 CM_D6 GP6 N3 CM_D6: CM data input bit 6 GP6: GP 6 VDD2 CM_D7 GP7 N4 CM_D7: CM data input bit 7 GP7: GP 7 VDD2 CM_VSYNC GP8 P4 CM_VSYNC: CM VSYNC input GP8: GP 8 VDD2 CM_HSYNC GP9 P3 CM_HSYNC: CM HSYNC input GP9: GP 9 VDD2 CM_PCLK GP10 P2 CM_PCLK: CM pixel clock input GP10: GP 10 VDD2 CM_MCLK GP11 P1 CM_MCLK: CM master clock output GP11: GP 11 VDD2 Table 2-13 PS2 Keyboard s (2; all GP shared) Loc Cell PS2_KCLK GP32 W11 PS2_CLK: PS/2 keyboard clock GP32: GP 32 VDD2 PS2_KDATA GP33 Y12 PS2_KDATA: PS/2 keyboard data GP33: GP 33 VDD2 Table 2-14 AC97/2S s (6; all GP shared) Loc Cell BTCLK GP77 Y9 BTCLK: AC97/2S bit clock GP77: GP 77 VDD2 SDATA_UT GP70 W9 SDATA_UT: AC97/2S serial data output GP70: GP 70 VDD2 20 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

23 Packaging and out nformation Loc Cell SDATA_N GP71 Y10 SDATA_N: AC97/2S serial data input GP71: GP 71 VDD2 SYNC GP78 V10 SYNC: AC97 frame SYNC or 2S Left/Right GP78: GP 78 VDD2 SYSCLK GP68 V9 SYSCLK: 2S system clock output GP68: GP 68 VDD2 ACRESET_ GP69 W10 ACRESET_: AC97 reset output GP69: GP 69 VDD2 Table 2-15 MSC s (6; all GP shared) Loc Cell MSC_DAT0 GP34 W18 MSC_DAT0: MSC data bit 0 GP34: GP 34 VDD2 MSC_DAT1 GP35 U16 MSC_DAT1: MSC data bit 1 GP35: GP 35 VDD2 MSC_DAT2 GP36 Y20 MSC_DAT2: MSC data bit 2 GP36: GP 36 VDD2 MSC_DAT3 GP37 V17 MSC_DAT3: MSC data bit 3 GP37: GP 37 VDD2 MSC_CMD GP38 U15 MSC_CMD: MSC command GP38: GP 38 VDD2 MSC_CLK GP39 Y19 MSC_CLK: MSC clock output GP39: GP 39 VDD2 Table 2-16 GP s (15) Loc Cell GP13 B6 GP13: GP 13 VDD2 GP26 A5 GP26: GP 26 VDD2 GP27 C6 GP27: GP 27 VDD2 GP96 Y16 GP96: GP 96 VDD2 GP97 W15 GP97: GP 97 VDD2 GP98 V14 GP98: GP 98 VDD2 GP99 U13 GP99: GP 99 VDD2 GP100 Y15 GP100: GP 100 VDD2 GP101 W14 GP101: GP 101 VDD2 GP102 Y14 GP102: GP 102 VDD2 GP103 V13 GP103: GP 103 VDD2 GP104 W17 GP104: GP 104 VDD2 Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 21

24 Packaging and out nformation Loc Cell GP105 V16 GP105: GP 105 VDD2 GP106 W16 GP106: GP 106 VDD2 GP107 Y18 GP107: GP 107 VDD2 GP108 U14 GP108: GP 108 VDD2 GP109 V15 GP109: GP 109 VDD2 GP110 Y17 GP110: GP 110 VDD2 Loc Cell TRST_ U7 Schmitt, pull-down TCK V6 Schmitt, pull-down TMS Y5 Schmitt, pull-up TD W5 Schmitt, pull-up Table 2-17 JTAG s (5) TRST_: JTAG reset TCK: JTAG clock TMS: JTAG mode select TD: JTAG serial data input VDD2 VDD2 VDD2 VDD2 TD U6 4mA TD: JTAG serial data output VDD2 Loc Cell Table 2-18 System s (11) EXTAL A V4 3~20 MHz EXTAL: SC input or external clock input VDD2 XTAL A U5 scillator, XTAL: SC output SC on/off VDD2 RTCLK W2 RTCLK: 32768Hz clock input VDD2 RESETP_ W3 Schmitt RESETP_: power on reset and RESET-KEY reset input VDD2 RESETUT_ W4 4mA RESETUT_: Reset output VDD2 BT_SEL0 W6 BT_SEL0: Boot select bit 0 VDD2 BT_SEL1 W7 BT_SEL1: Boot select bit 1 VDD2 BT_SEL2 V7 BT_SEL2: Boot select bit 2 VDD2 BT_SEL3 Y6 BT_SEL3: Boot select bit 3 VDD2 TEST_MDE R1 Schmitt, TEST_MDE: Manufacture test enable pull-down VDD2 TAP_MD L3 Schmitt, TAP_MD: TAP select. 1: CPU EJTAG TAP; 0: boundary scan JTAG TAP pull-down VDD2 CHP_MDE B5 CHP_MDE: this pin must be inputted 0 or is left not-connected Schmitt, 0 chip works for handset/mobile multi-media applications pull-down 1 chip works for fiscal applications VDD2 Table 2-19 Not connected s (9) 22 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

25 Packaging and out nformation Loc Cell NC - T17 U4 U17 V3 V19 W19 Y1 Y2 Y3 NC: 9 not connected pins - Loc VDD1 P A6 D8 D14 J17 R17 Table 2-20 /Core/PLL/USB power supplies (28) Cell VDD1: 5 digital power, 1.8V ~ 3.3V VDD2 P H4 U9 VDD2: 2 digital power, 3.3V - VSS P D9 D13 H17 D6 G4 P17 U10 VDDcore P D10 K17 L4 R2 U11 VSScore P D11 K4 L17 R4 U12 VSS: 7 digital ground VDDcore: 5 CRE digital power, 1.8V VSScore: 5 CRE digital ground VDDPLL P W1 VDDPLL: 1 PLL analog power, 1.8V - VSSPLL P V2 VSSPLL: 1 PLL analog ground - VDDUSB P V1 VDDUSB: 1 USB analog power, 3.3V - VSSUSB P U3 VSSUSB: 1 USB analog ground Notes: 1. cells power supplied by VDD1 are regular cells. DC specification of them is described in Table 3-3 and Table cells power supplied by VDD2 are standard cells. DC specification of them is described in Table The meaning of phases in cell characteristics are a) 2/4/8/12mA: The cell s output driving strength is about 2/4/8/12mA b) Pull-up: The cell contains a pull-up resistor c) Pull-down: The cell contains a pull-down resistor d) Pullup-pe: The cell contains a pull-up resistor and the pull-up resistor can be enabled or disabled by setting corresponding register e) Pulldown-pe: The cell contains a pull-down resistor and the pull-down resistor can be enabled or disabled by setting corresponding register f) Schmitt: The cell is Schmitt trigged input 4. For any GP shared pin, the reset state is GP input with internal pull-up or pull-down. Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 23

26 Electrical Specifications 3 Electrical Specifications 3.1 Absolute Maximum Ratings The absolute maximum ratings for the processors are listed in Table 3-1. Do not exceed these parameters or the part may be damaged permanently. peration at absolute maximum ratings is not guaranteed. Table 3-1 Absolute Maximum Ratings Symbol Description Min Max Unit T stg Storage Temperature C T opt peration Temperature C VDD1 power supplies voltage V VDD2 power supplies voltage V VDDUSB power supplies voltage V VDDcore power supplies voltage V VDDPLL power supplies voltage V V 1 nput voltage to VDD1 supplied non-supply pins V V 2 nput voltage to VDD2 supplied non-supply pins V V USB nput voltage to VDDUSB supplied non-supply pins V V 1 V 2 V USB V ESD utput voltage from VDD1 supplied non-supply pins V utput voltage from VDD2 supplied non-supply pins V utput voltage from VDDUSB supplied non-supply pins V Maximum ESD stress voltage, Human Body Model; Any pin to any supply pin, either polarity, or Any pin to all non-supply pins together, either polarity. Three 2000 V stresses maximum. 3.2 Recommended operating conditions Table 3-2 Recommended operating conditions for power supplies Symbol Description Min Typical Max Unit V 1 VDD1 voltage for 3.3V applications V V 1 VDD1 voltage for 1.8V applications V 24 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

27 Electrical Specifications V 2 VDD2 voltage V V USB VDDUSB voltage V V CRE Core voltage V V PLL PLL analog voltage V Table 3-3 Recommended operating conditions for VDD1 supplied pins in 3.3V application Symbol Description Min Typical Max Unit V H nput high voltage V V L nput low voltage V Table 3-4 Recommended operating conditions for VDD1 supplied pins in 1.8V application Symbol Description Min Typical Max Unit V H nput high voltage 0.65 * V 1 + V 1 V L nput low voltage * V 1 V V Table 3-5 Recommended operating conditions for VDD2 supplied pins Symbol Description Min Typical Max Unit V H nput high voltage V V L nput low voltage V Table 3-6 Recommended operating conditions for VDDUSB pins Symbol Description Min Typical Max Unit V LH nput voltage range 0 V USB V Table 3-7 Recommended operating conditions for others Symbol Description Min Typical Max Unit T A Ambient temperature 0 70 C 3.3 DC Specifications The DC characteristics for each pin include input-sense levels and output-drive levels and currents. These parameters can be used to determine maximum DC loading, and also to determine maximum transition times for a given load. All DC specification values are valid for the entire temperature range of the device. Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 25

28 Electrical Specifications Table 3-8 DC characteristics for VDD1 supplied pins in 3.3V application Symbol Description Min Typical Max Unit V T Threshold point V V T+ Schmitt trig low to high threshold point V V T- Schmitt trig high to low threshold point V L nput Leakage Current ±10 μa Z Tri-State output leakage current ±10 μa R PU Pull-up Resistor kω R PD Pull-down Resistor kω C Capacitance of the pins pf V L utput low L =2, 4, 8, 12mA 0.4 V V H utput high H =2, 4, 8, 12mA 2.4 V Low level output L =0.4V for cells of L H 2mA 4mA 8mA 12mA ma High level output H =2.4V for cells of 2mA mA ma 8mA mA Table 3-9 DC characteristics for VDD1 supplied pins in 1.8V application Symbol Description Min Typical Max Unit V T Threshold point V V T+ Schmitt trig low to high threshold point V V T- Schmitt trig high to low threshold point V L nput Leakage Current ±10 μa Z Tri-State output leakage current ±10 μa R PU Pull-up Resistor kω R PD Pull-down Resistor kω C Capacitance of the pins pf V L utput low L =2, 4, 8, 12mA 0.45 V V H utput high H =2, 4, 8, 12mA V V L Low level output L =0.4V for cells of 2mA 4mA 8mA 12mA ma 26 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

29 Electrical Specifications High level output H =2.4V for cells of H 2mA 4mA 8mA 12mA ma Table 3-10 DC characteristics for VDD2 supplied pins Symbol Description Min Typical Max Unit V T Threshold point V V T+ Schmitt trig low to high threshold point V V T- Schmitt trig high to low threshold point V L nput Leakage Current ±10 μa Z Tri-State output leakage current ±10 μa R PU Pull-up Resistor kω R PD Pull-down Resistor kω C Capacitance of the pins pf V L utput low L =2, 4mA 0.4 V V H utput high H =2, 4mA 2.4 V Low level output L =0.4V for cells of L H 2mA 4mA ma High level output H =2.4V for cells of 2mA ma 4mA Table 3-11 DC characteristics for VDDUSB pins Symbol Description Min Typical Max Unit V LH utput voltage range 0 V USB V V D Differential input sensitivity 0.2 V V CM Differential common mode range V V SE Single ended receiver threshold V Z Tri-State leakage current ±10 μa Z DRV Driver output resistance, including damping Ω resistor V L Static output low voltage 0.3 V V H Static output high voltage 2.8 V 3.4 Consumption Specifications consumption depends on the operating frequency, operating voltage, program used which determines internal and external switching activities, external loading and even environment Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 27

30 Electrical Specifications ambient. The typical power consumption of both dynamic and static for the Jz4730 processor are provided here. Table 3-12 Dynamic Consumption Specifications Symbol Description Conditions Typical Unit CRE VDDcore current VDDcore = VDDPLL = 1.8V, VDD1 = VDD2 = VDDUSB = 3.3V, ma VDD1 + VDD2 current Temp = room, CPU clock = 360MHz, ma AHB/APB/SDRAM clock = 120MHz, PLL VDDPLL current ma USB VDDUSB current Program = run GCC to compile a C file in Linux, 12MHz crystal used for EXCLK, Without 48MHz USB clock input, ETH CM are not in use, LCD is in use ma Table 3-13 Static Consumption Specifications Symbol Description Conditions Typical Unit CRE VDDcore current ua VDD1 + VDD2 current ua PLL VDDPLL current ua USB VDDUSB current VDDcore = VDDPLL = 1.8V, VDD1=VDD2=VDDUSB=3.3V, Chip enters hibernating mode, Temp = room, CRE VDDcore current ua VDD1 + VDD2 current ua PLL VDDPLL current ua USB VDDUSB current Same as above except chip enters sleep mode, The difference between sleep mode and hibernating mode is that 12MHz crystal running in sleep mode. ua ua 3.5 Reset and AC Timing Specifications The Jz4730 processor asserts the RESETUT_ pin in one of several modes: n Reset (RESETP_) Watch Dog Reset (internal controlled) The following sections provide the timing and specifications for the entry and exit of these modes n Timing The external voltage regulator and other power-on devices must provide the Jz4730 processor with a specific sequence of power and resets to ensure proper operation. Figure 3-1 shows this sequence and is detailed in Table n the processor, it is important that the power supplies be powered up in a certain order to avoid high current situations. The required order is: 28 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.

31 Electrical Specifications 1. VDD1 & VDD2 & VDDUSB 2. VDDCRE & VDDPLL t r_vdd VDD1/VDD2 /VDDUSB t r_vddcre VDDcore/VDDPLL t D_VDDCRE t D_TRST_ TRST_ t D_JTAG JTAG PNS RESETP_ t D_RESETP_ RESETUT_ t D_RESETUT_ Figure 3-1 -n Timing Diagram Table n Timing Parameters Symbol Description Min Typical Max Unit t r_vdd t D_VDDCRE VDD1/VDD2/VDDUSB Rise / Stabilization time ms Delay between VDD1/VDD2/VDDUSB stable and VDDCRE/VDDPLL applied 0 ms t r_vddcre VDDCRE/VDDPLL Rise / Stabilization time ms t D_TRST_ t D_JTAG t D_RESETP_ t D_RESETUT_ Delay between VDDCRE, VDDPLL stable 10 and JTAG reset TRST_ deasserted ns Delay between TRST_ deasserted and other JATG pins active 10 ns Delay between VDDCRE, VDDPLL stable 0.2 and RESETP_ deasserted ms Delay between RESETP_ deasserted and RESETUT_ deasserted ms Copyright ngenic Semiconductor Co., Ltd. All rights reserved. 29

32 Electrical Specifications Hardware Reset Timing The timing sequences for input signals RESETP_ and output signals RESETUT_, are shown in Figure 3-2 and Table 3-15, assumes the power supplies are stable at the assertion of RESETP_. t ac_reset_ RESETP_ t fd_resetout_ t rd_resetout_ RESETUT_ Figure 3-2 Hardware Reset Timing Diagram Table 3-15 RESETP_ to RESETUT_ Timing Parameters Symbol Description Min Typical Max Unit t ac_resetp_ Minimum assertion time of RESETP_ 0.2 (1) ms t fd_resetut_ t rd_resetut_ Delay between RESETP_ Asserted and RESETUT_ Asserted Delay between RESETP_ deasserted and RESETUT_ deasserted ns ms 30 Copyright ngenic Semiconductor Co., Ltd. All rights reserved.