RING DETECTION/VALIDATION WITH THE Si305X DAAS 1. Overview This application note is a guide to implementing ring validation and detection using the Si305x products. There are several methods available to detect ringing as well as a hardware validation feature to qualify the frequency and cadence of signals. In addition to ring detection, these features can also be used for polarity reversal detection, which is required for features, such as UK caller ID. 2. Ring Detection Methods Ring detection on the Si305x can be achieved using one of three methods. The first method uses the RGDT pin (available only on the Si3050/56). The second uses the RDT, RDTP, and the RTDN bits. Finally, the Serial Data out pin can be used to detect ringing signals. All of these methods require the DSP to qualify the frequency and cadence of the ringing signal. Alternatively, the hardware ring validation feature discussed can be used in place of using the DSP to monitor frequency. On the Si305x products, the ringing signal is resistively coupled from TIP and RING to the line side device. The signal appearing on these pins can be detected in Full- Wave or Half-Wave mode. Full-wave ring detection is accomplished by setting the RFWE bit. This bit affects each of the three methods as discussed below. The Full-Wave mode can be used to detect polarity reversals during caller ID, etc (excluding the Si3007/8). The actual voltage level that trips the ring detector can be programmed with the RT bit (N/A for Si3007/8). When cleared, the voltage threshold is in the range from 13.5 to 16.5 V rms. When set, the threshold voltage is increased from 19.35 to 23.65 V rms. The three detection methods are discussed in detail in the following sections. 2.1. RGDT Pin Method (Si3050/56 only) The RDGT pin can be monitored for activity on the RNG1 and RNG2 pins. In Half-Wave Detection mode (RFWE = 0), every time the voltage on these pins crosses the positive threshold, the RGDT pin will be asserted. In Full-Wave Detection mode (RFWE = 1), a voltage above the positive or below the negative threshold will cause the RGDT pin to be asserted. In this case, the frequency on the pin is twice the frequency of the actual ringing waveform. The RGDT pin is an open-drain output, and the polarity of this pin can be changed by setting the RPOL bit (Register 14, bit 1). It requires a 4.7 k pullup or pulldown for proper operation. If multiple devices are used, the RGDT pins can be connected to a single input with the combined pullup or pulldown resistance equal to 4.7 k. 2.2. Ring Detect Bits Method The second method of ring detection uses the RDT, RDTP, and RDTN bits. RDTP is set whenever the voltage at the line side device exceeds the positive threshold, and the RDTN bit is set when the voltage exceeds the negative threshold. When the signal at the device is between the thresholds, neither bit is set. The RDT behavior is also based on the voltage. When the RFWE bit is 0, a positive ring signal sets the RDT bit for a set period of time. When the RFWE bit is 1, a positive or negative ring signal sets the RDT bit. The RDT bit acts as a one-shot pulse. When a new ring signal is detected, the one shot is reset. If no new ring signals are detected prior to the one-shot counter reaching 0, the RDT bit clears. The length of this count is five seconds. The RDT bit is also reset to 0 by an offhook event. When the RDTM bit is set, a hardware interrupt occurs on the interrupt pin when RDT is triggered. This interrupt can be cleared by writing the RDTI bit to 0. The function of the interrupt pin is slightly different if Ring Validation mode is enabled as described in the Ring Validation section. 2.3. Serial Data Out Method The third method of ring detection uses the data communication interface to transmit ring data. If the isolation capacitor link is active (PDL = 0) and the device is in the on-hook state, the ring data is presented on the Serial Data Out Pin. The waveform on this pin depends on the state of the RFWE bit and whether the DAA is in On-Hook Monitor mode. When RFWE is 0, the serial data is 32768 (0x8000) while the voltage at the device is between the thresholds. When a ring is detected, the data transitions to +32767 when the ring signal is positive and then goes back to 32768 when the ring is near 0 and negative. Thus, a near square wave is presented by the SDO data that swings from 32768 to +32767 in cadence with the ring signal. Rev. 0.2 10/06 Copyright 2006 by Silicon Laboratories AN72
When RFWE is 1, the serial data pin sits at approximately +1228 while the voltage at the device is between the thresholds. When the ring becomes positive, the SDO data transitions to +32767. When the ring signal goes near 0, the SDO data remains near 1228. As the ring becomes negative, the SDO data transitions to 32768. This repeats in cadence with the ring signal. A simple method to see the ring signal on the serial data pin is to observe the MSB of the data. The MSB toggles at the same frequency as the ring signal independent of the Ring Detector mode. This is adequate information for determining the ring frequency. When using the Si3052 system side device, the data is presented in a parallel format on the PCI bus, but the waveform data is the same as described above. 3. Hardware Ring Validation Ringing signals are validated using a state machine with a series of bits to specify valid frequencies and cadences. These bits can be used to distinguish between actual ring signals and false ring trips and to detect and distinguish between distinctive ringing signals. They also eliminate software algorithms required to qualify ringing signals in previous generation products. The state machine is shown in Figure 1. The following is a summary of the relevant bits: RNGV Ring Validation Enable Enables/Disables hardware ring validation. RAS[5:0] Ring Assertion Time Sets minimum valid ring frequency. RMX[5:0] Ring Assertion Maximum Count Sets maximum valid ring frequency in conjunction with RAS. RCC[2:0] Ring Confirmation Count Sets minimum valid cadence on-time. RTO[3:0] Ring Timeout Sets minimum valid cadence off-time. RDLY[2:0] Ring Delay Sets delay from valid ring frequency to interrupt generation. Can be used to avoid going off-hook during power cross tests. RDT Ring Detect Indicates ring is occurring. RDTI Ring Detect Interrupt Indicates valid ring had occurred. RDTM Ring Detect Mask Used to mask RDTI to AOUT/INT pin. RDI Ring Detect Interrupt Mode Controls whether an interrupt occurs at the beginning only or the beginning and the end of a ring burst. By programming these bits to proper values as shown in the following sections, the programmer can accurately distinguish between valid and invalid ringing signals. 3.1. RNGV Ring Validation Enable (R24[7]) When set, this bit enables the usage of the built-in hardware validation feature. When cleared, this feature is disabled and ring detection must be performed using one of the previously-mentioned methods. 3.2. RAS Ring Assertion Time (R24[5:0]) At the first positive detect of any signal, a counter previously loaded with the value in the RAS bits begins to count down at a constant rate. As it counts down, the state machine checks for additional positive detects. If no additional positive detects occur during a period defined by a counter loaded with the value of the RAS bits, a polarity reversal has occurred and the state machine outputs a line reversal and resets itself. If additional positive detects are present and the RAS counter has not expired, the frequency of the signal is high enough and may be considered valid. The actual value loaded into the RAS bits is in binary coded increments of 2 ms. The value is calculated using the following formula: RAS[5:0] = 1/(2 x fmin x 2 ms) where fmin is the lower limit of the valid ring frequency range. Fmin is multiplied by 2 because there are two detects per cycle of the ringing signal. Also, the 2 ms factor is used because of the coding mentioned above. The default value of RAS is 11001 b, which translates to an fmin of 10 Hz. 3.3. RMX Ring Assertion Maximum Count (R22[5:0]) At the negative detect of the ringing signal, the value in the RAS counter is compared to the value of the RMX bits to determine if the signal frequency is in or out of the valid frequency range. If the RAS timer value is less than or equal to the RMX value, the frequency is valid; otherwise, it is too high. The value loaded into the RMX bits is also in binary coded increments of 2 ms and is calculated using the following formula: RMX[5:0] = RAS[5:0] - 1/(2 x fmax x 2 ms) where fmax is the upper limit of the valid ring frequency range. The default value is 10110 b, which translates to an fmax of 83.3 Hz. A timing diagram for both RAS and RMX is shown in Figure 2. When using the Si3007 or Si3008 lineside device, the RMX value should be loaded with a value 1 less than RAS to ensure proper ring detection for ringing signals with low DC battery feeds. 2 Rev. 0.2
SLEEP State-Machine Operation State machine is evaluated at 16 khz intervals count1 < ring_timeout count2 < inversion_assert output line_reversal = FALSE output valid_ring = FALSE CHECK_REVERSAL decrement count2 on line_activity line_activity & ring validation enabled line_activity & (count1 <= rmax) count2 < distinctive_ring_conf line_activity & timeout2 ASSERT_REVERSAL output line_reversal = TRUE count1 < ring_assert State-Machine Inputs line_activity : Tip/Ring voltage crosses ring voltage threshold timeout1 : count1 = = 0 timeout2 : count2 = = 0 TRIGGER Reject short events, transients, out-of-band signals decrement count2 timeout1 (low frequency detect) line_activity & (count1 > rmax) (high frequency detect) ring_timeout = RTO[3:0]x2048 inversion_assert = IAS distinctive_ring_conf = f(rcc[2:0]) ring_assert = RAS[5:0]x32 rmax = RMX[5:0]x32 ring_conf = RDLY[2:0]x4096 line_activity count1 < ring_timeout count2 < ring_conf timeout2 State-Machine Outputs line_reversal 1: = battery reversal detected valid_ring 1: = ring signal validated line_activity SCREEN Filter out multiple triggers from distinctive ringing cadences decrement count2 timeout2 timeout1 count2 < ring_conf count1 < ring_timeout ENDRING Find end of a valid ringing signal output valid_ring = TRUE timeout1 Figure 1. Si3050/52/54 Ring Validation State Diagram Rev. 0.2 3
RING FREQUENCY TOO LOW RING FREQUENCY IN RANGE RING FREQUENCY TOO HIGH High f Region Valid Region Low f Region RAS Timer RMX Value RMX Value Figure 2. Ring Validation Frequency Example RMX Value 384 ms RCC = 640 ms RCC = 640 ms On-time > RCC Valid On-time < RCC Invalid Figure 3. Ring Validation RCC[2:0] Bits Detect 512 ms Off - time Detect 2nd Detect Off - time RTO RTO Off-time < RTO No 2nd Detect Off-time > RTO 2nd Detect Figure 4. Ring Validation RTO[3:0] Bits 4 Rev. 0.2
Detect No Detect RDLY never reaches 0 On-time 384 ms On-time RDLY = 128 ms RDLY = 768 ms RCC = 512 ms RTO = 256 ms 3.4. RCC Ring Confirmation Count (R23[2:0]) The value of the RCC bits is loaded into another counter that begins counting down after the signal frequency has been validated by RAS and RMX. If the frequency falls out of the valid range any time before the counter expires, then the ring is not valid. If the frequency stays in range until the counter expires, then the ring signal meets the on-time requirement. The range of the RCC bits is 100 to, and the default value is 512 ms. The function of RCC is summarized in Figure 3. 3.5. RTO Ring Timeout (R23[6:3]) After the ring signal has been present for a duration equal to RCC, the state machine stops looking at frequency and starts looking for the end of the ring burst. The state machine determines the end of a ring burst by starting a timer that is previously loaded with the value encoded in RTO. This timer is reset whenever a detection occurs. If the timer expires, the ring burst is considered to have ended. In addition, the state machine is reset at this time. These bits can be used to detect and distinguish between distinctive ringing signals. The default value for RTO is 640 ms, and the range is from 128 to 1920 ms. Figure 4 shows the function of RTO. 3.6. RDLY Ring Delay (R23[7], R22[7:6]) The RDLY bits are used to delay the interrupt from occurring a certain amount of time from when the frequency and on-time has been validated. This is accomplished using a countdown timer. To get an interrupt, the RDLY timer must expire before the RTO Figure 5. Ring Validation RDLY[2:0] Bits timer expires because the latter causes the state machine to be reset. RDLY can be used to keep the DAA from going off-hook during 50/60 Hz power cross tests, which could be detected as a valid ring. The RDLY default value is 512 ms, and the range is from 0 to 1792 ms. A timing diagram for RDLY is shown in Figure 5. 4. Interrupt Generation in Ring Validation Mode With Ring Validation enabled, the output of the state machine controls when an interrupt is generated and the RDTI bit is set. The RDTI bit follows the rising edge of the RDT bit. The RDT bit still acts like a one shot, but the RDTI bit can be cleared during the ring signal. In Ring Validation mode, the state machine controls the RDT bit instead of RDT being a one-shot pulse with a 5 second width. If an interrupt is needed at the beginning and the end of the ring burst, the RDI bit should be set. This bit allows an interrupt to occur on the rising and falling edge of the ring burst. To see both interrupts, the RDTI bit must be cleared before the end of the burst. The beginning interrupt is triggered by the rising edge of the RDT bit, and the ending interrupt is triggered by RDT falling, which occurs when the RTO counter expires in the ring validation state machine. Rev. 0.2 5
DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Updated to include Si3007/8 line side ring validation considerations. 6 Rev. 0.2
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