Fujitsu Microelectronics Europe Application Note MCU-AN-300067-E-V11 FR FAMILY 32-BIT MICROCONTROLLER MB91460 CLOCK MONITOR APPLICATION NOTE
Revision History Revision History Date Issue 2008-06-02 V1.0, First draft, HPi 2008-06-03 V1.1, Updated introduction and Key feature section, HPi This document contains 12 pages. MCU-AN-300067-E-V11-2 - Fujitsu Microelectronics Europe GmbH
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Contents Contents REVISION HISTORY... 2 WARRANTY AND DISCLAIMER... 3 CONTENTS... 4 1 INTRODUCTION... 5 1.1 Key Features... 5 2 CLOCK MONITOR... 6 2.1 Block Diagrams... 6 2.2 Operation... 6 2.3 Registers... 7 2.3.1 Monitor Configuration Register (CMCFG)... 7 2.3.2 Clock Source Configuration Register (CSCFG)... 8 3 SOFTWARE EXAMPLE... 9 3.1 Basic Functionality of the Clock Monitor... 9 4 ADDITIONAL INFORMATION... 10 LIST OF FIGURES... 11 LIST OF TABLES... 12 MCU-AN-300067-E-V11-4 - Fujitsu Microelectronics Europe GmbH
Chapter 1 Introduction 1 Introduction The Clock Monitor is a module that outputs internal clock signals to a terminal to externally monitor them. The Clock Monitor provides a function to divide the frequency of a clock signal before it outputs to the terminal, thus allowing the clock signal to be used as an event at which external circuits act in synchronization with a MCU function. Not all devices are having this feature. Please refer datasheet of corresponding device to check availability of this function. 1.1 Key Features Divide an internal clock signal to output it to a terminal (MONCLK) Maximum frequency that can be monitored on a terminal (MONCLK) is 50MHz A dedicated MONCLK pin is available and no port function registers are required to set for enabling it. Division ratios: CLK/1, CLK/2, CLK/3,..., CLK/16 Programmable mark level (output L or H before enabling the clock output) Glitch free output enable Fujitsu Microelectronics Europe GmbH - 5 - MCU-AN-300067-E-V11
Chapter 2 Clock Monitor 2 Clock Monitor THE BASIC FUNCTIONALITY OF THE CLOCK MONITOR IS EXPLAINED 2.1 Block Diagrams Figure 2-1 shows the internal block diagram of a Clock Monitor. 2.2 Operation Figure 2-1: Clock Monitor Due to the glitch free switching mechanism it is necessary to follow these rules when switching the clock source (CMCFG3:0) or the pre-scalar ratio (CMPRE3:0): - The CMPRE3:0 registers can only be written if the CMSEL3:0 registers are currently 0x00. - The CMPRE3:0 registers can only be written if the CMSEL3:0 registers are written to 0x00 within the same write access. - Between 2 write accesses to CMPRE/CMCFG there must be at least 2 cycles of the divided monitor clock. - For changing the selector value, the MONCLK must be disabled. MCU-AN-300067-E-V11-6 - Fujitsu Microelectronics Europe GmbH
Chapter 2 Clock Monitor 2.3 Registers 2.3.1 Monitor Configuration Register (CMCFG) This register selects output settings of an internal clock signal Bit No. Name Explanation Value Operation 0000 Source clock (selected by CMSEL) divided by 1 (Initial) 0001 Source clock (selected by CMSEL) divided by 2 7,6,5,4 CMPRE3- Select an output CMPRE0 frequency prescaler 1110 Source clock (selected by CMSEL) divided by 15 1111 Source clock (selected by CMSEL) divided by 16 0000 MONCLK output disabled (high impedance) (Initial) 3,2,1,0 CMSEL3- CMSEL0 Select a clock source 0001 OSCMAIN 0010 OSCSUB 0011 CLKRC 0100 CLKSUBRC 0101 CLKMAIN 0110 CLKSUB 0111 CLKMOD 1000 Clock modulator observer output* 1001 PLL output after 1/g divider (Auto Gear) 1010 PLL output after 1/m divider 1011 CLKCAN 1100 CLKPLLFB 1101 CLKB 1110 CLKP 1111 CLKT *Silicon evaluation purposes only, not available for customer applications. Table 2-1: CMCFG Fujitsu Microelectronics Europe GmbH - 7 - MCU-AN-300067-E-V11
Chapter 2 Clock Monitor 2.3.2 Clock Source Configuration Register (CSCFG) Operation for Channel (2n+0) or Bit No. Name Explanation Value (2n+1) EDSU/MPU is (clock) disabled [Initial 0 7 EDSUEN EDSU/MPU Enable value] 1 EDSU/MPU is (clock) enabled 0 PLL is in the un-locked state 6 PLLLOCK PLL Lock 1 PLL is in the locked state 0 CLKRC is set to 100kHz [Initial value] 5 RCSEL CLKRC Selector 1 CLKRC is set to 2MHz MONCLK mark level is low [Initial Clock Monitor 0 4 MONCKI value] MONCLK inverter 1 MONCLK mark level is high LCD Controller is sourced by Sub Clock Source 0 Oscillator 3 CSC3 Selection for LCD LCD Controller is sourced by RC Controller 1 Oscillator (100kHz) Sub clock Calibration is sourced by Clock Source 0 Sub Oscillator 2 CSC2 Selection for Sub Sub clock Calibration is sourced by RC clock calibration 1 Oscillator(100kHz) Real Time Clock is sourced by Main 00 Oscillator Real Time Clock is sourced by Sub CSC1, Clock Source 01 1,0 CSC0 Oscillator Selection for RTC Real Time Clock is sourced by RC 10 Oscillator(100kHz) 11 Setting prohibited Table 2-2: CSCFG MCU-AN-300067-E-V11-8 - Fujitsu Microelectronics Europe GmbH
Chapter 3 Software Example 3 Software Example EXAMPLE FOR CLCOK MONITOR 3.1 Basic Functionality of the Clock Monitor The following example sets clock source and clock divider. /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES. */ /* (C) Fujitsu Microelectronics Europe GmbH */ /*---------------------------------------------------------------------------*/ void InitClockMonitor(unsigned char divider, unsigned char clk_source) { /* disable MonClk output */ CMCFG = (CMCFG & 0xF0); while (CMCFG & 0x0F) { HWWD_CL = 0; } /* Set Pre scalar value */ CMCFG = (CMCFG & 0x0F) (divider << 4); } /* Enable MonClk output */ CMCFG = CMCFG (clk_source & 0x0F); Note: Maximum frequency that can be monitored on a terminal (MONCLK) is 50MHz Fujitsu Microelectronics Europe GmbH - 9 - MCU-AN-300067-E-V11
Chapter 4 Additional Information 4 Additional Information Information about FUJITSU Microcontrollers can be found on the following Internet page: http://mcu.emea.fujitsu.com/ The software examples related to this application note is: 91460_monclk It can be found on the following Internet page: http://mcu.emea.fujitsu.com/mcu_product/mcu_all_software.htm MCU-AN-300067-E-V11-10 - Fujitsu Microelectronics Europe GmbH
List of Figures List of Figures Figure 2-1: Clock Monitor... 6 Fujitsu Microelectronics Europe GmbH - 11 - MCU-AN-300067-E-V11
List of Tables List of Tables Table 2-1: CMCFG... 7 Table 2-2: CSCFG... 8 MCU-AN-300067-E-V11-12 - Fujitsu Microelectronics Europe GmbH