MachXO Breakout Board Evaluation Kit User s Guide February 0 Revision: EB68_0.0
Introduction Thank you for choosing the Lattice Semiconductor MachXO Breakout Board Evaluation Kit! MachXO Breakout Board This user s guide describes how to start using the MachXO Breakout Board, an easy-to-use platform for evaluating and designing with the MachXO ultra-low density FPGA. Along with the board and accessories, this kit includes a pre-loaded demonstration design. You may also reprogram the on-board MachXO device to review your own custom designs. The MachXO Breakout Board currently features the MachXO-7000HE device. A previous version of this board featured the MachXO-00ZE. The board design and features have not changed, and consequently, this document can be used as a guide for either version of the board. If you require a board featuring the MachXO-00ZE, Lattice recommends the MachXO Pico Development Kit. See Ordering Information on page 6 for more information. Note: Static electricity can severely shorten the lifespan of electronic components. See the Storage and Handling section of this document for handling and storage tips. Features The MachXO Breakout Board Evaluation Kit includes: MachXO Breakout Board The board is a x form factor that features the following on-board components and circuits: MachXO FPGA Current board version: LCMXO-7000HE-TGC (Previous board version no longer available: LCMXO-00ZE-TGC) USB mini-b connector for power and programming Eight LEDs 60-hole prototype area Four x0 expansion header landings for general I/O, JTAG, and external power x8 expansion header landing for JTAG.V and.v supply rails Pre-loaded Demo The kit includes a pre-loaded counter design that highlights use of the embedded MachXO oscillator and programmable I/Os configured for LED drive. USB Connector Cable The board is powered from the USB mini-b socket when connected to a host PC. The USB channel also provides a programming interface to the MachXO JTAG port. Lattice Breakout Board Evaluation Kits Web Page Visit www.latticesemi.com/breakoutboards for the latest documentation (including this guide) and drivers for the kit. The content of this user s guide includes demo operation, programming instructions, top-level functional descriptions of the Breakout Board, descriptions of the on-board connectors, and a complete set of schematics.
MachXO Breakout Board Figure. MachXO Breakout Board, Top Side LED Array (J) x 60-Hole Prototype Array (J6) MachXO PLD (U) Two x0 Header Landings (J, J) Two x0 Header Landings (J, J) FTDI USB to UART/FIFO IC (U) JTAG Header Landing (J) USB Mini-B Socket (J7) Power/GND Test Points (TP, TP, TP) Power LED (PWR_ON) Storage and Handling Static electricity can shorten the lifespan of electronic components. Please observe these tips to prevent damage that could occur from electro-static discharge: Use anti-static precautions such as operating on an anti-static mat and wearing an anti-static wrist-band. Store the evaluation board in the packaging provided. Touch a metal USB housing to equalize voltage potential between you and the board. Software Requirements You should install the following software before you begin developing new designs for the Breakout board: Lattice Diamond design software FTDI Chip USB hardware drivers (installed as an option within the Diamond installation program) MachXO Device This board currently features the MachXO-7000HE FPGA which offers embedded Flash technology for instanton, non-volatile operation in a single chip. Numerous system functions are included, such as two PLLs and 6 Kbits of embedded RAM plus hardened implementations of I C, SPI, timer/counter, and user Flash memory. Flexible, high performance I/Os support numerous single-ended and differential standards including LVDS, and also source synchronous interfaces to DDR/DDR/LPDDR DRAM memory. The -pin TQFP package provides up to
MachXO Breakout Board user I/Os in a 0mm x 0mm form factor. Previous versions of this board featured the MachXO-00ZE PLD in the same package. This version of the board is no longer available. A complete description of this device can be found in the MachXO Family Data Sheet. Demonstration Design Lattice provides a simple, pre-programmed demo to illustrate basic operation of the MachXO device. The design integrates an up-counter with the on-chip oscillator. Note: You may obtain your Breakout Board after it has been reprogrammed. To restore the factory default demo and program it with other Lattice-supplied examples see the Download Demo Designs section of this document. Run the Demonstration Design Upon power-up, the preprogrammed demonstration design automatically loads and drives the LED array in an alternating pattern. The program shows a clock generator based on the MachXO on-chip oscillator. The counter module is clocked at the oscillator default frequency of.08mhz to illustrate how low speed timer functions can be implemented with a FPGA. The -bit up-counter further divides the clock to advance the LED display approximately every 00ms. The resulting light pattern will appear as an alternating pair of lit LEDs per row. Figure. Demonstration Design Block Diagram MachXO c_delay[0] (~ Hz) x8 LED Array -bit Up-Counter Clock Generator c_delay[:0].08 MHz WARNING: Do not connect the Breakout Board to your PC before you follow the driver installation procedure of this section. Communication with the Breakout Board with a PC via the USB connection cable requires installation of the FTDI chip USB hardware drivers. Loading these drivers enables the computer to recognize and program the Breakout Board. Drivers can be loaded as part of the installation of Lattice Diamond design software or Diamond Programmer, or as a stand-alone package. To load the FTDI Chip USB hardware drivers as part of the Lattice Diamond installation:. Select Programmer Drivers in the Product Options of Lattice Diamond Setup.. Select FTDI Windows USB Driver or All Drivers in the LSC Drivers Install/Uninstall dialog box.. Click Finish to install the USB driver.. After the driver installation is complete, connect the USB cable from a USB port on your PC to the board s USB mini-b socket (J). After the connection is made, a green Power LED (D9) will light indicating the board is powered on.. The demonstration design will automatically load and drive the LED array in an alternating pattern.
MachXO Breakout Board To load the FTDI chip USB hardware drivers via the stand-alone package:. Browse to www.latticesemi.com/breakoutboards and download the FTDI Chip USB Hardware Drivers package.. Extract the FTDI chip USB Hardware driver package to your PC hard drive.. Connect the USB cable from a USB port on your PC to the board s USB mini-b socket (J7). After the connection is made, a green Power LED (D9) will light indicating the board is powered on.. If you are prompted, Windows may connect to Windows Update select No, not this time from available options and click Next to proceed with the installation. Choose the Install from specific location (Advanced) option and click Next.. Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder created in the Download Windows USB Hardware Drivers section. Select the CDM.0.06 WHQL Certified folder and click OK. 6. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message indicating that the installation was successful. 7. Click Finish to install the USB driver. 8. The demonstration design will automatically load and drive the LED array in an alternating pattern. See the Troubleshooting section of this guide if the board does not function as expected. Download Demo Designs The counter demo is preprogrammed into the Breakout Board, however over time it is likely your board will be modified. Lattice distributes source and programming files for demonstration designs compatible with the Breakout Board. Please make sure you're downloading the demo design that matches your version of the board. Demo designs for both the 00ZE and 7000HE versions of the board are available. The description below references the 7000HE version, but instructions are similar for the 00ZE version. To download demo designs:. Browse to the Lattice Breakout Board Evaluation Kits web page (www.latticesemi.com/breakoutboards) of the Lattice web site. Select MachXO Breakout Board Demo Source and save the file.. Extract the contents of MachXO_7000HE_BB_Eval_Kit_v0.0.zip to an accessible location on your hard drive. The demo design directory Demo_LED is unpacked with all design files needed for the demo, including the JEDEC programming data file. Continue to Programming a Demo Design with Lattice Diamond Design Software. Programming a Demo Design with the Lattice Diamond Programmer The demonstration design is pre-programmed into the MachXO Breakout Board by Lattice. If you have changed the design but now want to restore the Breakout Board to factory settings, use the procedure described below. To program the MachXO device:. Install, license and run Lattice Diamond software. See www.latticesemi.com/latticediamond for download and licensing information.. Connect the USB cable to the host PC and the MachXO Breakout Board.. From Diamond, open the Demo_LED_OSC.ldf project file.
MachXO Breakout Board. Click the Programmer icon.. Click Detect Cable. The Programmer will detect the cable (Cable: USB, Port: FTUSB-0). 6. Click the Program icon. When complete, PASS is displayed in the Status column. MachXO Breakout Board This section describes the features of the MachXO Breakout Board in detail. Overview The Breakout Board is a complete development platform for the MachXO FPGA. The board includes a prototyping area, a USB program/power port, an LED array, and header landings with electrical connections to most of the FPGA s programmable I/O, power, and JTAG pins. The board is powered by the PC s USB port or optionally with external power. You may create or modify the program files and reprogram the board using Lattice Diamond software. Figure. MachXO Breakout Board Block Diagram Bank 0 x0 Header Landing (J) GPIO JTAG Programming USB Controller x8 Header Landing (J, Optional JTAG Interface) USB Mini B Socket A/Mini-B USB Cable Bank Bank (-00ZE) Bank, & (-7000HE) GPIO x0 Header Landing (J) x0 Header Landing (J) GPIO MachXO-7000HE or 00ZE device 8 LED Array GPIO x0 Header Landing (J) Bank 6
MachXO Breakout Board Table describes the components on the board and the interfaces it supports. Table. Breakout Board Components and Interfaces Component/Interface Type Schematic Reference Description Circuits USB Controller Circuit U: FTH USB-to-JTAG interface and dual USB UART/FIFO IC USB Mini-B Socket I/O J7:USB_MINI_B Programming and debug interface Components LCMXO FPGA U: LCMXO- 7000HE-TGC 7000-LUT device packaged in a 0 x 0mm, -pin TQFP Interfaces LED Array Output D8-D Red LEDs Four x0 Header Landings I/O J: header_x0 J: header_x0 J: header_x0 J: header_x0 User-definable I/O x8 Header Landing I/O J: header_x8 Optional JTAG interface x 60-Hole Prototype Area Prototype area 00mil centered holes. Test Points Power TP: +.V TP: +.V TP: GND Power and ground reference points Subsystems This section describes the principle sub systems for the Breakout Board in alphabetical order. Clock Sources All clocks for the counter demonstration designs originate from the MachXO on-chip oscillator. You may use an expansion header landing to drive a FPGA input with an external clock source. Expansion Header Landings The expansion header landings provide access to user GPIOs, primary inputs, clocks, and VCCO pins of the MachXO. The remaining pins serve as power supplies for external connections. Each landing is configured as one x0 00 mil. Table. Expansion Connector Reference Item Reference Designators Part Number J, J, J, J header_x0 Description 7
MachXO Breakout Board Table. Expansion Header Pin Information (J) Header Pin Number -00ZE Function -7000HE Function MachXO Pin NC NC - VCCIO0 VCCIO0 8,, PT7D / DONE PT6D / DONE 09 PT7C / INITn PT6C / INITn 0 PT7B PT6B 6 PT7A PT6A 7-8 - 9 PT6D PTB 0 PT6C PTA PT6B PT8B PT6A PT8A 7 PTD / PROGn PT7D / PROGn 9 PTC / JTAGen PT7C / JTAGen 0-6 - 7 PTB PTB 8 PTA PTA 9 PTD / SDA / PCLKC0_0 PTD / SDA / PCLKC0_0 0 PTC / SCL / PCLKT0_0 PTC / SCL / PCLKT0_0 6 PTB / PCLKC0_ PT8B / PCLKC0_ 7 PTA / PCLKT0_ PT8A / PCLKT0_ 8 - - PTD / TMS PT7D / TMS 0 6 PTC / TCK PT7C / TCK 7 PTB PTB 8 PTA PTA 9 PT0D / TDI PTD / TDI 6 0 PT0C / TDO PTC / TDO 7 - - PT0B PTB 8 PT0A PTA 9 PT9D PT0B 0 6 PT9C PT0A 7 PT9B PT9B 8 PT9A PT9A 9-0 - 8
MachXO Breakout Board Table. Expansion Header Pin Information (J) Header Pin Number -00ZE Function -7000HE Function MachXO Pin VCC_.V VCC_.V 6, 7, 08, VCCIO VCCIO 79, 88, 0 VCC_.V VCC_.V 6, 7, 08, NC NC - PR0C PRA 7 6 PR0D PRB 7 7 PR0A PRA 76 8 PR0B PRB 7 9-0 - PR9C PRA 78 PR9D PRB 77 PR9A PR8A 8 PR9B PR8B 8-6 - 7 PR8C PR7A 8 8 PR8D PR7B 8 9 PR8A PR6A 86 0 PR8B PR6B 8 - - PRC / PCLKT_0 PRA / PCLKT_0 9 PRD / PCLKC_0 PRB / PCLKC_0 9 PRA PRA 9 6 PRB PRB 9 7-8 - 9 PRC PR9A 96 0 PRD PR9B 9 PRA PR7A 98 PRB PR7B 97 - - PRA PRA 00 6 PRB PRB 99 7 PRC PRA 0 8 PRD PRB 0 9 PRA PRA 07 0 PRB PRB 06 9
MachXO Breakout Board Table. Expansion Header Pin Information (J) Header Pin Number -00ZE Function -7000HE Function MachXO Pin VCC_.V VCC_.V - VCCIO VCCIO// 0, 6, 7 VCC_.V VCC_.V - NC NC - PLA / L_GPLLT_FB PLA / L_GPLLT_FB 6 PLB / L_GPPLC_FB PLB / L_GPPLC_FB 7 PLC / L_GPLLT_IN PLA / L_GPLLT_IN 8 PLD / L_GPLLC_IN PLB / L_GPLLC_IN 9 PLA / PCLKT_ PL6A / PCLKT_0 0 PLB / PCLKC_ PL6B / PCLKC_0 6 PLC PL8A 9 PLD PL8B 0 - - PLA PL9A 6 PLB PL9B 7 PLC PL0A 8 PLD PL0B 9-0 - PLA / PCLKT_ PLA / PCLKT_0 9 PLB / PCLKC_ PLB / PCLKC_0 0 PLC PLA PLD PLB - 6-7 PL8A PL7A 8 PL8B PL7B 9 PL8C PL9A 0 PL8D PL9B 6 - - PL9A / PCLKT_0 PLA / PCLKT_0 7 PL9B / PCLKC_0 PLB / PCLKC_0 8-6 - 7 PL0A PLA 8 PL0B PLB 9 PL0C PLA 0 PL0D PLB 0
MachXO Breakout Board Table 6. Expansion Header Pin Information (J) Header Pin Number -00ZE Function -7000HE Function MachXO Pin NC NC - VCCIO VCCIO 7,, 66 PB0D / SI / SISPI PB8B / SI / SISPI 7 PB0B PB7B 69 PB0C / SN PB8A / SN 70 6 PB0A PB7A 68 7 PB8D PBB 67 8 PB8B PBB 6 9 PB8C PBA 6 0 PB8A PBA 6 - - PBD PB9B 60 PBB PB6B 8 PBC PB9A 9 6 PBA PB6A 7 7-8 - 9 PBB / PCLKC_ PBB / PCLKC_ 6 0 PBD PB8B PBA / PCLKT_ PBA / PCLKT_ PBC PB8A - - PB9B / PCLKC_0 PB6B / PCLKC_0 0 6 PB9D PBB 8 7 PB9A / PCLKT_0 PB6A / PCLKT_0 9 8 PB9C PBA 7 9-0 - PB6D / S0 / SPISO PBB / S0 / SPISO PB6B PB9B PB6C / MCLK / CCLK PBA / MCLK / CCLK PB6A PB9A - 6-7 PBD PB6B 8 PBB PBB 9 9 PBC / CSSPIN PB6A / CSSPIN 0 0 PBA PBA 8
MachXO Breakout Board Figure. J/J Header Landing Callout J J NC IO0 09 0 7 9 0 6 7 8 0 6 7 8 9 0. IO. NC 6 9 0 9 0 6 7 8 Top Side LCMXO-7000HE TGC J J Figure. J/J Header Landing Callout J J Top Side LCMXO-7000HE TGC J J. IO. NC 7 7 76 7 78 77 8 8 8 8 86 8 9 9 9 9 96 9 98 97 00 99 0 0 07 06 NC IO 7 69 70 68 67 6 6 6 60 8 9 7 6 0 8 9 7 9 0 8
MachXO Breakout Board Figure 6. J Header Landing and LED Array Callout LED Array J. TDO TDI NC NC TMS GND TCK 8 J D8 D LED D8 D7 D6 D D D D D Function LED7 LED6 LED LED LED LED LED LED0 MachXO Pin 07 06 0 0 00 99 98 97 LCMXO-7000HE TGC Top Side MachXO FPGA The MachXO-7000HE-TGC is a -pin TQFP package FPGA device which provides up to usable I/Os in a 0 x 0mm package. 08 I/Os are accessible from the breakout board headers. Table 7. MachXO FPGA Interface Reference Item Reference Designators Part Number Manufacturer Web Site Description U LCMXO-7000HE-TGC Lattice Semiconductor www.latticesemi.com JTAG Interface Circuits For power and programming an FTDI USB UART/FIFO IC converter provides a communication interface between a PC host and the JTAG programming chain of the Breakout Board. The USB V supply is also used as a source for the.v supply rail. A USB mini-b socket is provided for the USB connector cable. Table 8. JTAG Interface Reference Item Reference Designators Part Number Manufacturer Web Site Description U FTHL Future Technology Devices International (FTDI) www.ftdichip.com
MachXO Breakout Board Table 9. JTAG Programming Pin Information Description Test Data Output Test Data Input Test Mode Select Test Clock 7:TDO 6:TDI 0:TMS :TCK MachXO Pin LEDs A green LED (D9) is used to indicate USB V power. Eight red LEDs are driven by I/O pins of the MachXO device. Table 0. Power and User LEDs Reference Item Reference Designators Part Number Manufacturer Web Site Description D, D, D, D, D, D6, D7, D8, D9 LTST-C90KRKT (D-D8) LTST-C90KGKT (D9) Lite-On It Corporation www.liteonit.com Power Supply.V and.v power supply rails are converted from the USB V interface when the board is connected to a host PC. Test Points In order to check the various voltage levels used, test points are provided: TP: +.V TP: +.V TP: GND USB Programming and Debug Interface The USB mini-b socket of the Breakout Board serves as the programming and debug interface. JTAG Programming: For JTAG programming, a preprogrammed USB PHY peripheral controller is provided on the Breakout Board to serve as the programming interface to the MachXO FPGA. Programming requires the Lattice Diamond or ispvm System software. Table. USB Interface Reference Item Reference Designators Part Number Manufacturer Web Site Description U FTHL Future Technology Devices International (FTDI) www.ftdichip.com
Board Modifications This section describes modifications to the board to change or add functionality. MachXO Breakout Board Bypassing the USB Programming Interface The USB programming interface circuit (USB Programming and Debug Interface section) may be optionally bypassed by removing the 0 ohm resistors: R, R6, R7, R8 (See Appendix A. Schematics, Sheet of ). Header landing J provides JTAG signal access for jumper wires or a x8 pin header. Applying External Power The Breakout Board is powered by the circuit of Schematic Sheet of based on the V USB power source. You may disconnect this power source by removing the 0 ohm resistors: R (VCC_.V) and R (VCC_.V). Power connections are available from the expansion header landings, J (+.V, pins and, schematic sheet of ) and J (+.V, pins and, schematic sheet of ). Measuring Bank and Core Power In addition to the expansion headers, test points (TP, TP) provide access to power supplies of the MachXO FPGA. Inline ohm resistors: R (VCCIO0, +.V, Bank 0), R (VCCIO, +.V, Bank ), R6 (VCCIO, +.V, Bank ), R7 (VCCIO, +.V, Bank ), R6 (VCC core, +.V) can be used to measure current for the power supplies. Mechanical Specifications Dimensions: in. [L] x in. [W] x / in. [H] Environmental Requirements The evaluation board must be stored between -0 C and 00 C. The recommended operating temperature is between 0 C and 90 C. The board can be damaged without proper anti-static handling. Glossary FPGA: Field Programmable Gate Array DIP: Dual in-line package LED: Light Emitting Diode. LUT: Look Up Table PCB: Printed Circuit Board RoHS: Restriction of Hazardous Substances Directive USB: Universal Serial Bus WDT: Watchdog Timer Troubleshooting Use the tips in this section to diagnose problems with the Breakout Board. LEDs Do Not Flash If power is applied but the board does not flash according to the preprogrammed counter demonstration then it is likely the board has been reprogrammed with a new design. Follow the directions in the Demonstration Design section to restore the factory default.
MachXO Breakout Board USB Cable Not Detected If Lattice Diamond Programmer or ispvm System does not recognize the USB cable after installing the Lattice USB port drivers and rebooting, the incorrect USB driver may have been installed. This usually occurs if you attach the board to your PC prior to installing the Lattice-supplied USB driver. To access the Troubleshooting the USB Driver Installation Guide: For Diamond software and standalone Diamond Programmer:. Start Diamond or Diamond Programmer and choose Help.. Search for USB driver or Troubleshooting, then select the Troubleshooting the USB Driver topic.. Follow the directions to install the Lattice USB driver. For ispvm:. Start ispvm System and choose Options > Cable and I/O Port Setup. The Cable and I/O Port Setup Dialog appears.. Click the Troubleshooting the USB Driver Installation Guide link. The Troubleshooting the USB Driver Installation Guide document appears in your system s PDF file reader.. Follow the directions to install the Lattice USB driver. Determine the Source of a Pre-Programmed Device If the Breakout Board has been reprogrammed, the original demo design can be restored. To restore the board to the factory default, see the Download Demo Designs section for details on downloading and reprogramming the device. Ordering Information Description Ordering Part Number China RoHS Environment-Friendly Use Period (EFUP) MachXO-7000HE Breakout Board Evaluation Kit LCMXO-7000HE-B-EVN MachXO Breakout Board Evaluation Kit LCMXO-00ZE-B-EVN.For reference only. This version of the board is no longer available for sale. Technical Support Assistance Hotline: -800-LATTICE (North America) +-0-68-800 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com 6
MachXO Breakout Board Revision History Date Version Change Summary December 0 0.0 Initial release. January 0 0. Figure MachXO-00ZE Breakout Board, Top Side updated with revision B board photo. December 0 0. Updated document to describe new version of the board featuring the MachXO-7000HE. Indicated that the MachXO-00ZE version of the board is no longer available. February 0 0.0 Updated Tables -6 to include -7000HE information. Added -7000HE notes to Figure and Appendix A. 0 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 7
Appendix A. Schematics MachXO Breakout Board Note: The schematics are drawn using the MachXO-00ZE device. Please consult Tables through 6 for -00 and -7000HE pin name and bank synonyms. Pin numbers are correct for either device. Figure 7. Block Diagram D D JTAG HEADER LEDS(-8) I/Os + IC BANK 0 I/Os C C HEADER HEADER I/Os + SPI BANK FPGA BANK RS LCMXO-7000HE-TGC or LCMXO-00ZE-TGC USB to JTAG / RS BANK Power from USB V USB CONNECTOR I/Os HEADER B B A A AXELSYS Title Lattice MachXO 00ZE Breakout Board - Block Diagram Size Document Number Rev B LCMXO-7000HE-B-EVN or LCMXO-00ZE-B-EVN A Thursday, April, 0 Date: Sheet of 8
MachXO Breakout Board Figure 8. USB Interface to JTAG +.V +.V 600ohm 00mA +.V L TCK R C C u7 R R R 0.uF k k k k D L D TMS 600ohm 00mA C C TDI u7 +.V 0.uF TDO +.V VCC_8FT +.V C C8 C6 C9 C7 6 R TCK 0 ADBUS0 7 R6 TDI 0.uF 0.uF 0.uF 0.uF 0.uF VREGIN ADBUS 8 R7 C TDO C 9 ADBUS 9 R8 VREGOUT ADBUS TMS ADBUS ADBUS DM DM ADBUS6 DP DP ADBUS7 C0 C k R9 6 ACBUS0 7 0uF 0.uF RESET# ACBUS 8 +.V R0 k % ACBUS 9 ACBUS 0 +.V REF ACBUS ACBUS R R R ACBUS6 0k 0k 0k FT_EECS 6 ACBUS7 FT_EECLK 6 EECS 8 0 DNI R RS_Rx_TTL U FT_EEDATA 6 EECLK BDBUS0 9 0 DNI R EEDATA RS_Tx_TTL 8 BDBUS 0 0 DNI R6 RTSn 7 VCC CS BDBUS 0 DNI R7 FOR FUTURE RS FUNCTION BDBUS CTSn 6 NU CLK 0 DNI R8 OSCI BDBUS DTRn C ORG DI 0 DNI R0 VSS DO DSRn R9 k BDBUS 0 DNI R X BDBUS6 DCDn 0.uF 9LC6-SO8 6 BDBUS7 B B OSCO 8 BCBUS0 C G G C BCBUS 8pF BCBUS 8pF MHZ TEST BCBUS BCBUS 7 BCBUS FTDI High-Speed USB 8 BCBUS6 9 BCBUS7 U FTHL FTH VCC_8FT +.V TDO TDI TMS TCK A A AXELSYS Title Lattice MachXO 00ZE Breakout Board -USB to JTAG Size Document Number Rev LCMXO-00ZE-B-EVN A B Thursday, April, 0 Date: Sheet of 7 8 6 0 0 0 0 0 7 AGND GND GND GND GND GND GND GND GND VPHY VPLL VCORE VCORE VCORE 9 7 6 VCCIO 0 VCCIO VCCIO VCCIO 6 PWREN# SUSPEND# 60 6 J header_x8 DNI 6 7 8 6 7 8 9
MachXO Breakout Board Figure 9. FPGA +.V R R VCCIO VCC_.V VCCIO0 MAKE PWR TRACES k k D CAPABLE OF A C C6 D MAKE PWR TRACES U- CAPABLE OF A 0.uF 0.uF J BANK 0 BANK PT7D_DONE 09 PR0D RS_Rx_TTL J PT7C_INITn 0 PT7D/DONE PR0D 7 PR0C RS_Tx_TTL PT7B PT7C/INITn PR0C 7 7 PR0B RTSn PT7C_INITn PT7D_DONE PT7A PT7B PR0B 76 PR0A PT7A PT7B PT7A PR0A CTSn PT6D PR9D PR0D PR0C DSRn PT6C 0 PT6D PT6C PT6D PR9D 77 PR9C PR0B PR0A DCDn PT6A PT6B PT6B PT6C PR9C 78 8 PR9B DTRn 0 PTC_JTAGen PTD_PROGn PT6A 7 PT6B PR9B 8 PR9A PR9D PR9C 6 PT6A PR9A PR9B PR9A PTA 8 7 PTB PTD_PROGn 9 PR8D 6 PTC_SCL_PCLT0_0 0 9 PTD_SDA_PCLKC0_0 PTC_JTAGen 0 PTD/PROGRAMn PR8D 8 PR8C PR8D 8 7 PR8C PTA_PCLKT0_ PTB_PCLKC0_ PTB PTC/JTAGENB PR8C 8 8 PR8B PR8B 0 9 PR8A PTA PTB PR8B 86 PR8A PTC_TCK_TESTCLK 6 PTD_TMS PTA PR8A PCLKC_PRD PCLKT_PRC PTA 8 7 PTB PTD_SDA_PCLKC0_0 87 PRB 6 PRA PT0C_TDO 0 9 PT0D_TDI PTC_SCL_PCLT0_0 6 PTD/SDA/PCLKC0_0 NC 89 8 7 PTB_PCLKC0_ 7 PTC/SCL/PCLKT0_0 NC PRD 0 9 PRC PT0A PT0B PTA_PCLKT0_ 8 PTB/PCLKC0_ PCLKC_PRD PRB PRA C C PT9C 6 PT9D PTA/PCLKT0_ PCLKC_0/PRD 9 PCLKT_PRC PT9A 8 7 PT9B TMS PTD_TMS 0 PCLKT_0/PRC 9 9 PRB PRB 6 PRA 0 9 TCK PTC_TCK_TESTCLK PTD/TMS PRB 9 PRA PRD 8 7 PRC PTB PTC/TCK/TEST_CLK PRA PRB 0 9 PRA PTA PTB PRD PTA PRD 9 PRC Headerx0 TDI PT0D_TDI 6 PRC 96 97 PRB LED0 DNI TDO PT0C_TDO 7 PT0D/TDI PRB 98 PRA LED Headerx0 PT0B 8 PT0C/TDO PRA DNI PT0A 9 PT0B 99 PRB PT0A PRB LED 00 PRA LED PT9D 0 PRA PT9C PT9D 0 PT9B PT9C NC6 PT9A PT9B PRD PT9A PRD 0 LED PRC PRC 0 LED 06 PRB PRB LED6 07 PRA VCCIO0 PRA LED7 VCCIO 8 79 C7 VCCIO0 VCCIO 88 C B C8 C9 C0 VCCIO0 VCCIO 0 C C C B VCCIO0 VCCIO 0.0uF 0.uF 0.uF 0.uF LCMXO-7000HE-TGC or LCMXO-00ZE-TGC 0.0uF 0.uF 0.uF 0.uF +.V VCCIO0 +.V VCCIO R R A A AXELSYS Title Lattice MachXO 00ZE Breakout Board - FPGA Document Number Size Rev LCMXO-00ZE-B-EVN A B Thursday, April, 0 Date: Sheet of 6 8 7 9 6 8 7 9 0
MachXO Breakout Board Figure 0. FPGA VCCIO VCC_.V VCCIO D MAKE PWR TRACES C C6 U- D CAPABLE OF A MAKE PWR TRACES 0.uF 0.uF BANK BANK CAPABLE OF A PLA_L_GPLLT_FB 8 PBA J J PLB_L_GPPLC_FB PLA/L_GPLLT_FB PBA 9 PBB PLC_L_GPLLT_IN PLB/L_GPPLC_FB PBB CSSPIN_PBC PLD_L_GPLLC_IN PLC/L_GPLLT_IN CSSPIN/PBC 0 PBD PLD/L_GPLLC_IN PBD PB0B SI_SISPI_PB0D PLA_PCLKT_ PB6A PB0A SN_PB0C PLB_L_GPPLC_FB PLA_L_GPLLT_FB PLB_PCLKC_ PLA/PCLKT_ PB6A PB6B PB8B PB8D PLD_L_GPLLC_IN PLC_L_GPLLT_IN PLC PLB/PCLKC_ PB6B MCLK_CCLK_PB6C PB8A 0 PB8C PLB_PCLKC_ PLA_PCLKT_ PLD 0 PLC MCLK/CCLK/PB6C 0 S0_SPISO_PB6D PLD PLC PLD SO/SPISO/PB6D PBB PBD PLA PB9C PBA 6 PBC PLB PLA PLB PLA PB9C 7 6 PB9D 8 7 PLD PLC PLC PLB PB9D 8 8 7 9 PCLKT_0_PB9A PBD 0 9 PCLKC_PBB 0 9 PLD PLC PCLKT_0/PB9A 0 PCLKC_0_PB9B PBC PCLKT_PBA PLB_PCLKC_ PLA_PCLKT_ PLD PCLKC_0/PB9B PLD PLC 7 NC0 PBC PB9D 6 PCLKC_0_PB9B NC PBC 6 PBD PB9C 8 7 PCLKT_0_PB9A PL8B PL8A PLA_PCLKT_ 9 PBD 8 7 PCLKT_PBA 0 9 PL8D 0 9 PL8C PLB_PCLKC_ 0 PLA/PCLKT_ PCLKT_/PBA 6 PCLKC_PBB PB6B S0_SPISO_PB6D PLC PLB/PCLKC_ PCLKC_/PBB PB6A MCLK_CCLK_PB6C PL9B_PCLKC_0 PL9A_PCLKT_0 PLD PLC 7 PBA 6 C PLD C 6 PBA 8 PBB PBB 8 7 PBD PL0B 8 7 PL0A PL8A PBB PBC PBA 0 9 CSSPIN_PBC PL0D PL0C PL8B PL8A PBC 9 0 9 PBD PL8C PL8B PBD 60 PL8D 6 PL8C 6 PB8A PL8D PB8A 6 PB8B Headerx0 Headerx0 PL9A_PCLKT_0 7 PB8B 6 DNI DNI PL9B_PCLKC_0 8 PL9A/PCLKT_0 NC PB8C PL9B/PCLKC_0 PB8C 6 PB8D NC PB8D 67 PL0A 68 PB0A PL0B PL0A PB0A 69 PB0B PL0C PL0B PB0B SN_PB0C PL0D SI_SISPI_PB0D PL0D PL0C 70 SI/SISPI/PB0D 7 SN/PB0C 70 VCCIO VCCIO +.V VCCIO +.V VCCIO 7 C7 6 VCCIO VCCIO C C8 C9 C0 0 VCCIO VCCIO 66 C C C R6 R7 VCCIO VCCIO 0.0uF 0.uF 0.uF 0.uF 0.0uF 0.uF 0.uF 0.uF LCMXO-7000HE-TGC or LCMXO-00ZE-TGC B B PL0A NOTE PLACE ALL 00 OHM DIFF TERM RESISTORS ON BOTTOM OF BOARD R This is optional to enable or disable the crystal. DNI X EN Vcc GND Output +.V C 0.uF PL9A_PCLKT_0 PBA PBB CSSPIN_PBC PBD PB6A PB6B MCLK_CCLK_PB6C S0_SPISO_PB6D R8 DNI 00 R0 DNI 00 R DNI 00 R DNI 00 PBA PBB PBC PBD PB8A PB8B PB8C PB8D R9 DNI 00 R DNI 00 R DNI 00 R DNI 00 CBLV-C-0M0000 PB9C DNI R6 00 PB0A DNI R7 00 PB9D PB0B 0MHz OSC A A PCLKT_0_PB9A DNI R8 00 SN_PB0C DNI R9 00 PCLKC_0_PB9B SI_SISPI_PB0D AXELSYS PBC DNI R0 00 PBD Title Lattice MachXO 00ZE Breakout Board - FPGA PCLKT_PBA DNI R 00 PCLKC_PBB Size Document Number Rev B LCMXO-00ZE-B-EVN A Thursday, April, 0 Date: Sheet of 0 6 8 7 9 6 9 7 6 8 7 9
MachXO Breakout Board Figure. Power LEDs +.V +.V VCC_.V +.V VBUS_V U FAN R 0 L R6 C C6 C7 C8 C9 C0 C C C C C Input Output 600ohm 00mA C6 0uF uf 0.uF 0.uF 0.uF 0.uF 0.0uF 0uF uf 0.uF 0.0uF C7 0uF Tab R D uf D 00 +.V U- DNI DNI DNI 9 GND 8 TP TP TP VCCP GND 8 VCC_.V +.V GND 9 VBUS_V +.V +.V 6 GND 6 7 VCC GND U 08 VCC GND 6 R 0 L VCC GND 80 R IN OUT VCC GND 90 600ohm 00mA GND 0 K TAB C8 GND 6 D9 C9 C0 GND GND Green 0uF GND uf 0.uF NCP7 C LCMXO-00ZE-TGC C +.V LEDs VBUS_V B B Proto Type Area STATUS_LED7 STATUS_LED6 STATUS_LED STATUS_LED STATUS_LED STATUS_LED STATUS_LED STATUS_LED0 DM DP LED7 LED6 LED LED LED LED LED LED0 A A X PROTOTYPE AREA AXELSYS Title Lattice MachXO 00ZE Breakout Board - Power, LEDs Document Number Rev Size LCMXO-00ZE-B-EVN A B Thursday, April, 0 Date: Sheet of Proto Type Area, Holes on 0. inch Centers GND L R R6 R7 R8 R9 R0 R R C K K K K K K K K 0.uF 600ohm 00mA J7 VCC D- D+ ID GND SKT_MINIUSB_B_RA R 0 C 0.uF D8 D7 D6 D D D D D J6 LAYOUT LEDs IN A SINGLE ROW Red Red Red Red Red Red Red Red
Appendix B. Bill of Materials Table. MachXO Breakout Board Bill of Materials MachXO Breakout Board Item Quantity Reference Manufacturer Part Number C, C Panasonic ECJ-VB0J7K C, C, C, C6, C7, C8, C9, C, C, C, C6, C8, Kemet C00C0KRACTU C9, C0, C, C, C, C, C6, C8, C9, C0, C, C, C, C7, C8, C9, C0, C, C0, C, C, C C0, C, C, C6, C8 Taiyo Yuden LMK07BJ06MALTD C, C Kemet C00C80KGACTU 6 C7, C, C7, C, C, C Kemet C00C0JRACTU 6 C6, C Kemet C00C0K9PACTU 7 C7, C9 Taiyo Yuden LMKBJ6MG-T 8 8 D, D, D, D, D, D6, D7, D8 LITE-On, Inc. LTST-C90KRKT 9 D9 LITE-On, Inc. LTST-C90KGKT 0 J Molex -8-08 J, J, J, J Samtec J6 J7 Neltron 07BMR-0-SM-CR L, L, L, L, L Murata BLM8AG60SND R, R, R Yageo RC00FR-07KL 6 R, R9, R9, R, R Yageo RC00FR-07KL 7 8 R, R6, R7, R8, R, R, R, R Yageo RC060JR-070RL 8 R0 Yageo RC00FR-07KL 9 R, R, R Yageo RC00FR-070KL 0 7 R, R, R6, R7, R8, R0, R Yageo RC060JR-070RL R, R, R6, R7, R6 Vishay/Dale CRCW060R00JNEAHP R8, R9, R0, R, R, R, R, R, R6, R7, R8, Yageo RC060FR-0700RL R9, R0, R 9 R, R, R6, R7, R8, R9, R0, R, R Yageo RC00FR-07KL R Yageo RC060FR-0700RL TP, TP, TP 6 U FTDI FTHL 7 U Microchip 9LC6C-I/SN 8 U Lattice LCMXO-7000HE-TGC or LCMXO-00ZE-TGC 9 U Fairchild Semi FANSX 0 U On Semi NCP7STTG X TXC 7M-.000MAAJ-T X CTS CBLV-C-0M0000