Precision High-Speed Difet OPERATIONAL AMPLIFIERS

Precision High-Speed Difet OPERATIONAL AMPLIFIERS FEATURES VERY LOW NOISE: 4.5nV/ Hz at khz FAST SETTLING TIME: 55ns to.% 45ns to.% LOW V OS : µv max LOW DRIFT:.8µV/ C max LOW I B : 5pA max : Unity-Gain Stable : Stable in Gain 5 DESCRIPTION The and Difet operational amplifiers provide a new level of performance in a precision FET op amp. When compared to the popular OPA op amp, the /7 has lower noise, lower offset voltage, and much higher speed. It is useful in a broad range of precision and high speed analog circuitry. The /7 is fabricated on a high-speed, dielectrically-isolated complementary NPN/PNP process. It operates over a wide range of power supply voltage ±4.5V to ±8V. Laser-trimmed Difet input circuitry provides high accuracy and low-noise performance comparable with the best bipolar-input op amps. APPLICATIONS PRECISION INSTRUMENTATION FAST DATA ACQUISITION DAC OUTPUT AMPLIFIER OPTOELECTRONICS SONAR, ULTRASOUND HIGH-IMPEDANCE SENSOR AMPS HIGH-PERFORMANCE AUDIO CIRCUITRY ACTIVE FILTERS High frequency complementary transistors allow increased circuit bandwidth, attaining dynamic performance not possible with previous precision FET op amps. The is unity-gain stable. The is stable in gains equal to or greater than five. Difet fabrication achieves extremely low input bias currents without compromising input voltage noise performance. Low input bias current is maintained over a wide input common-mode voltage range with unique cascode circuitry. The /7 is available in plastic DIP, SOIC and metal TO-99 packages. Industrial and military temperature range models are available. Trim Trim 5 7 V S Output In In Difet, Burr-Brown Corp. V S 4 International Airport Industrial Park Mailing Address: PO Box 4, Tucson, AZ 8574 Street Address: 7 S. Tucson Blvd., Tucson, AZ 857 Tel: (5) 74- Twx: 9-95- Internet: http://www.burr-brown.com/ FAXLine: (8) 548- (US/Canada Only) Cable: BBRCORP Telex: -49 FAX: (5) 889-5 Immediate Product Info: (8) 548-989 Burr-Brown Corporation PDS-998H Printed in U.S.A. March, 998 SBOS5

SPECIFICATIONS ELECTRICAL At T A = 5 C, and V S = ±5V, unless otherwise noted. BM, BP, SM AM, AP, AU BM, BP, SM AM, AP, AU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS OFFSET VOLTAGE () Input Offset Voltage 4 5 µv AP, BP, AU Grades 5 8 5 µv Average Drift.4.8. µv/ C AP, BP, AU Grades.8.5 µv/ C Power Supply Rejection V S = ±4.5 to ±8V db INPUT BIAS CURRENT () Input Bias Current V CM = V 5 pa Over Specified Temperature V CM = V na SM Grade V CM = V 5 na Over Common-Mode Voltage V CM = ±V pa Input Offset Current V CM = V.5 5 pa Over Specified Temperature V CM = V na SM Grade 5 na NOISE Input Voltage Noise Noise Density: f = Hz 5 4 nv/ Hz f = Hz 8 nv/ Hz f = khz 5. 8 5. nv/ Hz f = khz 4.5 4.8 nv/ Hz Voltage Noise, BW =.Hz to Hz...8 µvp-p Input Bias Current Noise Noise Density, f = Hz..5.5 fa/ Hz Current Noise, BW =.Hz to Hz 48 fap-p INPUT IMPEDANCE Differential 8 * Ω pf Common-Mode 7 * Ω pf INPUT VOLTAGE RANGE Common-Mode Input Range ± ±.5 * * V Over Specified Temperature ±.5 ± * * V Common-Mode Rejection V CM = ±.5V db OPEN-LOOP GAIN Open-Loop Voltage Gain V O = ±V, R L = kω db Over Specified Temperature V O = ±V, R L = kω 7 db SM Grade V O = ±V, R L = kω 4 db FREQUENCY RESPONSE Slew Rate: G =, V Step 4 55 * * V/µs G = 4, V Step 5 * * V/µs Settling Time:.% G =, V Step 55 * ns.% G =, V Step 45 * ns.% G = 4, V Step 45 * ns.% G = 4, V Step * ns Gain-Bandwidth Product: G = * MHz G = 8 * MHz Total Harmonic Distortion Noise G =, f = khz. * % POWER SUPPLY Specified Operating Voltage ±5 * V Operating Voltage Range ±4.5 ±8 * * V Current ±7 ±7.5 * * ma OUTPUT Voltage Output R L = kω ±.5 ±. * * Over Specified Temperature ± ±.5 * * V Current Output V O = ±V ±45 * ma Short-Circuit Current ±5 7/55 ± * * * ma Output Impedance, Open-Loop MHz 55 * Ω TEMPERATURE RANGE Specification: AP, BP, AM, BM, AU 5 85 * * C SM 55 5 C Storage: AM, BM, SM 5 * * C AP, BP, AU 4 5 * * C θ J-A : AM, BM, SM * C/W AP, BP * C/W AU C/W * Specifications same as B grade. NOTES: () Offset voltage measured fully warmed-up. () High-speed test at T J = 5 C. See Typical Performance Curves for warmed-up performance. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems., 7

PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS () Top View Offset Trim In In V S 4 8 7 5 DIP/SOIC No Internal Connection VS Output Offset Trim Supply Voltage... ±8V Input Voltage Range... V S V to V S V Differential Input Range... Total V S 4V Power Dissipation... mw Operating Temperature M Package... 55 C to 5 C P, U Package... 4 C to 5 C Storage Temperature M Package... 5 C to 5 C P, U Package... 4 C to 5 C Junction Temperature M Package... 75 C P, U Package... 5 C Lead Temperature (soldering, s)... C SOlC (soldering, s)... C Top View Offset Trim No Internal Connection 8 7 V S TO-99 NOTE: () Stresses above these ratings may cause permanent damage. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER () RANGE In 5 Output AP Plastic DIP 5 C to 85 C BP Plastic DIP 5 C to 85 C AU SOIC 8 5 C to 85 C AM TO-99 Metal 5 C to 85 C BM TO-99 Metal 5 C to 85 C SM TO-99 Metal 55 C to 5 C In Case connected to V S. 4 V S Offset Trim AP Plastic DIP 5 C to 85 C BP Plastic DIP 5 C to 85 C AU SOIC 8 5 C to 85 C AM TO-99 Metal 5 C to 85 C BM TO-99 Metal 5 C to 85 C SM TO-99 Metal 55 C to 5 C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book., 7

TYPICAL PERFORMANCE CURVES At T A = 5 C, and V S = ±5V, unless otherwise noted. INPUT VOLTAGE NOISE SPECTRAL DENSITY TOTAL INPUT VOLTAGE NOISE vs BANDWIDTH k Voltage Noise (nv/ Hz) Input Voltage Noise (µv). Noise Bandwidth:.Hz to indicated frequency. RMS p-p k k k M M Frequency (Hz). k k k M M Bandwidth (Hz) VOLTAGE NOISE vs SOURCE RESISTANCE OPEN-LOOP GAIN vs FREQUENCY k 4 Voltage Noise (nv/ Hz) R S Resistor Resistor Noise Only Comparison with OPA7 Bipolar Op Amp Resistor Spot Noise at khz Voltage Gain (db) 8 4 k k k M M M k k k M M M Source Resistance ( Ω) Frequency (Hz) GAIN/PHASE vs FREQUENCY 9 GAIN/PHASE vs FREQUENCY 9 Gain (db) Gain 75 Phase Margin Phase 5 Phase (Degrees) Gain (db) Gain Phase 5 Phase (Degrees) 8 8 Frequency (MHz) Frequency (MHz), 7 4

TYPICAL PERFORMANCE CURVES (CONT) At T A = 5 C, and V S = ±5V, unless otherwise noted. 5 OPEN-LOOP GAIN vs TEMPERATURE OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY Voltage Gain (db) 5 Output Resistance (Ω) 8 4 5 75 5 5 5 5 75 5 k k k M M Temperature ( C) Frequency (Hz) COMMON-MODE REJECTION vs FREQUENCY COMMON-MODE REJECTION vs INPUT COMMON MODE VOLTAGE 4 Common-Mode Rejection Ratio (db) 8 4 Common-Mode Rejection (db) 9 8 k k k M M 5 5 5 5 Frequency (Hz) Common-Mode Voltage (V) 4 POWER-SUPPLY REJECTION vs FREQUENCY 5 POWER-SUPPLY REJECTION AND COMMON-MODE REJECTION vs TEMPERATURE Power-Supply Rejection (db) 8 4 V S PSRR 7 7 V S PSRR 7 and 7 CMR and PSR (db) 5 PSR CMR k k k M M 5 75 5 5 5 5 75 5 Frequency (Hz) Temperature ( C) 5, 7

TYPICAL PERFORMANCE CURVES (CONT) At T A = 5 C, and V S = ±5V, unless otherwise noted. 8 SUPPLY CURRENT vs TEMPERATURE OUTPUT CURRENT LIMIT vs TEMPERATURE Supply Current (ma) 7.5 7.5 Output Current (ma) 8 4 I L at V O = V I L at V O = V I L at V O = V I L at V O = V 75 5 5 5 5 75 5 Temperature ( C) 75 5 5 5 5 75 5 Temperature ( C) 4 GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE Slew Rate Gain-Bandwidth (MHz) GBW Slew Rate 55 Slew Rate (V/µs) Gain-Bandwidth (MHz) 8 GBW 4 Slew Rate (V/µs) 8 75 5 5 5 5 5 75 5 Temperature ( C) 4 75 5 5 5 5 75 5 Temperature ( C) 8 THDN (%)... TOTAL HARMONIC DISTORTION NOISE vs FREQUENCY G = G = V I V O = ±V V I V O = ±V Ω Ω pf 5kΩ pf Measurement BW: 8kHz 549Ω G = THDN (%).. TOTAL HARMONIC DISTORTION NOISE vs FREQUENCY G = V I 549Ω 5kΩ V O = ±V Ω pf Measurement BW: 8kHz V I G = 5 Ω 5kΩ G = 5 V O = ±V Ω pf. G =.. k k k Frequency (Hz) G =. k k k Frequency (Hz), 7

TYPICAL PERFORMANCE CURVES (CONT) At T A = 5 C, and V S = ±5V, unless otherwise noted. k INPUT BIAS AND OFFSET CURRENT vs JUNCTION TEMPERATURE INPUT BIAS CURRENT vs POWER SUPPLY VOLTAGE Input Current (pa) k I B I OS Input Bias Current (pa) 5 5 NOTE: Measured fully warmed-up. TO-99 Plastic DIP, SOIC. 5 5 5 5 75 5 5 Junction Temperature ( C) TO-99 with 87HS Heat Sink ±4 ± ±8 ± ± ±4 ± ±8 Supply Voltage (±V S ). INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE 5 INPUT OFFSET VOLTAGE WARM-UP vs TIME Input Bias Current Multiplier..9 Beyond Linear Common-Mode Range Beyond Linear Common-Mode Range Offset Voltage Change (µv) 5 5.8 5 5 5 5 Common-Mode Voltage (V) 5 4 5 Time From Power Turn-On (Min) MAX OUTPUT VOLTAGE vs FREQUENCY SETTLING TIME vs CLOSED-LOOP GAIN Output Voltage (Vp-p) Settling Time (µs) Error Band: ±.% k M M M Frequency (Hz). Closed-Loop Gain (V/V) 7, 7

TYPICAL PERFORMANCE CURVES (CONT) At T A = 5 C, and V S = ±5V, unless otherwise noted. 5 SETTLING TIME vs ERROR BAND C F SETTLING TIME vs LOAD CAPACITANCE Settling Time (ns) 5 R I RF kω 5V 5V R I kω R F kω C F pf 5Ω kω 4pF G = Settling Time (µs) Error Band: ±.% G = 4 G = G = 4... Error Band (%) 5 4 5 Load Capacitance (pf) APPLICATIONS INFORMATION The is unity-gain stable. The may be used to achieve higher speed and bandwidth in circuits with noise gain greater than five. Noise gain refers to the closed-loop gain of a circuit as if the non-inverting op amp input were being driven. For example, the may be used in a non-inverting amplifier with gain greater than five, or an inverting amplifier of gain greater than four. When choosing between the or, it is important to consider the high frequency noise gain of your circuit configuration. Circuits with a feedback capacitor (Figure ) place the op amp in unity noise-gain at high frequency. These applications must use the for proper stability. An exception is the circuit in Figure, where a small feedback capacitance is used to compensate for the input capacitance at the op amp s inverting input. In this case, the closed-loop noise gain remains constant with frequency, so if the closed-loop gain is equal to five or greater, the may be used. Buffer Bandwidth Limiting Integrator R I R I R F < 4R I R F < 4R Non-Inverting Amp G < 5 Inverting Amp G < 4 Filter FIGURE. Circuits with Noise Gain Less than Five Require the for Proper Stability., 7 8

OFFSET VOLTAGE ADJUSTMENT The /7 is laser-trimmed for low offset voltage and drift, so many circuits will not require external adjustment. Figure shows the optional connection of an external potentiometer to adjust offset voltage. This adjustment should not be used to compensate for offsets created elsewhere in a system (such as in later amplification stages or in an A/D converter) because this could introduce excessive temperature drift. Generally, the offset drift will change by approximately 4µV/ C for mv of change in the offset voltage due to an offset adjustment (as shown on Figure ). R C R C C = C IN C STRAY C = R C R FIGURE. Circuits with Noise Gain Equal to or Greater than Five May Use the. amp contributes little additional noise. Below kω, op amp noise dominates over the resistor noise, but compares favorably with precision bipolar op amps. CIRCUIT LAYOUT As with any high speed, wide bandwidth circuit, careful layout will ensure best performance. Make short, direct interconnections and avoid stray wiring capacitance especially at the input pins and feedback circuitry. The case (TO-99 metal package only) is internally connected to the negative power supply as it is with most common op amps. Pin 8 of the plastic DIP, SOIC, and TO-99 packages has no internal connection. Power supply connections should be bypassed with good high frequency capacitors positioned close to the op amp pins. In most cases.µf ceramic capacitors are adequate. The /7 is capable of high output current (in excess of 45mA). Applications with low impedance loads or capacitive loads with fast transient signals demand large currents from the power supplies. Larger bypass capacitors such as µf solid tantalum capacitors may improve dynamic performance in these applications. V S NOISE PERFORMANCE Some bipolar op amps may provide lower voltage noise performance, but both voltage noise and bias current noise contribute to the total noise of a system. The /7 is unique in providing very low voltage noise and very low current noise. This provides optimum noise performance over a wide range of sources, including reactive source impedances. This can be seen in the performance curve showing the noise of a source resistor combined with the noise of an. Above a kω source resistance, the op 7 4 V S kω 5 /7 kω to MΩ Potentiometer (kω preferred) ±mv Typical Trim Range FIGURE. Optional Offset Voltage Trim Circuit. Non-inverting Buffer In Out In Out In Inverting TO-99 Bottom View Board Layout for Input Guarding: Guard top and bottom of board. Alternate use Teflon standoff for sensitive input pins. Out 4 5 7 8 No Internal Connection Teflon E.I. du Pont de Nemours & Co. To Guard Drive FIGURE 4. Connection of Input Guard for Lowest I B. 9, 7

INPUT BIAS CURRENT Difet fabrication of the /7 provides very low input bias current. Since the gate current of a FET doubles approximately every C, to achieve lowest input bias current, the die temperature should be kept as low as possible. The high speed and therefore higher quiescent current of the /7 can lead to higher chip temperature. A simple press-on heat sink such as the Burr-Brown model 87HS (TO-99 metal package) can reduce chip temperature by approximately 5 C, lowering the I B to one-third its warmed-up value. The 87HS heat sink can also reduce lowfrequency voltage noise caused by air currents and thermoelectric effects. See the data sheet on the 87HS for details. Temperature rise in the plastic DIP and SOIC packages can be minimized by soldering the device to the circuit board. Wide copper traces will also help dissipate heat. The /7 may also be operated at reduced power supply voltage to minimize power dissipation and temperature rise. Using ±5V power supplies reduces power dissipation to one-third of that at ±5V. This reduces the I B of TO- 99 metal package devices to approximately one-fourth the value at ±5V. Leakage currents between printed circuit board traces can easily exceed the input bias current of the /7. A circuit board guard pattern (Figure 4) reduces leakage effects. By surrounding critical high impedance input circuitry with a low impedance circuit connection at the same potential, leakage current will flow harmlessly to the lowimpedance node. The case (TO-99 metal package only) is internally connected to V S. Input bias current may also be degraded by improper handling or cleaning. Contamination from handling parts and circuit boards may be removed with cleaning solvents and deionized water. Each rinsing operation should be followed by a -minute bake at 85 C. Many FET-input op amps exhibit large changes in input bias current with changes in input voltage. Input stage cascode circuitry makes the input bias current of the /7 virtually constant with wide common-mode voltage changes. This is ideal for accurate high inputimpedance buffer applications. PHASE-REVERSAL PROTECTION The /7 has internal phase-reversal protection. Many FET-input op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This is most often encountered in non-inverting circuits when the input is driven below V, causing the output to reverse into the positive rail. The input circuitry of the /7 does not induce phase reversal with excessive commonmode voltage, so the output limits into the appropriate rail. OUTPUT OVERLOAD When the inputs to the /7 are overdriven, the output voltage of the /7 smoothly limits at approximately.5v from the positive and negative power supplies. If driven to the negative swing limit, recovery takes approximately 5ns. When the output is driven into the positive limit, recovery takes approximately µs. Output recovery of the can be improved using the output clamp circuit shown in Figure 5. Diodes at the inverting input prevent degradation of input bias current. R I () HP 58-8 kω R F V I V S 5kΩ ZD 5kΩ V S V O Diode Bridge BB: PWS74- ZD : V IN9 Clamps output at V O = ±.5V FIGURE 5. Clamp Circuit for Improved Overload Recovery. CAPACITIVE LOADS As with any high-speed op amp, best dynamic performance can be achieved by minimizing the capacitive load. Since a load capacitance presents a decreasing impedance at higher frequency, a load capacitance which is easily driven by a slow op amp can cause a high-speed op amp to perform poorly. See the typical curves showing settling times as a function of capacitive load. The lower bandwidth of the makes it the better choice for driving large capacitive loads. Figure shows a circuit for driving very large load capacitance. This circuit s two-pole response can also be used to sharply limit system bandwidth. This is often useful in reducing the noise of systems which do not require the full bandwidth of the. G = R F R Optional Gain Gain > R R F kω pf C G = F R O BW MHz Ω C L 5nF For Approximate Butterworth Response: C F = R O C L R F >> R O R F f db = π R F R O C F C L FIGURE. Driving Large Capacitive Loads., 7

INPUT PROTECTION The inputs of the /7 are protected for voltages between V S V and V S V. If the input voltage can exceed these limits, the amplifier should be protected. The diode clamps shown in Figure 7a will prevent the input voltage from exceeding one forward diode voltage drop beyond the power supplies well within the safe limits. If the input source can deliver current in excess of the maximum forward current of the protection diodes, use a series resistor, R S, to limit the current. Be aware that adding resistance to the input will increase noise. The 4nV/ Hz theoretical thermal noise of a kω resistor will add to the 4.5nV/ Hz noise of the /7 (by the square-root of the sum of the squares), producing a total noise of nv/ Hz. Resistors below Ω add negligible noise. Leakage current in the protection diodes can increase the total input bias current of the circuit. The specified maximum leakage current for commonly used diodes such as the N448 is approximately 5nA more than a thousand times larger than the input bias current of the /7. Leakage current of these diodes is typically much lower and may be adequate in many applications. Light falling on the junction of the protection diodes can dramatically increase leakage current, so common glass-packaged diodes should be shielded from ambient light. Very low leakage can be achieved by using a diode-connected FET as shown. The N47A is specified at pa and its metal case shields the junction from light. Sometimes input protection is required on I/V converters of inverting amplifiers (Figure 7b). Although in normal operation, the voltage at the summing junction will be near zero (equal to the offset voltage of the amplifier), large input transients may cause this node to exceed V beyond the power supplies. In this case, the summing junction should be protected with diode clamps connected to ground. Even with the low voltage present at the summing junction, common signal diodes may have excessive leakage current. Since the reverse voltage on these diodes is clamped, a diode-connected signal transistor can be used as an inexpensive low leakage diode (Figure 7b). V S D D Optional R S V S I IN (a) D (b) D V O D: IN448 5nA Leakage N47A pa Leakage Siliconix = D: N94 = V O NC FIGURE 7. Input Protection Circuits. LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE FPO (A) (B) When used as a unity-gain buffer, large common-mode input voltage steps produce transient variations in input-stage currents. This causes the rising edge to be slower and falling edges to be faster than nominal slew rates observed in higher-gain circuits. G = FIGURE 8. Dynamic Performance, G =., 7

LARGE SIGNAL RESPONSE V OUT (V) (C) V OUT (V) (D) pf () When driven with a very fast input step (left), common-mode transients cause a slight variation in input stage currents which will reduce output slew rate. If the input step slew rate is reduced (right), output slew rate will increase slightly. NOTE: () Optimum value will depend on circuit board layout and stray capacitance at the inverting input. kω kω G = V OUT FIGURE 9. Dynamic Performance, G =. LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE V OUT (V) (E) V OUT (mv) FPO (F) 4pF () kω G = 5 5Ω V OUT NOTE: () Optimum value will depend on circuit board layout and capacitance at inverting input. FIGURE. Dynamic Response, G = 5., 7

/ R I kω Error Out HP- 58-85 C F kω 5V R I, R kω 5Ω C F pf 4pF Error Band ±.5mV ±.mv (.%) High Quality Pulse Generator 5Ω R I ±5V Out NOTE: C F is selected for best settling time performance depending on test fixture layout. Once optimum value is determined, a fixed capacitor may be used. 5V FIGURE. Settling Time and Slew Rate Test Circuit. In Gain = CMRR db Bandwidth MHz Input Common-Mode Range = ±5V R G Ω R F 5kΩ pf R F 5kΩ 5kΩ INA5 Differential Amplifier 5kΩ 5kΩ 5kΩ 5 Output In Differential Voltage Gain = R F /R G FIGURE. High Speed Instrumentation Amplifier, Gain =. In Gain = CMRR db Bandwidth 4kHz Input Common-Mode Range = ±V R G Ω R F 5kΩ pf R F 5kΩ kω INA Differential Amplifier kω kω kω 5 Output In Differential Voltage Gain = ( R F /R G ) FIGURE. High Speed Instrumentation Amplifier, Gain =. V I A R R R * OPA R 4 V O R L 5Ω for ±V Out This composite amplifier uses the OPA current-feedback op amp to provide extended bandwidth and slew rate at high closed-loop gain. The feedback loop is closed around the composite amp, preserving the precision input characteristics of the /7. Use separate power supply bypass capacitors for each op amp. *Minimize capacitance at this node. GAIN A R R R R 4 db SLEW RATE (V/V) OP AMP (Ω) (kω) (Ω) (kω) (MHz) (V/µs) 5.5 () 4.99 5 7 49.9 4.99 5 NOTE: () Closest /% value. FIGURE 4. Composite Amplifier for Wide Bandwidth., 7

PACKAGE OPTION ADDENDUM www.ti.com -Apr-9 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty AM NRND TO-99 LMC 8 Green (RoHS & Eco Plan () Lead/Ball Finish MSL Peak Temp () AP ACTIVE PDIP P 8 5 TBD Call TI Call TI APG4 ACTIVE PDIP P 8 5 TBD Call TI Call TI AU ACTIVE SOIC D 8 75 Green (RoHS & AU/K5 ACTIVE SOIC D 8 5 Green (RoHS & AU/K5E4 ACTIVE SOIC D 8 5 Green (RoHS & AUE4 ACTIVE SOIC D 8 75 Pb-Free (RoHS) AUG4 ACTIVE SOIC D 8 75 Green (RoHS & BM NRND TO-99 LMC 8 Green (RoHS & AU BP ACTIVE PDIP P 8 5 TBD Call TI Call TI BPG4 ACTIVE PDIP P 8 5 TBD Call TI Call TI SM NRND TO-99 LMC 8 Green (RoHS & AM NRND TO-99 LMC 8 Green (RoHS & AM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI AP ACTIVE PDIP P 8 5 Green (RoHS & APG4 ACTIVE PDIP P 8 5 Green (RoHS & AU ACTIVE SOIC D 8 75 Green (RoHS & AU/K5 ACTIVE SOIC D 8 5 Green (RoHS & AU/K5E4 ACTIVE SOIC D 8 5 Green (RoHS & AU AU AU AUE4 ACTIVE SOIC D 8 TBD Call TI Call TI AUG4 ACTIVE SOIC D 8 75 Green (RoHS & BM NRND TO-99 LMC 8 Green (RoHS & BM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI BP ACTIVE PDIP P 8 5 Green (RoHS & BPG4 ACTIVE PDIP P 8 5 Green (RoHS & SM NRND TO-99 LMC 8 Green (RoHS & () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. AU AU Level--C-8 HR Level--C-8 HR Level--C-8 HR Level--C-8 HR Level--C-8 HR Level--C-8 HR Level--C-8 HR Level--C-8 HR Level--C-8 HR Addendum-Page

PACKAGE OPTION ADDENDUM www.ti.com -Apr-9 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all substances, including the requirement that lead not exceed.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or ) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.% by weight in homogeneous material) () MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

PACKAGE MATERIALS INFORMATION www.ti.com -Mar-8 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Reel Diameter Width (mm) W (mm) A (mm) B (mm) K (mm) P (mm) AU/K5 SOIC D 8 5..4.4 5.. 8.. Q W (mm) Pin Quadrant Pack Materials-Page

PACKAGE MATERIALS INFORMATION www.ti.com -Mar-8 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AU/K5 SOIC D 8 5 4. 4. 9. Pack Materials-Page

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