What The Mainframe your Customer and Linux needs to know Technischer Hintergrund von z/ v Arwed Win with Tschoeke Linux on Systems Architect tschoeke@deibmcom It s usiness that Matters IM Virtualization Evolution 40 Jahre kontinuierliche Innovation Der IM Mainframe ist Pionier und Perfektionist auf dem Gebiet der Virtualisierung System i & p haben fortschrittliche Hypervisor mit PR/SM-ähnlicher Funktionalität Andere Server hinken mit ihren Virtualisierungsmechanismen nach S/360 /370 EXEC CP-67 Programmable Operator Hypervisor Control Program 158/168 /SP N-way assist microcode 9672 G2 - G6 z/ 9x21 3090 64-bit 308x /ESA 303x PR/SM QDIO Adapter ESA 4381 Interrupt Assist /XA /HPO EMIF FCP / SCSI 64 M real 31-bit Guest Lan Dynamic Stg Reconfig II HiperSockets instruction (DSR II) CMS pipelines Virtual Switch XEDIT Logical Virtual Partitioning Disk PER IUCV Advanced Paging Subsystem REXX TRACE TRAP Shared File System Resource Capping Z900 / z890 Integrated Facility For Linux (IFL) IRD Performance Toolkit AS/400 LPAR i & pseries LPAR Z990 / z890 DLPAR Z9 EC/C z zaaps ZIIPs zaaps ZIIPs Multiple Subchannel Sets Multiple Channel Sub- Systems other assists z N-Port Virtualization (NPVI) APV Micro-partitioning VIOS pave LPAR Group Capacity i/p 1967 1970 1980 1990 2000 2007 2 1
System z Virtualization Architecture HiperSockets & Virtual Networking and Switching Web SysAdmin Apache Test Sphere Tools Linux Linux CMS Linux & Assists z/ IFL Processors LPAR 1 I/O & Network WebSphere WLM z/os Processors Traditional OLTP and atch WLM z/os FTP Linux LPAR 2 LPAR 3 LPAR 4 Intelligent Resource Director (IRD) HW/ucode functions - & assist Processor Resource / System Manager (PR/SM) z/ Test z/os & Assists Multi-Dimensionale Virtualisierung HW: PR/SM (LPAR s) & SW: z ( s) Isolierte Umgebungen: EAL5 für PR/SM und EAL3+ für z/ Hochentwickelter Hypervisor Instruktion: Virtualsierung ist eingebaut, kein Add-On 10% der Integrierten Schaltkreise werden für Virtualisierung benutzt () Zeit- und Ereignisgesteuertes Dispatching SHARED ALL Architektur Jegliche virtuelle CPU kann auf jeder beliebigen physischen CPU betrieben werden Sharing ist bis auf 1 %-Ebene möglich Shared oder Dedizierter Pool an *CPUs Garantierte LPAR Kapazität Physische & Virtuelle Ressourcen (CPU, I/O und Hauptspeicher) können dynamisch innerhalb und entlang der LPARs angepasst werden LPAR Zoning: Jede LPAR hat eine 0-Origin Das erlaubt I/O-Zugirffe auf den Hauptspeicher einer LPAR ohne Hypervisor Eingriff z/ kann virtuelle Devices erschaffen, die physisch nicht vorhanden sind z/ hat raffinierte Scheduling-Algorithmen um das Gesamtsystem für Reaktion und Throughput zu optimieren 3 System z: Evolution of z/ z/ Version 5: High-Value Virtualization Technology Generating new business with Linux on System z Enabling growth for existing customers z/ V5 12/05 9/04 z/ V4 8/03 5/02 z/ V3 10/01 2/01 7/01 R2 R1 R4 R3 R1 R1 R2 6/07 R3 2008 R4 Future enhancements: - Hardware and I/O - Systems management - Linux/ synergies - High availability - Virtualization - Networking - Security 12/05 6/03 12/03 5/05 9/06 9/07 4/09 9/10 Service discontinued Withdrawn from marketing Currently marketed mm/yy Release GA date (top) The EAL3+ evaluated copy of z/ V51 is available as the Common Criteria Certification feature of z/ V52 z/ V52 will be withdrawn from marketing on June 15, 2007 mm/yy Service discontinuance date (bottom) Note: All statements regarding IM's plans, directions, and intent are subject to change or withdrawal without notice, and represent goals and objectives only 2
System z Interpretive Execution Advanced Technology for Virtual Server Hosting Start Interpretive Execution () instruction Establish the full architectural capabilities of an architecture for the guest Supports MULTIPLE architectures CONCURRENTLY for multiple guests Allows guests to run in NORMAL mode (no OS modifications needed/no TRAP ing) Reduces context switch time Multiple control register sets PR/SM AND z/ exploit No performance penalty for running z/ in an LPAR 5 How: Start Interpretive Execution () = Start Interpretive Execution, an instruction z/ (like the LPAR hypervisor) uses the instruction to run virtual processors for a given virtual machine has access to: A control block that describes the virtual processor state (registers, etc) The Dynamic Address Translation (DAT) tables for the virtual machine z/ gets control back from for various reasons: Page faults I/O channel program translation Privileged instructions (including CP system service calls) CPU timer expiration (dispatch slice) Other, including CP asking to get control for special cases CP can also shoulder tap from another processor to remove virtual processor from (perhaps to reflect an interrupt) 6 3
Classic Scheduler / Dispatcher Picture User goes idle Dispatch List DK D1 DK Dn Resources available (time slice and priority basis) Minor time slice expires other interrupt or intercept Elapsed time slice expires ready wait state Dormant list Eligible List DK E1 DK En User becomes runnable User logs off User logs on 7 asic Direct HW virtualization transparent to applications/os Logical CPU Program stream Application High Frequency Control that require emulation modifications Low Frequency Control that require emulation modifications Interception Guest leaves Modify Subchannel instruction, etc PRSM-LPAR or Hypervisor Dispatch Guest (establish architecture) Load, Store, Add, Move, etc Start Subchannel, Test Subchannel, etc Re-dispatch guest PRSM-LPAR or Hypervisor Physical CPU HW Interpretation Controls STATE Description Ucode Firmware High perform Interpretation Handling Assists Execution Unit Load Store Add SSCH TSCH MSCH System z with (Start Interpretive Execution) * System z runs ALWAYS in PR/SM-LPAR mode under * LPAR is the only game in town, meaning performance items and other functionalities is developed accordingly z invokes to run s ( under ) * Efficient for performance - and new version of OS and Hypervisor Positioning of System z & Intel/AMD System z: the requirement for the underlying HW support is NOT an issue for System z, - since the basic System z Architecture & HW design has implemented this for decades Intel and AMD is developing some virtualization HW support based on a similar structure like the architecture as it was externally documented 25 years ago The amount of HW and assist functionalities are seemingly rather limited at this point No under 8 4
A Dispatcher Run the virtual machine z/ - Flow Open interruption window (enable/disable) Check for pending simulation work Purge Machine Lookaside if scheduled I/O or external interruption handler Validate guest PSW Queued guest interruptions Enter console-function mode A Reflect if enabled Intercept enablement if disabled Detect guest wait state Load guest state into registers Enable I/O, external interruptions C Host interruption (disable on interruption) Interception - Disable interruptions - Save guest state Program interruption - Save guest state - Resolve fault or Reflect exception to guest I/O or external Interruption - Save guest state - Check for pending interseption - Process interruption Dispatcher (if pending Interception Indicated) Process interception from depending in interception code - interception - Program interruption - I/O or external request - Guest wait state - Simulate instruction - Simulate program interruption - Translate program interruption - Schedule interruption Scan C A Guest EndOp - Reflect per event or exigent machine check - Mark guest EndOp 9 Large Linux guest with z/ 52 Performance Informix database server Throughput 2 4 6 8 10 12 16 24 48 Linux (G) LPAR z/ 52 guest z/ 51 guest Large guests can now be run under z/ without special treatment in the Linux DASD driver SLES9, z/ 52 5
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