Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes December 2015 Notice: The Intel 64 and IA-32 architectures may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in the specification updates. Document Number: 252046-049
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Contents Revision History........................................... 4 Preface.................................................. 7 Summary Tables of Changes................................. 8 Documentation Changes..................................... 9 Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 3
Revision History Revision History Revision Description Date -001 Initial release November 2002-002 -003 Added 1-10 Documentation Changes. Removed old Documentation Changes items that already have been incorporated in the published Software Developer s manual Added 9-17 Documentation Changes. Removed Documentation Change #6 - References to bits Gen and Len Deleted. Removed Documentation Change #4 - VIF Information Added to CLI Discussion December 2002 February 2003-004 Removed Documentation changes 1-17. Added Documentation changes 1-24. June 2003 Removed Documentation Changes 1-24. -005 September 2003 Added Documentation Changes 1-15. -006 Added Documentation Changes 16-34. November 2003 Updated Documentation changes 14, 16, 17, and 28. -007 January 2004 Added Documentation Changes 35-45. Removed Documentation Changes 1-45. -008 March 2004 Added Documentation Changes 1-5. -009 Added Documentation Changes 7-27. May 2004 Removed Documentation Changes 1-27. -010 August 2004 Added Documentation Changes 1. -011 Added Documentation Changes 2-28. November 2004 Removed Documentation Changes 1-28. -012 March 2005 Added Documentation Changes 1-16. Updated title. -013 There are no Documentation Changes for this revision of the July 2005 document. -014 Added Documentation Changes 1-21. September 2005 Removed Documentation Changes 1-21. -015 March 9, 2006 Added Documentation Changes 1-20. -016 Added Documentation changes 21-23. March 27, 2006 Removed Documentation Changes 1-23. -017 September 2006 Added Documentation Changes 1-36. -018 Added Documentation Changes 37-42. October 2006 Removed Documentation Changes 1-42. -019 March 2007 Added Documentation Changes 1-19. -020 Added Documentation Changes 20-27. May 2007 Removed Documentation Changes 1-27. -021 November 2007 Added Documentation Changes 1-6 -022-023 Removed Documentation Changes 1-6 Added Documentation Changes 1-6 Removed Documentation Changes 1-6 Added Documentation Changes 1-21 August 2008 March 2009 4 Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes
Revision History Revision Description Date -024-025 -026-027 -028-029 -030-031 -032-033 -034-035 -036-037 -038-039 -040-041 -042-043 -044-045 -046 Removed Documentation Changes 1-21 Added Documentation Changes 1-16 Removed Documentation Changes 1-16 Added Documentation Changes 1-18 Removed Documentation Changes 1-18 Added Documentation Changes 1-15 Removed Documentation Changes 1-15 Added Documentation Changes 1-24 Removed Documentation Changes 1-24 Added Documentation Changes 1-29 Removed Documentation Changes 1-29 Added Documentation Changes 1-29 Removed Documentation Changes 1-29 Added Documentation Changes 1-29 Removed Documentation Changes 1-29 Added Documentation Changes 1-29 Removed Documentation Changes 1-29 Added Documentation Changes 1-14 Removed Documentation Changes 1-14 Added Documentation Changes 1-38 Removed Documentation Changes 1-38 Added Documentation Changes 1-16 Removed Documentation Changes 1-16 Added Documentation Changes 1-18 Removed Documentation Changes 1-18 Added Documentation Changes 1-17 Removed Documentation Changes 1-17 Added Documentation Changes 1-28 Removed Documentation Changes 1-28 Add Documentation Changes 1-22 Removed Documentation Changes 1-22 Add Documentation Changes 1-17 Removed Documentation Changes 1-17 Add Documentation Changes 1-24 Removed Documentation Changes 1-24 Add Documentation Changes 1-20 Removed Documentation Changes 1-20 Add Documentation Changes 1-8 Removed Documentation Changes 1-8 Add Documentation Changes 1-43 Removed Documentation Changes 1-43 Add Documentation Changes 1-12 Removed Documentation Changes 1-12 Add Documentation Changes 1-22 Removed Documentation Changes 1-22 Add Documentation Changes 1-25 June 2009 September 2009 December 2009 March 2010 June 2010 September 2010 January 2011 April 2011 May 2011 October 2011 December 2011 March 2012 May 2012 August 2012 January 2013 June 2013 September 2013 February 2014 February 2014 June 2014 September 2014 January 2015 April 2015 Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 5
Revision History Revision Description Date -047-048 -049 Removed Documentation Changes 1-25 Add Documentation Changes 1-19 Removed Documentation Changes 1-19 Add Documentation Changes 1-33 Removed Documentation Changes 1-33 Add Documentation Changes 1-33 June 2015 September 2015 December 2015 6 Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes
Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Affected Documents Document Title Document Number/ Location Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 1: Basic Architecture 253665 Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 2A: Instruction Set Reference, A-M Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 2B: Instruction Set Reference, N-Z Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 2C: Instruction Set Reference Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3A: System Programming Guide, Part 1 Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3B: System Programming Guide, Part 2 Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3C: System Programming Guide, Part 3 Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3D: System Programming Guide, Part 4 253666 253667 326018 253668 253669 326019 332831 Nomenclature Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification. Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 7
Summary Tables of Changes The following table indicates documentation changes which apply to the Intel 64 and IA-32 architectures. This table uses the following notations: Codes Used in Summary Tables Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. Documentation Changes(Sheet 1 of 2) No. DOCUMENTATION CHANGES 1 Updates to Chapter 1, Volume 1 2 Updates to Chapter 6, Volume 1 3 Updates to Chapter 8, Volume 1 4 Updates to Chapter 13, Volume 1 5 Updates to Chapter 15, Volume 1 6 Updates to Chapter 1, Volume 2A 7 Updates to Chapter 2, Volume 2A 8 Updates to Chapter 3, Volume 2A 9 Updates to Chapter 4, Volume 2B 10 Updates to Chapter 1, Volume 3A 11 Updates to Chapter 2, Volume 3A 12 Updates to Chapter 4, Volume 3A 13 Updates to Chapter 5, Volume 3A 14 Updates to Chapter 6, Volume 3A 15 Updates to Chapter 10, Volume 3A 16 Updates to Chapter 14, Volume 3B 17 Updates to Chapter 15, Volume 3B 18 Updates to Chapter 16, Volume 3B 19 Updates to Chapter 17, Volume 3B 20 Updates to Chapter 18, Volume 3B 21 Updates to Chapter 19, Volume 3B 22 Updates to Chapter 22, Volume 3C 23 Updates to Chapter 24, Volume 3C 24 Updates to Chapter 25, Volume 3C 25 Updates to Chapter 26, Volume 3C 26 Updates to Chapter 27, Volume 3C 27 Updates to Chapter 28, Volume 3C Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 8
Documentation Changes(Sheet 2 of 2) No. DOCUMENTATION CHANGES 28 Updates to Chapter 34, Volume 3C 29 Updates to Chapter 35, Volume 3C 30 Updates to Chapter 36, Volume 3C 31 Updates to Chapter 38, Volume 3D 32 Updates to Appendix B, Volume 3D 33 Updates to Appendix C, Volume 3D Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 9
Documentation Changes 1. Updates to Chapter 1, Volume 1 Change bars show changes to Chapter 1 of the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 1: Basic Architecture. ------------------------------------------------------------------------------------------... 1.1 INTEL 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which include: Pentium processors P6 family processors Pentium 4 processors Pentium M processors Intel Xeon processors Pentium D processors Pentium processor Extreme Editions 64-bit Intel Xeon processors Intel Core Duo processor Intel Core Solo processor Dual-Core Intel Xeon processor LV Intel Core 2 Duo processor Intel Core 2 Quad processor Q6000 series Intel Xeon processor 3000, 3200 series Intel Xeon processor 5000 series Intel Xeon processor 5100, 5300 series Intel Core 2 Extreme processor X7000 and X6800 series Intel Core 2 Extreme processor QX6000 series Intel Xeon processor 7100 series Intel Pentium Dual-Core processor Intel Xeon processor 7200, 7300 series Intel Core 2 Extreme processor QX9000 and X9000 series Intel Core 2 Quad processor Q9000 series Intel Core 2 Duo processor E8000, T9000 series Intel Atom processor family Intel Atom processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000, C1000 series are built from 45 nm and 32 nm processes Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 10
Intel Core i7 processor Intel Core i5 processor Intel Xeon processor E7-8800/4800/2800 product families Intel Core i7-3930k processor 2nd generation Intel Core i7-2xxx, Intel Core i5-2xxx, Intel Core i3-2xxx processor series Intel Xeon processor E3-1200 product family Intel Xeon processor E5-2400/1400 product family Intel Xeon processor E5-4600/2600/1600 product family 3rd generation Intel Core processors Intel Xeon processor E3-1200 v2 product family Intel Xeon processor E5-2400/1400 v2 product families Intel Xeon processor E5-4600/2600/1600 v2 product families Intel Xeon processor E7-8800/4800/2800 v2 product families 4th generation Intel Core processors The Intel Core M processor family Intel Core i7-59xx Processor Extreme Edition Intel Core i7-49xx Processor Extreme Edition Intel Xeon processor E3-1200 v3 product family Intel Xeon processor E5-2600/1600 v3 product families Intel Xeon processor 5200, 5400, 7400 series 5th generation Intel Core processors Intel Atom processor X7-Z8000 and X5-Z8000 series Intel Atom processor Z3400 series Intel Atom processor Z3500 series 6th generation Intel Core processors Intel Xeon processor E3-1500m v5 product family P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium Pro, Pentium II, Pentium III, and Pentium III Xeon processors. The Pentium 4, Pentium D, and Pentium processor Extreme Editions are based on the Intel NetBurst microarchitecture. Most early Intel Xeon processors are based on the Intel NetBurst microarchitecture. Intel Xeon processor 5000, 7100 series are based on the Intel NetBurst microarchitecture. The Intel Core Duo, Intel Core Solo and dual-core Intel Xeon processor LV are based on an improved Pentium M processor microarchitecture. The Intel Xeon processor 3000, 3200, 5100, 5300, 7200 and 7300 series, Intel Pentium dual-core, Intel Core 2 Duo, Intel Core 2 Quad, and Intel Core 2 Extreme processors are based on Intel Core microarchitecture. The Intel Xeon processor 5200, 5400, 7400 series, Intel Core 2 Quad processor Q9000 series, and Intel Core 2 Extreme processor QX9000, X9000 series, Intel Core 2 processor E8000 series are based on Enhanced Intel Core microarchitecture. The Intel Atom processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000, C1000 series are based on the Intel Atom microarchitecture and supports Intel 64 architecture. Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 11
The Intel Core i7 processor and Intel Xeon processor 3400, 5500, 7500 series are based on 45 nm Intel microarchitecture code name Nehalem. Intel microarchitecture code name Westmere is a 32 nm version of Intel microarchitecture code name Nehalem. Intel Xeon processor 5600 series, Intel Xeon processor E7 and various Intel Core i7, i5, i3 processors are based on Intel microarchitecture code name Westmere. These processors support Intel 64 architecture. The Intel Xeon processor E5 family, Intel Xeon processor E3-1200 family, Intel Xeon processor E7-8800/ 4800/2800 product families, Intel Core TM i7-3930k processor, and 2nd generation Intel Core i7-2xxx, Intel Core i5-2xxx, Intel Core i3-2xxx processor series are based on the Intel microarchitecture code name Sandy Bridge and support Intel 64 architecture. The Intel Xeon processor E7-8800/4800/2800 v2 product families, Intel Xeon processor E3-1200 v2 product family and the 3rd generation Intel Core processors are based on the Intel microarchitecture code name Ivy Bridge and support Intel 64 architecture. The Intel Xeon processor E5-4600/2600/1600 v2 product families, Intel Xeon processor E5-2400/1400 v2 product families and Intel Core i7-49xx Processor Extreme Edition are based on the Intel microarchitecture code name Ivy Bridge-E and support Intel 64 architecture. The Intel Xeon processor E3-1200 v3 product family and 4th Generation Intel Core processors are based on the Intel microarchitecture code name Haswell and support Intel 64 architecture. The Intel Core M processor family and 5th generation Intel Core processors are based on the Intel microarchitecture code name Broadwell and support Intel 64 architecture. The Intel Xeon processor E3-1500m v5 product family and 6th generation Intel Core processors are based on the Intel microarchitecture code name Skylake and support Intel 64 architecture. The Intel Xeon processor E5-2600/1600 v3 product families and the Intel Core i7-59xx Processor Extreme Edition are based on the Intel microarchitecture code name Haswell-E and support Intel 64 architecture. The Intel Atom processor Z8000 series is based on the Intel microarchitecture code name Airmont. The Intel Atom processor Z3400 series and the Intel Atom processor Z3500 series are based on the Intel microarchitecture code name Silvermont. P6 family, Pentium M, Intel Core Solo, Intel Core Duo processors, dual-core Intel Xeon processor LV, and early generations of Pentium 4 and Intel Xeon processors support IA-32 architecture. The Intel Atom processor Z5xx series support IA-32 architecture. The Intel Xeon processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100, 7200, 7300, 7400 series, Intel Core 2 Duo, Intel Core 2 Extreme processors, Intel Core 2 Quad processors, Pentium D processors, Pentium Dual-Core processor, newer generations of Pentium 4 and Intel Xeon processor family support Intel 64 architecture. IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microprocessors. Intel 64 architecture is the instruction set architecture and programming environment which is the superset of Intel s 32-bit and 64-bit architectures. It is compatible with the IA-32 architecture.... 2. Updates to Chapter 6, Volume 1 Change bars show changes to Chapter 6 of the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 1: Basic Architecture. ------------------------------------------------------------------------------------------... Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 12
6.4.1 Call and Return Operation for Interrupt or Exception Handling Procedures A call to an interrupt or exception handler procedure is similar to a procedure call to another protection level (see Section 6.3.6, CALL and RET Operation Between Privilege Levels ). Here, the vector references one of two kinds of gates in the IDT: an interrupt gate or a trap gate. Interrupt and trap gates are similar to call gates in that they provide the following information: Access rights information The segment selector for the code segment that contains the handler procedure An offset into the code segment to the first instruction of the handler procedure The difference between an interrupt gate and a trap gate is as follows. If an interrupt or exception handler is called through an interrupt gate, the processor clears the interrupt enable (IF) flag in the EFLAGS register to prevent subsequent interrupts from interfering with the execution of the handler. When a handler is called through a trap gate, the state of the IF flag is not changed. Table 6-1 Exceptions and Interrupts Vector Mnemonic Description Source 0 #DE Divide Error DIV and IDIV instructions. 1 #DB Debug Any code or data reference. 2 NMI Interrupt Non-maskable external interrupt. 3 #BP Breakpoint INT 3 instruction. 4 #OF Overflow INTO instruction. 5 #BR BOUND Range Exceeded BOUND instruction. 6 #UD Invalid Opcode (UnDefined Opcode) UD2 instruction or reserved opcode. 1 7 #NM Device Not Available (No Math Coprocessor) Floating-point or WAIT/FWAIT instruction. 8 #DF Double Fault Any instruction that can generate an exception, an NMI, or an INTR. 9 #MF CoProcessor Segment Overrun (reserved) Floating-point instruction. 2 10 #TS Invalid TSS Task switch or TSS access. 11 #NP Segment Not Present Loading segment registers or accessing system segments. 12 #SS Stack Segment Fault Stack operations and SS register loads. 13 #GP General Protection Any memory reference and other protection checks. 14 #PF Page Fault Any memory reference. 15 Reserved 16 #MF Floating-Point Error (Math Fault) Floating-point or WAIT/FWAIT instruction. 17 #AC Alignment Check Any data reference in memory. 3 18 #MC Machine Check Error codes (if any) and source are model dependent. 4 19 #XM SIMD Floating-Point Exception SIMD Floating-Point Instruction 5 20 #VE Virtualization Exception EPT violations 6 21-31 Reserved 32-255 Maskable Interrupts External interrupt from INTR pin or INT n instruction. Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 13
Table 6-1 Exceptions and Interrupts (Contd.) Vector Mnemonic Description Source NOTES: 1. The UD2 instruction was introduced in the Pentium Pro processor. 2. IA-32 processors after the Intel386 processor do not generate this exception. 3. This exception was introduced in the Intel486 processor. 4. This exception was introduced in the Pentium processor and enhanced in the P6 family processors. 5. This exception was introduced in the Pentium III processor. 6. This exception can occur only on processors that support the 1-setting of the EPT-violation #VE VM-execution control.... 3. Updates to Chapter 8, Volume 1 Change bars show changes to Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 1: Basic Architecture. ------------------------------------------------------------------------------------------... 8.1.2 x87 FPU Data Registers The x87 FPU data registers (shown in Figure 8-1) consist of eight 80-bit registers. Values are stored in these registers in the double extended-precision floating-point format shown in Figure 4-3. When floating-point, integer, or packed BCD integer values are loaded from memory into any of the x87 FPU data registers, the values are automatically converted into double extended-precision floating-point format (if they are not already in that format). When computation results are subsequently transferred back into memory from any of the x87 FPU registers, the results can be left in the double extended-precision floating-point format or converted back into a shorter floating-point format, an integer format, or the packed BCD integer format. (See Section 8.2, x87 FPU Data Types, for a description of the data types operated on by the x87 FPU.) Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 14
Sign 79 78 64 63 R7 Exponent R6 R5 R4 R3 R2 R1 R0 15 Control Register 0 Data Registers Significand 47 Last Instruction Pointer (FCS:FIP) 0 0 Status Register Tag Register Figure 8-1 Last Data (Operand) Pointer (FDS:FDP) 10 0 Opcode x87 FPU Execution Environment... 8.1.8 x87 FPU Instruction and Data (Operand) Pointers The x87 FPU stores pointers to the instruction and data (operand) for the last non-control instruction executed. These are the x87 FPU instruction pointer and x87 FPU data (operand) pointers; software can save these pointers to provide state information for exception handlers. The pointers are illustrated in Figure 8-1 (the figure illustrates the pointers as used outside 64-bit mode; see below). Note that the value in the x87 FPU data pointer is always a pointer to a memory operand. If the last non-control instruction that was executed did not have a memory operand, the value in the data pointer is undefined (reserved). If CPUID.(EAX=07H,ECX=0H):EBX[bit 6] = 1, the data pointer is updated only for x87 non-control instructions that incur unmasked x87 exceptions. The contents of the x87 FPU instruction and data pointers remain unchanged when any of the following instructions are executed: FCLEX/FNCLEX, FLDCW, FSTCW/FNSTCW, FSTSW/FNSTSW, FSTENV/FNSTENV, FLDENV, and WAIT/FWAIT. For all the x87 FPUs and NPXs except the 8087, the x87 FPU instruction pointer points to any prefixes that preceded the instruction. For the 8087, the x87 FPU instruction pointer points only to the actual opcode. The x87 FPU instruction and data pointers each consists of an offset and a segment selector: The x87 FPU Instruction Pointer Offset (FIP) comprises 64 bits on processors that support IA-32e mode; on other processors, it offset comprises 32 bits. The x87 FPU Instruction Pointer Selector (FCS) comprises 16 bits. The x87 FPU Data Pointer Offset (FDP) comprises 64 bits on processors that support IA-32e mode; on other processors, it offset comprises 32 bits. The x87 FPU Data Pointer Selector (FDS) comprises 16 bits. Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 15
The pointers are accessed by the FINIT/FNINIT, FLDENV, FRSTOR, FSAVE/FNSAVE, FSTENV/FNSTENV, FXRSTOR, FXSAVE, XRSTOR, XSAVE, and XSAVEOPT instructions as follows: FINIT/FNINIT. Each instruction clears FIP, FCS, FDP, and FDS. FLDENV, FRSTOR. These instructions use the memory formats given in Figures Figure 8-9 through Figure 8-12: For each of FIP and FDP, each instruction loads the lower 32 bits from memory and clears the upper 32 bits. If CR0.PE = 1, each instruction loads FCS and FDS from memory; otherwise, it clears them. FSAVE/FNSAVE, FSTENV/FNSTENV. These instructions use the memory formats given in Figures Figure 8-9 through Figure 8-12. Each instruction saves the lower 32 bits of each FIP and FDP into memory. the upper 32 bits are not saved. If CR0.PE = 1, each instruction saves FCS and FDS into memory. If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 1, the processor deprecates FCS and FDS; it saves each as 0000H. After saving these data into memory, FSAVE/FNSAVE clears FIP, FCS, FDP, and FDS. FXRSTOR, XRSTOR. These instructions load data from a memory image whose format depend on operating mode and the REX prefix. The memory formats are given in Tables 3-52, 3-55, and 3-56 in Chapter 3, Instruction Set Reference, A-M, of the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 2A. Outside of 64-bit mode or if REX.W = 0, the instructions operate as follows: For each of FIP and FDP, each instruction loads the lower 32 bits from memory and clears the upper 32 bits. Each instruction loads FCS and FDS from memory. In 64-bit mode with REX.W = 1, the instructions operate as follows: Each instruction loads FIP and FDP from memory. Each instruction clears FCS and FDS. FXSAVE, XSAVE, and XSAVEOPT. These instructions store data into a memory image whose format depend on operating mode and the REX prefix. The memory formats are given in Tables 3-52, 3-55, and 3-56 in Chapter 3, Instruction Set Reference, A-M, of the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 2A. Outside of 64-bit mode or if REX.W = 0, the instructions operate as follows: Each instruction saves the lower 32 bits of each of FIP and FDP into memory. The upper 32 bits are not saved. Each instruction saves FCS and FDS into memory. If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 1, the processor deprecates FCS and FDS; it saves each as 0000H. In 64-bit mode with REX.W = 1, each instruction saves FIP and FDP into memory. FCS and FDS are not saved.... 8.3 X87 FPU INSTRUCTION SET The floating-point instructions that the x87 FPU supports can be grouped into six functional categories: Data transfer instructions Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 16
Basic arithmetic instructions Comparison instructions Transcendental instructions Load constant instructions x87 FPU control instructions See Section, CPUID.EAX=80000001H:ECX.PREFTEHCHW[bit 8]: if 1 indicates the processor supports the PREFTEHCHW instruction. CPUID.(EAX=07H, ECX=0H):ECX.PREFTEHCHWT1[bit 0]: if 1 indicates the processor supports the PREFTEHCHWT1 instruction., for a list of the floating-point instructions by category. The following section briefly describes the instructions in each category. Detailed descriptions of the floating-point instructions are given in the Intel 64 and IA-32 Architectures Software Developer s Manual, Volumes 2A, 2B &2C.... 8.1.10 Saving the x87 FPU s State with FSTENV/FNSTENV and FSAVE/FNSAVE The FSTENV/FNSTENV and FSAVE/FNSAVE instructions store x87 FPU state information in memory for use by exception handlers and other system and application software. The FSTENV/FNSTENV instruction saves the contents of the status, control, tag, x87 FPU instruction pointer, x87 FPU data pointer, and opcode registers. The FSAVE/FNSAVE instruction stores that information plus the contents of the x87 FPU data registers. Note that the FSAVE/FNSAVE instruction also initializes the x87 FPU to default values (just as the FINIT/FNINIT instruction does) after it has saved the original state of the x87 FPU. The manner in which this information is stored in memory depends on the operating mode of the processor (protected mode or real-address mode) and on the operand-size attribute in effect (32-bit or 16-bit). See Figures Figure 8-9 through Figure 8-12. In virtual-8086 mode or SMM, the real-address mode formats shown in Figure 8-12 is used. See Chapter 34, System Management Mode, of the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3C, for information on using the x87 FPU while in SMM. The FLDENV and FRSTOR instructions allow x87 FPU state information to be loaded from memory into the x87 FPU. Here, the FLDENV instruction loads only the status, control, tag, x87 FPU instruction pointer, x87 FPU data pointer, and opcode registers, and the FRSTOR instruction loads all the x87 FPU registers, including the x87 FPU stack registers. 31 0 0 0 0 0 32-Bit Protected Mode Format 16 15 Bits 10:0 of opcode Control Word Status Word Tag Word FPU Instruction Pointer Offset (FIP) FPU Instruction Pointer Selector FPU Data Pointer Offset (FDP) FPU Data Pointer Selector (FDS) For instructions that also store x87 FPU data registers, the eight 80-bit registers (R0-R7) follow the above structure in sequence. 0 0 4 8 12 16 20 24 Figure 8-9 Protected Mode x87 FPU State Image in Memory, 32-Bit Format Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 17
31 0 0 0 0 0 0 0 0 32-Bit Real-Address Mode Format 16 15 0 Control Word 0 Status Word 4 Tag Word 8 FIP[15:0] 12 FIP[31:16] FOP[10:0] 16 FDP[15:0] 20 FDP[31:16] 0 0 0 0 0 0 0 0 0 0 0 0 24 For instructions that also store x87 FPU data registers, the eight 80-bit registers (R0-R7) follow the above structure in sequence. Figure 8-10 Real Mode x87 FPU State Image in Memory, 32-Bit Format 16-Bit Protected Mode Format 15 0 Control Word 0 Status Word 2 Tag Word 4 FIP 6 FCS 8 FDP 10 FDS 12 Figure 8-11 Protected Mode x87 FPU State Image in Memory, 16-Bit Format 16-Bit Real-Address Mode and Virtual-8086 Mode Format 15 0 Control Word 0 Status Word 2 Tag Word 4 FIP[15:0] 6 FIP[19:16] 0 Bits 10:0 of opcode 8 FDP[15:0] 10 FDP[19:16] 0 0 0 0 0 0 0 0 0 0 0 0 12 Figure 8-12 Real Mode x87 FPU State Image in Memory, 16-Bit Format... Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 18
4. Updates to Chapter 13, Volume 1 Change bars show changes to Chapter 13 of the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 1: Basic Architecture. ------------------------------------------------------------------------------------------... 13.4.1 Legacy Region of an XSAVE Area The legacy region of an XSAVE area comprises the 512 bytes starting at the area s base address. It has the same format as the FXSAVE area (see Section 10.5.1). The XSAVE feature set uses the legacy area for x87 state (state component 0) and SSE state (state component 1). Table 13-1 illustrates the format of the first 416 bytes of the legacy region of an XSAVE area. Table 13-1 Format of the Legacy Region of an XSAVE Area 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIP[63:48] or reserved FCS or FIP[47:32] MXCSR_MASK FIP[31:0] FOP Rsvd. FTW FSW FCW 0 MXCSR FDP[63:48] or reserved FDS or FDP[47:32] FDP[31:0 16 Reserved ST0/MM0 32 Reserved ST1/MM1 48 Reserved ST2/MM2 64 Reserved ST3/MM3 80 Reserved ST4/MM4 96 Reserved ST5/MM5 112 Reserved ST6/MM6 128 Reserved ST7/MM7 144 XMM0 160 XMM1 176 XMM2 192 XMM3 208 XMM4 224 XMM5 240 XMM6 256 XMM7 272 XMM8 288 XMM9 304 XMM10 320 XMM11 336 Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 19
The x87 state component comprises bytes 23:0 and bytes 159:32. The SSE state component comprises bytes 31:24 and bytes 415:160. The XSAVE feature set does not use bytes 511:416; bytes 463:416 are reserved. Section 13.7 through Section 13.9 provide details of how instructions in the XSAVE feature set use the legacy region of an XSAVE area.... Table 13-1 Format of the Legacy Region of an XSAVE Area (Contd.) (Contd.) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XMM12 352 XMM13 368 XMM14 384 XMM15 400 13.5.1 x87 State Instructions in the XSAVE feature set can manage the same state of the x87 FPU execution environment (x87 state) that can be managed using the FXSAVE and FXRSTOR instructions. They organize all x87 state as a user state component in the legacy region of the XSAVE area (see Section 13.4.1). This region is illustrated in Table 13-1; the x87 state is listed below, along with details of its interactions with the XSAVE feature set: Bytes 1:0, 3:2, 7:6. These are used for the x87 FPU Control Word (FCW), the x87 FPU Status Word (FSW), and the x87 FPU Opcode (FOP), respectively. Byte 4 is used for an abridged version of the x87 FPU Tag Word (FTW). The following items describe its usage: For each j, 0 j 7, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save a 0 into bit j of byte 4 if x87 FPU data register STj has a empty tag; otherwise, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save a 1 into bit j of byte 4. For each j, 0 j 7, XRSTOR and XRSTORS establish the tag value for x87 FPU data register STj as follows. If bit j of byte 4 is 0, the tag for STj in the tag register for that data register is marked empty (11B); otherwise, the x87 FPU sets the tag for STj based on the value being loaded into that register (see below). Bytes 15:8 are used as follows: If the instruction has no REX prefix, or if REX.W = 0: Bytes 11:8 are used for bits 31:0 of the x87 FPU Instruction Pointer Offset (FIP). If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 0, bytes 13:12 are used for x87 FPU Instruction Pointer Selector (FCS). Otherwise, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save these bytes as 0000H, and XRSTOR and XRSTORS ignore them. Bytes 15:14 are not used. If the instruction has a REX prefix with REX.W = 1, bytes 15:8 are used for the full 64 bits of FIP. Bytes 23:16 are used as follows: If the instruction has no REX prefix, or if REX.W = 0: Bytes 19:16 are used for bits 31:0 of the x87 FPU Data Pointer Offset (FDP). If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 0, bytes 21:20 are used for x87 FPU Data Pointer Selector (FDS). Otherwise, XSAVE, XSAVEOPT, XSAVEC, and XSAVES save these bytes as 0000H; and XRSTOR and XRSTORS ignore them. Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 20
Bytes 23:22 are not used. If the instruction has a REX prefix with REX.W = 1, bytes 23:16 are used for the full 64 bits of FDP. Bytes 31:24 are used for SSE state (see Section 13.5.2). Bytes 159:32 are used for the registers ST0 ST7 (MM0 MM7). Each of the 8 register is allocated a 128-bit region, with the low 80 bits used for the register and the upper 48 bits unused. x87 state is XSAVE-managed but the x87 FPU feature is not XSAVE-enabled. The XSAVE feature set can operate on x87 state only if the feature set is enabled (CR4.OSXSAVE = 1). 1 Software can otherwise use x87 state even if the XSAVE feature set is not enabled.... 13.5.6 PT State The register state used by Intel Processor Trace (PT state) comprises the following 9 MSRs: IA32_RTIT_CTL, IA32_RTIT_OUTPUT_BASE, IA32_RTIT_OUTPUT_MASK_PTRS, IA32_RTIT_STATUS, IA32_RTIT_CR3_MATCH, IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B, IA32_RTIT_ADDR1_A, and IA32_RTIT_ADDR1_B. 2 As noted in Section 13.1, the XSAVE feature set manages PT state as supervisor state component 8. Thus, PT state is located in the extended region of the XSAVE area (see Section 13.4.3). As noted in Section 13.2, CPUID.(EAX=0DH,ECX=8):EAX enumerates the size (in bytes) required for PT state. Each of the MSRs is allocated 8 bytes in the state component, with IA32_RTIT_CTL at byte offset 0, IA32_RTIT_OUTPUT_BASE at byte offset 8, etc. Any locations in the state component at or beyond byte offset 72 are reserved. PT state is XSAVE-managed but Intel Processor Trace is not XSAVE-enabled. The XSAVE feature set can operate on PT state only if the feature set is enabled (CR4.OSXSAVE = 1) and has been configured to manage PT state (IA32_XSS[8] = 1). Software can otherwise use Intel Processor Trace and access its MSRs (using RDMSR and WRMSR) even if the XSAVE feature set is not enabled or has not been configured to manage PT state. The following items describe special treatment of PT state by the XSAVES and XRSTORS instructions: If XSAVES saves PT state, the instruction clears IA32_RTIT_CTL.TraceEn (bit 0) after saving the value of the IA32_RTIT_CTL MSR and before saving any other PT state. If XSAVES causes a fault or a VM exit, it restores IA32_RTIT_CTL.TraceEn to its original value. If XSAVES saves PT state, the instruction saves zeroes in the reserved portions of the state component. If XRSTORS would restore (or initialize) PT state and IA32_RTIT_CTL.TraceEn = 1, the instruction causes a general-protection exception (#GP) before modifying PT state. If XRSTORS causes an exception or a VM exit, it does so before any modification to IA32_RTIT_CTL.TraceEn (even if it has loaded other PT state).... 13.6 PROCESSOR TRACKING OF XSAVE-MANAGED STATE The XSAVEOPT, XSAVEC, and XSAVES instructions use two optimization to reduce the amount of data that they write to memory. They avoid writing data for any state component known to be in its initial configuration (the init optimization). In addition, if either XSAVEOPT or XSAVES is using the same XSAVE area as that used by the most recent execution of XRSTOR or XRSTORS, it may avoid writing data for any state component whose config- 1. The processor ensures that XCR0[0] is always 1. 2. These MSRs might not be supported by every processor that supports Intel Processor Trace. Software can use the CPUID instruction to discover which are supported; see Section 36.3.1, Detection of Intel Processor Trace and Capability Enumeration, of Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3C. Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 21
uration is known not to have been modified since then (the modified optimization). (XSAVE does not use these optimizations, and XSAVEC does not use the modified optimization.) The operation of XSAVEOPT, XSAVEC, and XSAVES are described in more detail in Section 13.9 through Section 13.11. A processor can support the init and modified optimizations with special hardware that tracks the state components that might benefit from those optimizations. Other implementations might not include such hardware; such a processor would always consider each such state component as not in its initial configuration and as modified since the last execution of XRSTOR or XRSTORS. The following notation describes the state of the init and modified optimizations: XINUSE denotes the state-component bitmap corresponding to the init optimization. If XINUSE[i] = 0, state component i is known to be in its initial configuration; otherwise XINUSE[i] = 1. It is possible for XINUSE[i] to be 1 even when state component i is in its initial configuration. On a processor that does not support the init optimization, XINUSE[i] is always 1 for every value of i. Executing XGETBV with ECX = 1 returns in EDX:EAX the logical-and of XCR0 and the current value of the XINUSE state-component bitmap. Such an execution of XGETBV always sets EAX[1] to 1 if XCR0[1] = 1 and MXCSR does not have its RESET value of 1F80H. Section 13.2 explains how software can determine whether a processor supports this use of XGETBV. XMODIFIED denotes the state-component bitmap corresponding to the modified optimization. If XMODIFIED[i] = 0, state component i is known not to have been modified since the most recent execution of XRSTOR or XRSTORS; otherwise XMODIFIED[i] = 1. It is possible for XMODIFIED[i] to be 1 even when state component i has not been modified since the most recent execution of XRSTOR or XRSTORS. On a processor that does not support the modified optimization, XMODIFIED[i] is always 1 for every value of i. A processor that implements the modified optimization saves information about the most recent execution of XRSTOR or XRSTORS in a quantity called XRSTOR_INFO, a 4-tuple containing the following: (1) the CPL; (2) whether the logical processor was in VMX non-root operation; (3) the linear address of the XSAVE area; and (4) the XCOMP_BV field in the XSAVE area. An execution of XSAVEOPT or XSAVES uses the modified optimization only if that execution corresponds to XRSTOR_INFO on these four parameters. This mechanism implies that, depending on details of the operating system, the processor might determine that an execution of XSAVEOPT by one user application corresponds to an earlier execution of XRSTOR by a different application. For this reason, Intel recommends the application software not use the XSAVEOPT instruction. The following items specify the initial configuration each state component (for the purposes of defining the XINUSE bitmap): x87 state. x87 state is in its initial configuration if the following all hold: FCW is 037FH; FSW is 0000H; FTW is FFFFH; FCS and FDS are each 0000H; FIP and FDP are each 00000000_00000000H; each of ST0 ST7 is 0000_00000000_00000000H. SSE state. In 64-bit mode, SSE state is in its initial configuration if each of XMM0 XMM15 is 0. Outside 64-bit mode, SSE state is in its initial configuration if each of XMM0 XMM7 is 0. XINUSE[1] pertains only to the state of the XMM registers and not to MXCSR. An execution of XRSTOR or XRSTORS outside 64-bit mode does not update XMM8 XMM15. (See Section 13.13.) AVX state. In 64-bit mode, AVX state is in its initial configuration if each of YMM0_H YMM15_H is 0. Outside 64-bit mode, AVX state is in its initial configuration if each of YMM0_H YMM7_H is 0. An execution of XRSTOR or XRSTORS outside 64-bit mode does not update YMM8_H YMM15_H. (See Section 13.13.) BNDREG state. BNDREG state is in its initial configuration if the value of each of BND0 BND3 is 0. BNDCSR state. BNDCSR state is in its initial configuration if BNDCFGU and BNDCSR each has value 0. Opmask state. Opmask state is in its initial configuration if each of the opmask registers k0 k7 is 0. ZMM_Hi256 state. In 64-bit mode, ZMM_Hi256 state is in its initial configuration if each of ZMM0_H ZMM15_H is 0. Outside 64-bit mode, ZMM_Hi256 state is in its initial configuration if each of ZMM0_H ZMM7_H is 0. An execution of XRSTOR or XRSTORS outside 64-bit mode does not update ZMM8_H ZMM15_H. (See Section 13.13.) Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 22
Hi16_ZMM state. In 64-bit mode, Hi16_ZMM state is in its initial configuration if each of ZMM16 ZMM31 is 0. Outside 64-bit mode, Hi16_ZMM state is always in its initial configuration. An execution of XRSTOR or XRSTORS outside 64-bit mode does not update ZMM31 ZMM31. (See Section 13.13.) PT state. PT state is in its initial configuration if each of the 9 MSRs is 0. PKRU state. PKRU state is in its initial configuration if the value of the PKRU is 0.... 5. Updates to Chapter 15, Volume 1 Change bars show changes to Chapter 15 of the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 1: Basic Architecture. ------------------------------------------------------------------------------------------... 15.3.7 RTM-Enabled Debugger Support Any debug exception (#DB) or breakpoint exception (#BP) inside an RTM region causes a transactional abort and, by default, redirects control flow to the fallback instruction address with architectural state recovered and bit 4 in EAX set. However, to allow software debuggers to intercept execution on debug or breakpoint exceptions, the RTM architecture provides additional capability called advanced debugging of RTM transactional regions. Advanced debugging of RTM transactional regions is enabled if bit 11 of DR7 and bit 15 of the IA32_DEBUGCTL MSR are both 1. In this case, any RTM transactional abort due to a #DB or #BP causes execution to roll back to just before the XBEGIN instruction (EAX is restored to the value it had before XBEGIN) and then delivers a #DB. (A #DB is delivered even if the transactional abort was caused by a #BP.) DR6[16] is cleared to indicate that the exception resulted from a debug or breakpoint exception inside an RTM region. See also Section 17.3.3, Debug Exceptions, Breakpoint Exceptions, and Restricted Transactional Memory (RTM), of Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3B.... 6. Updates to Chapter 1, Volume 2A Change bars show changes to Chapter 1 of the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 2A: Instruction Set Reference, A-M. ------------------------------------------------------------------------------------------... 1.1 INTEL 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which include: Pentium processors P6 family processors Pentium 4 processors Pentium M processors Intel Xeon processors Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 23
Pentium D processors Pentium processor Extreme Editions 64-bit Intel Xeon processors Intel Core Duo processor Intel Core Solo processor Dual-Core Intel Xeon processor LV Intel Core 2 Duo processor Intel Core 2 Quad processor Q6000 series Intel Xeon processor 3000, 3200 series Intel Xeon processor 5000 series Intel Xeon processor 5100, 5300 series Intel Core 2 Extreme processor X7000 and X6800 series Intel Core 2 Extreme processor QX6000 series Intel Xeon processor 7100 series Intel Pentium Dual-Core processor Intel Xeon processor 7200, 7300 series Intel Core 2 Extreme processor QX9000 and X9000 series Intel Core 2 Quad processor Q9000 series Intel Core 2 Duo processor E8000, T9000 series Intel Atom processor family Intel Atom processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000, C1000 series are built from 45 nm and 32 nm processes Intel Core i7 processor Intel Core i5 processor Intel Xeon processor E7-8800/4800/2800 product families Intel Core i7-3930k processor 2nd generation Intel Core i7-2xxx, Intel Core i5-2xxx, Intel Core i3-2xxx processor series Intel Xeon processor E3-1200 product family Intel Xeon processor E5-2400/1400 product family Intel Xeon processor E5-4600/2600/1600 product family 3rd generation Intel Core processors Intel Xeon processor E3-1200 v2 product family Intel Xeon processor E5-2400/1400 v2 product families Intel Xeon processor E5-4600/2600/1600 v2 product families Intel Xeon processor E7-8800/4800/2800 v2 product families 4th generation Intel Core processors The Intel Core M processor family Intel Core i7-59xx Processor Extreme Edition Intel Core i7-49xx Processor Extreme Edition Intel Xeon processor E3-1200 v3 product family Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 24
Intel Xeon processor E5-2600/1600 v3 product families Intel Xeon processor 5200, 5400, 7400 series 5th generation Intel Core processors Intel Atom processor X7-Z8000 and X5-Z8000 series Intel Atom processor Z3400 series Intel Atom processor Z3500 series 6th generation Intel Core processors Intel Xeon processor E3-1500m v5 product family P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium Pro, Pentium II, Pentium III, and Pentium III Xeon processors. The Pentium 4, Pentium D, and Pentium processor Extreme Editions are based on the Intel NetBurst microarchitecture. Most early Intel Xeon processors are based on the Intel NetBurst microarchitecture. Intel Xeon processor 5000, 7100 series are based on the Intel NetBurst microarchitecture. The Intel Core Duo, Intel Core Solo and dual-core Intel Xeon processor LV are based on an improved Pentium M processor microarchitecture. The Intel Xeon processor 3000, 3200, 5100, 5300, 7200 and 7300 series, Intel Pentium dual-core, Intel Core 2 Duo, Intel Core 2 Quad, and Intel Core 2 Extreme processors are based on Intel Core microarchitecture. The Intel Xeon processor 5200, 5400, 7400 series, Intel Core 2 Quad processor Q9000 series, and Intel Core 2 Extreme processor QX9000, X9000 series, Intel Core 2 processor E8000 series are based on Enhanced Intel Core microarchitecture. The Intel Atom processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000, C1000 series are based on the Intel Atom microarchitecture and supports Intel 64 architecture. The Intel Core i7 processor and Intel Xeon processor 3400, 5500, 7500 series are based on 45 nm Intel microarchitecture code name Nehalem. Intel microarchitecture code name Westmere is a 32 nm version of Intel microarchitecture code name Nehalem. Intel Xeon processor 5600 series, Intel Xeon processor E7 and various Intel Core i7, i5, i3 processors are based on Intel microarchitecture code name Westmere. These processors support Intel 64 architecture. The Intel Xeon processor E5 family, Intel Xeon processor E3-1200 family, Intel Xeon processor E7-8800/ 4800/2800 product families, Intel Core TM i7-3930k processor, and 2nd generation Intel Core i7-2xxx, Intel Core i5-2xxx, Intel Core i3-2xxx processor series are based on the Intel microarchitecture code name Sandy Bridge and support Intel 64 architecture. The Intel Xeon processor E7-8800/4800/2800 v2 product families, Intel Xeon processor E3-1200 v2 product family and the 3rd generation Intel Core processors are based on the Intel microarchitecture code name Ivy Bridge and support Intel 64 architecture. The Intel Xeon processor E5-4600/2600/1600 v2 product families, Intel Xeon processor E5-2400/1400 v2 product families and Intel Core i7-49xx Processor Extreme Edition are based on the Intel microarchitecture code name Ivy Bridge-E and support Intel 64 architecture. The Intel Xeon processor E3-1200 v3 product family and 4th Generation Intel Core processors are based on the Intel microarchitecture code name Haswell and support Intel 64 architecture. The Intel Core M processor family and 5th generation Intel Core processors are based on the Intel microarchitecture code name Broadwell and support Intel 64 architecture. The Intel Xeon processor E3-1500m v5 product family and 6th generation Intel Core processors are based on the Intel microarchitecture code name Skylake and support Intel 64 architecture. The Intel Xeon processor E5-2600/1600 v3 product families and the Intel Core i7-59xx Processor Extreme Edition are based on the Intel microarchitecture code name Haswell-E and support Intel 64 architecture. Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes 25