Intel 64 and IA-32 Architectures Software Developer s Manual

Transcription

1 Intel 64 and IA-32 Architectures Software Developer s Manual Volume 3A: System Programming Guide, Part 1 NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of eight volumes: Basic Architecture, Order Number ; Instruction Set Reference A-M, Order Number ; Instruction Set Reference N-Z, Order Number ; Instruction Set Reference, Order Number ; System Programming Guide, Part 1, Order Number ; System Programming Guide, Part 2, Order Number ; System Programming Guide, Part 3, Order Number ; System Programming Guide, Part 4, Order Number Refer to all eight volumes when evaluating your design needs. Order Number: US September 2015

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3 CONTENTS CHAPTER 1 ABOUT THIS MANUAL 1.1 INTEL 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE NOTATIONAL CONVENTIONS Bit and Byte Order Reserved Bits and Software Compatibility Instruction Operands Hexadecimal and Binary Numbers Segmented Addressing Syntax for CPUID, CR, and MSR Values Exceptions RELATED LITERATURE CHAPTER 2 SYSTEM ARCHITECTURE OVERVIEW 2.1 OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE Global and Local Descriptor Tables Global and Local Descriptor Tables in IA-32e Mode System Segments, Segment Descriptors, and Gates Gates in IA-32e Mode Task-State Segments and Task Gates Task-State Segments in IA-32e Mode Interrupt and Exception Handling Interrupt and Exception Handling IA-32e Mode Memory Management Memory Management in IA-32e Mode System Registers System Registers in IA-32e Mode Other System Resources MODES OF OPERATION Extended Feature Enable Register SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER System Flags and Fields in IA-32e Mode MEMORY-MANAGEMENT REGISTERS Global Descriptor Table Register (GDTR) Local Descriptor Table Register (LDTR) IDTR Interrupt Descriptor Table Register Task Register (TR) CONTROL REGISTERS CPUID Qualification of Control Register Flags EXTENDED CONTROL REGISTERS (INCLUDING XCR0) PROTECTION KEY RIGHTS REGISTER (PKRU) SYSTEM INSTRUCTION SUMMARY Loading and Storing System Registers Verifying of Access Privileges Loading and Storing Debug Registers Invalidating Caches and TLBs Controlling the Processor Reading Performance-Monitoring and Time-Stamp Counters Reading Counters in 64-Bit Mode Reading and Writing Model-Specific Registers Reading and Writing Model-Specific Registers in 64-Bit Mode Enabling Processor Extended States CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT 3.1 MEMORY MANAGEMENT OVERVIEW PAGE Vol. 3A iii

4 CONTENTS iv Vol. 3A PAGE 3.2 USING SEGMENTS Basic Flat Model Protected Flat Model Multi-Segment Model Segmentation in IA-32e Mode Paging and Segmentation PHYSICAL ADDRESS SPACE Intel 64 Processors and Physical Address Space LOGICAL AND LINEAR ADDRESSES Logical Address Translation in IA-32e Mode Segment Selectors Segment Registers Segment Loading Instructions in IA-32e Mode Segment Descriptors Code- and Data-Segment Descriptor Types SYSTEM DESCRIPTOR TYPES Segment Descriptor Tables Segment Descriptor Tables in IA-32e Mode CHAPTER 4 PAGING 4.1 PAGING MODES AND CONTROL BITS Three Paging Modes Paging-Mode Enabling Paging-Mode Modifiers Enumeration of Paging Features by CPUID HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW BIT PAGING PAE PAGING PDPTE Registers Linear-Address Translation with PAE Paging IA-32E PAGING ACCESS RIGHTS Determination of Access Rights Protection Keys PAGE-FAULT EXCEPTIONS ACCESSED AND DIRTY FLAGS PAGING AND MEMORY TYPING Paging and Memory Typing When the PAT is Not Supported (Pentium Pro and Pentium II Processors) Paging and Memory Typing When the PAT is Supported (Pentium III and More Recent Processor Families) Caching Paging-Related Information about Memory Typing CACHING TRANSLATION INFORMATION Process-Context Identifiers (PCIDs) Translation Lookaside Buffers (TLBs) Page Numbers, Page Frames, and Page Offsets Caching Translations in TLBs Details of TLB Use Global Pages Paging-Structure Caches Caches for Paging Structures Using the Paging-Structure Caches to Translate Linear Addresses Multiple Cached Entries for a Single Paging-Structure Entry Invalidation of TLBs and Paging-Structure Caches Operations that Invalidate TLBs and Paging-Structure Caches Recommended Invalidation Optional Invalidation Delayed Invalidation Propagation of Paging-Structure Changes to Multiple Processors INTERACTIONS WITH VIRTUAL-MACHINE EXTENSIONS (VMX) VMX Transitions VMX Support for Address Translation USING PAGING FOR VIRTUAL MEMORY MAPPING SEGMENTS TO PAGES

5 CONTENTS CHAPTER 5 PROTECTION 5.1 ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION FIELDS AND FLAGS USED FOR SEGMENT-LEVEL AND PAGE-LEVEL PROTECTION Code Segment Descriptor in 64-bit Mode LIMIT CHECKING Limit Checking in 64-bit Mode TYPE CHECKING Null Segment Selector Checking NULL Segment Checking in 64-bit Mode PRIVILEGE LEVELS PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS Accessing Data in Code Segments PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS Direct Calls or Jumps to Code Segments Accessing Nonconforming Code Segments Accessing Conforming Code Segments Gate Descriptors Call Gates IA-32e Mode Call Gates Accessing a Code Segment Through a Call Gate Stack Switching Stack Switching in 64-bit Mode Returning from a Called Procedure Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions SYSENTER and SYSEXIT Instructions in IA-32e Mode Fast System Calls in 64-Bit Mode PRIVILEGED INSTRUCTIONS POINTER VALIDATION Checking Access Rights (LAR Instruction) Checking Read/Write Rights (VERR and VERW Instructions) Checking That the Pointer Offset Is Within Limits (LSL Instruction) Checking Caller Access Privileges (ARPL Instruction) Checking Alignment PAGE-LEVEL PROTECTION Page-Protection Flags Restricting Addressable Domain Page Type Combining Protection of Both Levels of Page Tables Overrides to Page Protection COMBINING PAGE AND SEGMENT PROTECTION PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT Detecting and Enabling the Execute-Disable Capability Execute-Disable Page Protection Reserved Bit Checking Exception Handling CHAPTER 6 INTERRUPT AND EXCEPTION HANDLING 6.1 INTERRUPT AND EXCEPTION OVERVIEW EXCEPTION AND INTERRUPT VECTORS SOURCES OF INTERRUPTS External Interrupts Maskable Hardware Interrupts Software-Generated Interrupts SOURCES OF EXCEPTIONS Program-Error Exceptions Software-Generated Exceptions Machine-Check Exceptions EXCEPTION CLASSIFICATIONS PAGE Vol. 3A v

6 CONTENTS 6.6 PROGRAM OR TASK RESTART NONMASKABLE INTERRUPT (NMI) Handling Multiple NMIs ENABLING AND DISABLING INTERRUPTS Masking Maskable Hardware Interrupts Masking Instruction Breakpoints Masking Exceptions and Interrupts When Switching Stacks PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND INTERRUPTS INTERRUPT DESCRIPTOR TABLE (IDT) IDT DESCRIPTORS EXCEPTION AND INTERRUPT HANDLING Exception- or Interrupt-Handler Procedures Protection of Exception- and Interrupt-Handler Procedures Flag Usage By Exception- or Interrupt-Handler Procedure Interrupt Tasks ERROR CODE EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE Bit Mode IDT Bit Mode Stack Frame IRET in IA-32e Mode Stack Switching in IA-32e Mode Interrupt Stack Table EXCEPTION AND INTERRUPT REFERENCE Interrupt 0 Divide Error Exception (#DE) Interrupt 1 Debug Exception (#DB) Interrupt 2 NMI Interrupt Interrupt 3 Breakpoint Exception (#BP) Interrupt 4 Overflow Exception (#OF) Interrupt 5 BOUND Range Exceeded Exception (#BR) Interrupt 6 Invalid Opcode Exception (#UD) Interrupt 7 Device Not Available Exception (#NM) Interrupt 8 Double Fault Exception (#DF) Interrupt 9 Coprocessor Segment Overrun Interrupt 10 Invalid TSS Exception (#TS) Interrupt 11 Segment Not Present (#NP) Interrupt 12 Stack Fault Exception (#SS) Interrupt 13 General Protection Exception (#GP) Interrupt 14 Page-Fault Exception (#PF) Interrupt 16 x87 FPU Floating-Point Error (#MF) Interrupt 17 Alignment Check Exception (#AC) Interrupt 18 Machine-Check Exception (#MC) Interrupt 19 SIMD Floating-Point Exception (#XM) Interrupt 20 Virtualization Exception (#VE) Interrupts 32 to 255 User Defined Interrupts CHAPTER 7 TASK MANAGEMENT 7.1 TASK MANAGEMENT OVERVIEW Task Structure Task State Executing a Task TASK MANAGEMENT DATA STRUCTURES Task-State Segment (TSS) TSS Descriptor TSS Descriptor in 64-bit mode Task Register Task-Gate Descriptor TASK SWITCHING TASK LINKING Use of Busy Flag To Prevent Recursive Task Switching Modifying Task Linkages PAGE vi Vol. 3A

7 CONTENTS 7.5 TASK ADDRESS SPACE Mapping Tasks to the Linear and Physical Address Spaces Task Logical Address Space BIT TASK-STATE SEGMENT (TSS) TASK MANAGEMENT IN 64-BIT MODE CHAPTER 8 MULTIPLE-PROCESSOR MANAGEMENT 8.1 LOCKED ATOMIC OPERATIONS Guaranteed Atomic Operations Bus Locking Automatic Locking Software Controlled Bus Locking Handling Self- and Cross-Modifying Code Effects of a LOCK Operation on Internal Processor Caches MEMORY ORDERING Memory Ordering in the Intel Pentium and Intel486 Processors Memory Ordering in P6 and More Recent Processor Families Examples Illustrating the Memory-Ordering Principles Assumptions, Terminology, and Notation Neither Loads Nor Stores Are Reordered with Like Operations Stores Are Not Reordered With Earlier Loads Loads May Be Reordered with Earlier Stores to Different Locations Intra-Processor Forwarding Is Allowed Stores Are Transitively Visible Stores Are Seen in a Consistent Order by Other Processors Locked Instructions Have a Total Order Loads and Stores Are Not Reordered with Locked Instructions Fast-String Operation and Out-of-Order Stores Memory-Ordering Model for String Operations on Write-Back (WB) Memory Examples Illustrating Memory-Ordering Principles for String Operations Strengthening or Weakening the Memory-Ordering Model SERIALIZING INSTRUCTIONS MULTIPLE-PROCESSOR (MP) INITIALIZATION BSP and AP Processors MP Initialization Protocol Requirements and Restrictions MP Initialization Protocol Algorithm for MP Systems MP Initialization Example Typical BSP Initialization Sequence Typical AP Initialization Sequence Identifying Logical Processors in an MP System INTEL HYPER-THREADING TECHNOLOGY AND INTEL MULTI-CORE TECHNOLOGY DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY Initializing Processors Supporting Hyper-Threading Technology Initializing Multi-Core Processors Executing Multiple Threads on an Intel 64 or IA-32 Processor Supporting Hardware Multi-Threading Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading INTEL HYPER-THREADING TECHNOLOGY ARCHITECTURE State of the Logical Processors APIC Functionality Memory Type Range Registers (MTRR) Page Attribute Table (PAT) Machine Check Architecture Debug Registers and Extensions Performance Monitoring Counters IA32_MISC_ENABLE MSR Memory Ordering Serializing Instructions Microcode Update Resources Self Modifying Code Implementation-Specific Intel HT Technology Facilities Processor Caches Processor Translation Lookaside Buffers (TLBs) Thermal Monitor PAGE Vol. 3A vii

8 CONTENTS External Signal Compatibility MULTI-CORE ARCHITECTURE Logical Processor Support Memory Type Range Registers (MTRR) Performance Monitoring Counters IA32_MISC_ENABLE MSR Microcode Update Resources PROGRAMMING CONSIDERATIONS FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS Hierarchical Mapping of Shared Resources Hierarchical Mapping of CPUID Extended Topology Leaf Hierarchical ID of Logical Processors in an MP System Hierarchical ID of Logical Processors with x2apic ID Algorithm for Three-Level Mappings of APIC_ID Identifying Topological Relationships in a MP System MANAGEMENT OF IDLE AND BLOCKED CONDITIONS HLT Instruction PAUSE Instruction Detecting Support MONITOR/MWAIT Instruction MONITOR/MWAIT Instruction Monitor/Mwait Address Range Determination Required Operating System Support Use the PAUSE Instruction in Spin-Wait Loops Potential Usage of MONITOR/MWAIT in C0 Idle Loops Halt Idle Logical Processors Potential Usage of MONITOR/MWAIT in C1 Idle Loops Guidelines for Scheduling Threads on Logical Processors Sharing Execution Resources Eliminate Execution-Based Timing Loops Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory MP INITIALIZATION FOR P6 FAMILY PROCESSORS Overview of the MP Initialization Process For P6 Family Processors MP Initialization Protocol Algorithm Error Detection and Handling During the MP Initialization Protocol CHAPTER 9 PROCESSOR MANAGEMENT AND INITIALIZATION 9.1 INITIALIZATION OVERVIEW Processor State After Reset Processor Built-In Self-Test (BIST) Model and Stepping Information First Instruction Executed X87 FPU INITIALIZATION Configuring the x87 FPU Environment Setting the Processor for x87 FPU Software Emulation CACHE ENABLING MODEL-SPECIFIC REGISTERS (MSRS) MEMORY TYPE RANGE REGISTERS (MTRRS) INITIALIZING SSE/SSE2/SSE3/SSSE3 EXTENSIONS SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION Real-Address Mode IDT NMI Interrupt Handling SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION Protected-Mode System Data Structures Initializing Protected-Mode Exceptions and Interrupts Initializing Paging Initializing Multitasking Initializing IA-32e Mode IA-32e Mode System Data Structures IA-32e Mode Interrupts and Exceptions bit Mode and Compatibility Mode Operation Switching Out of IA-32e Mode Operation MODE SWITCHING Switching to Protected Mode Switching Back to Real-Address Mode INITIALIZATION AND MODE SWITCHING EXAMPLE PAGE viii Vol. 3A

9 Vol. 3A ix CONTENTS PAGE Assembler Usage STARTUP.ASM Listing MAIN.ASM Source Code Supporting Files MICROCODE UPDATE FACILITIES Microcode Update Optional Extended Signature Table Processor Identification Platform Identification Microcode Update Checksum Microcode Update Loader Hard Resets in Update Loading Update in a Multiprocessor System Update in a System Supporting Intel Hyper-Threading Technology Update in a System Supporting Dual-Core Technology Update Loader Enhancements Update Signature and Verification Determining the Signature Authenticating the Update Optional Processor Microcode Update Specifications Responsibilities of the BIOS Responsibilities of the Calling Program Microcode Update Functions INT 15H-based Interface Function 00H Presence Test Function 01H Write Microcode Update Data Function 02H Microcode Update Control Function 03H Read Microcode Update Data Return Codes CHAPTER 10 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC) 10.1 LOCAL AND I/O APIC OVERVIEW SYSTEM BUS VS. APIC BUS THE INTEL 82489DX EXTERNAL APIC, THE APIC, THE XAPIC, AND THE X2APIC LOCAL APIC The Local APIC Block Diagram Presence of the Local APIC Enabling or Disabling the Local APIC Local APIC Status and Location Relocating the Local APIC Registers Local APIC ID Local APIC State Local APIC State After Power-Up or Reset Local APIC State After It Has Been Software Disabled Local APIC State After an INIT Reset ( Wait-for-SIPI State) Local APIC State After It Receives an INIT-Deassert IPI Local APIC Version Register HANDLING LOCAL INTERRUPTS Local Vector Table Valid Interrupt Vectors Error Handling APIC Timer TSC-Deadline Mode Local Interrupt Acceptance ISSUING INTERPROCESSOR INTERRUPTS Interrupt Command Register (ICR) Determining IPI Destination Physical Destination Mode Logical Destination Mode Broadcast/Self Delivery Mode Lowest Priority Delivery Mode

10 CONTENTS IPI Delivery and Acceptance SYSTEM AND APIC BUS ARBITRATION HANDLING INTERRUPTS Interrupt Handling with the Pentium 4 and Intel Xeon Processors Interrupt Handling with the P6 Family and Pentium Processors Interrupt, Task, and Processor Priority Task and Processor Priorities Interrupt Acceptance for Fixed Interrupts Signaling Interrupt Servicing Completion Task Priority in IA-32e Mode Interaction of Task Priorities between CR8 and APIC SPURIOUS INTERRUPT APIC BUS MESSAGE PASSING MECHANISM AND PROTOCOL (P6 FAMILY, PENTIUM PROCESSORS) Bus Message Formats MESSAGE SIGNALLED INTERRUPTS Message Address Register Format Message Data Register Format EXTENDED XAPIC (X2APIC) Detecting and Enabling x2apic Mode Instructions to Access APIC Registers x2apic Register Address Space Reserved Bit Checking x2apic Register Availability MSR Access in x2apic Mode VM-Exit Controls for MSRs and x2apic Registers x2apic State Transitions x2apic States x2apic After Reset x2apic Transitions From x2apic Mode x2apic Transitions From Disabled Mode State Changes From xapic Mode to x2apic Mode Routing of Device Interrupts in x2apic Mode Initialization by System Software CPUID Extensions And Topology Enumeration Consistency of APIC IDs and CPUID ICR Operation in x2apic Mode Determining IPI Destination in x2apic Mode Logical Destination Mode in x2apic Mode Deriving Logical x2apic ID from the Local x2apic ID SELF IPI Register APIC BUS MESSAGE FORMATS Bus Message Formats EOI Message Short Message Non-focused Lowest Priority Message APIC Bus Status Cycles CHAPTER 11 MEMORY CACHE CONTROL 11.1 INTERNAL CACHES, TLBS, AND BUFFERS CACHING TERMINOLOGY METHODS OF CACHING AVAILABLE Buffering of Write Combining Memory Locations Choosing a Memory Type Code Fetches in Uncacheable Memory CACHE CONTROL PROTOCOL CACHE CONTROL Cache Control Registers and Bits Precedence of Cache Controls Selecting Memory Types for Pentium Pro and Pentium II Processors Selecting Memory Types for Pentium III and More Recent Processor Families Writing Values Across Pages with Different Memory Types PAGE x Vol. 3A

11 CONTENTS Preventing Caching Disabling and Enabling the L3 Cache Cache Management Instructions L1 Data Cache Context Mode Adaptive Mode Shared Mode SELF-MODIFYING CODE IMPLICIT CACHING (PENTIUM 4, INTEL XEON, AND P6 FAMILY PROCESSORS) EXPLICIT CACHING INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) STORE BUFFER MEMORY TYPE RANGE REGISTERS (MTRRS) MTRR Feature Identification Setting Memory Ranges with MTRRs IA32_MTRR_DEF_TYPE MSR Fixed Range MTRRs Variable Range MTRRs System-Management Range Register Interface Example Base and Mask Calculations Base and Mask Calculations for Greater-Than 36-bit Physical Address Support Range Size and Alignment Requirement MTRR Precedences MTRR Initialization Remapping Memory Types MTRR Maintenance Programming Interface MemTypeGet() Function MemTypeSet() Function MTRR Considerations in MP Systems Large Page Size Considerations PAGE ATTRIBUTE TABLE (PAT) Detecting Support for the PAT Feature IA32_PAT MSR Selecting a Memory Type from the PAT Programming the PAT PAT Compatibility with Earlier IA-32 Processors CHAPTER 12 INTEL MMX TECHNOLOGY SYSTEM PROGRAMMING 12.1 EMULATION OF THE MMX INSTRUCTION SET THE MMX STATE AND MMX REGISTER ALIASING Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag Word SAVING AND RESTORING THE MMX STATE AND REGISTERS SAVING MMX STATE ON TASK OR CONTEXT SWITCHES EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX INSTRUCTIONS Effect of MMX Instructions on Pending x87 Floating-Point Exceptions DEBUGGING MMX CODE CHAPTER 13 SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES 13.1 PROVIDING OPERATING SYSTEM SUPPORT FOR SSE EXTENSIONS Adding Support to an Operating System for SSE Extensions Checking for CPU Support Initialization of the SSE Extensions Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE Instructions Providing a Handler for the SIMD Floating-Point Exception (#XM) Numeric Error flag and IGNNE# EMULATION OF SSE EXTENSIONS SAVING AND RESTORING SSE STATE DESIGNING OS FACILITIES FOR SAVING X87 FPU, SSE AND EXTENDED STATES ON TASK OR CONTEXT SWITCHES PAGE Vol. 3A xi

12 CONTENTS Using the TS Flag to Control the Saving of the x87 FPU and SSE State THE XSAVE FEATURE SET AND PROCESSOR EXTENDED STATE MANAGEMENT Checking the Support for XSAVE Feature Set Determining the XSAVE Managed Feature States And The Required Buffer Size Enable the Use Of XSAVE Feature Set And XSAVE State Components Provide an Initialization for the XSAVE State Components Providing the Required Exception Handlers INTEROPERABILITY OF THE XSAVE FEATURE SET AND FXSAVE/FXRSTOR THE XSAVE FEATURE SET AND PROCESSOR SUPERVISOR STATE MANAGEMENT SYSTEM PROGRAMMING FOR XSAVE MANAGED FEATURES Intel Advanced Vector Extensions (Intel AVX) Intel Advanced Vector Extensions 512 (Intel AVX-512) CHAPTER 14 POWER AND THERMAL MANAGEMENT 14.1 ENHANCED INTEL SPEEDSTEP TECHNOLOGY Software Interface For Initiating Performance State Transitions P-STATE HARDWARE COORDINATION SYSTEM SOFTWARE CONSIDERATIONS AND OPPORTUNISTIC PROCESSOR PERFORMANCE OPERATION Intel Dynamic Acceleration System Software Interfaces for Opportunistic Processor Performance Operation Discover Hardware Support and Enabling of Opportunistic Processor Operation OS Control of Opportunistic Processor Performance Operation Required Changes to OS Power Management P-state Policy Application Awareness of Opportunistic Processor Operation (Optional) Intel Turbo Boost Technology Performance and Energy Bias Hint support HARDWARE-CONTROLLED PERFORMANCE STATES (HWP) HWP Programming Interfaces Enabling HWP HWP Performance Range and Dynamic Capabilities Managing HWP HWP Feedback Non-Architectural HWP Feedback HWP Notifications Recommendations for OS use of HWP Controls HARDWARE DUTY CYCLING (HDC) Hardware Duty Cycling Programming Interfaces Package level Enabling HDC Logical-Processor Level HDC Control HDC Residency Counters IA32_THREAD_STALL Non-Architectural HDC Residency Counters MPERF and APERF Counters Under HDC MWAIT EXTENSIONS FOR ADVANCED POWER MANAGEMENT THERMAL MONITORING AND PROTECTION Catastrophic Shutdown Detector Thermal Monitor Thermal Monitor Thermal Monitor Two Methods for Enabling TM Performance State Transitions and Thermal Monitoring Thermal Status Information Adaptive Thermal Monitor Software Controlled Clock Modulation Extension of Software Controlled Clock Modulation Detection of Thermal Monitor and Software Controlled Clock Modulation Facilities Detection of Software Controlled Clock Modulation Extension On Die Digital Thermal Sensors Digital Thermal Sensor Enumeration Reading the Digital Sensor Power Limit Notification PACKAGE LEVEL THERMAL MANAGEMENT PAGE xii Vol. 3A

13 CONTENTS Support for Passive and Active cooling PLATFORM SPECIFIC POWER MANAGEMENT SUPPORT RAPL Interfaces RAPL Domains and Platform Specificity Package RAPL Domain PP0/PP1 RAPL Domains DRAM RAPL Domain CHAPTER 15 MACHINE-CHECK ARCHITECTURE 15.1 MACHINE-CHECK ARCHITECTURE COMPATIBILITY WITH PENTIUM PROCESSOR MACHINE-CHECK MSRS Machine-Check Global Control MSRs IA32_MCG_CAP MSR IA32_MCG_STATUS MSR IA32_MCG_CTL MSR IA32_MCG_EXT_CTL MSR Enabling Local Machine Check Error-Reporting Register Banks IA32_MCi_CTL MSRs IA32_MCi_STATUS MSRS IA32_MCi_ADDR MSRs IA32_MCi_MISC MSRs IA32_MCi_CTL2 MSRs IA32_MCG Extended Machine Check State MSRs Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture ENHANCED CACHE ERROR REPORTING CORRECTED MACHINE CHECK ERROR INTERRUPT CMCI Local APIC Interface System Software Recommendation for Managing CMCI and Machine Check Resources CMCI Initialization CMCI Threshold Management CMCI Interrupt Handler RECOVERY OF UNCORRECTED RECOVERABLE (UCR) ERRORS Detection of Software Error Recovery Support UCR Error Reporting and Logging UCR Error Classification UCR Error Overwrite Rules MACHINE-CHECK AVAILABILITY MACHINE-CHECK INITIALIZATION INTERPRETING THE MCA ERROR CODES Simple Error Codes Compound Error Codes Correction Report Filtering (F) Bit Transaction Type (TT) Sub-Field Level (LL) Sub-Field Request (RRRR) Sub-Field Bus and Interconnect Errors Memory Controller Errors Architecturally Defined UCR Errors Architecturally Defined SRAO Errors Architecturally Defined SRAR Errors Multiple MCA Errors Machine-Check Error Codes Interpretation GUIDELINES FOR WRITING MACHINE-CHECK SOFTWARE Machine-Check Exception Handler Pentium Processor Machine-Check Exception Handling Logging Correctable Machine-Check Errors Machine-Check Software Handler Guidelines for Error Recovery Machine-Check Exception Handler for Error Recovery Corrected Machine-Check Handler for Error Recovery PAGE Vol. 3A xiii

14 CONTENTS CHAPTER 16 INTERPRETING MACHINE-CHECK ERROR CODES 16.1 INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY 06H MACHINE ERROR CODES FOR MACHINE CHECK INCREMENTAL DECODING INFORMATION: INTEL CORE 2 PROCESSOR FAMILY MACHINE ERROR CODES FOR MACHINE CHECK Model-Specific Machine Check Error Codes for Intel Xeon Processor 7400 Series Processor Machine Check Status Register Incremental MCA Error Code Definition Intel Xeon Processor 7400 Model Specific Error Code Field Processor Model Specific Error Code Field Type B: Bus and Interconnect Error Processor Model Specific Error Code Field Type C: Cache Bus Controller Error INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_1AH, MACHINE ERROR CODES FOR MACHINE CHECK Intel QPI Machine Check Errors Internal Machine Check Errors Memory Controller Errors INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_2DH, MACHINE ERROR CODES FOR MACHINE CHECK Internal Machine Check Errors Intel QPI Machine Check Errors Integrated Memory Controller Machine Check Errors INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_3EH, MACHINE ERROR CODES FOR MACHINE CHECK Internal Machine Check Errors Integrated Memory Controller Machine Check Errors INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY WITH CPUID DISPLAYFAMILY_DISPLAYMODEL SIGNATURE 06_3FH, MACHINE ERROR CODES FOR MACHINE CHECK Internal Machine Check Errors Intel QPI Machine Check Errors Integrated Memory Controller Machine Check Errors INCREMENTAL DECODING INFORMATION: PROCESSOR FAMILY 0FH MACHINE ERROR CODES FOR MACHINE CHECK Model-Specific Machine Check Error Codes for Intel Xeon Processor MP 7100 Series Processor Machine Check Status Register MCA Error Code Definition Other_Info Field (all MCA Error Types) Processor Model Specific Error Code Field MCA Error Type A: L3 Error Processor Model Specific Error Code Field Type B: Bus and Interconnect Error Processor Model Specific Error Code Field Type C: Cache Bus Controller Error CHAPTER 17 DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES 17.1 OVERVIEW OF DEBUG SUPPORT FACILITIES DEBUG REGISTERS Debug Address Registers (DR0-DR3) Debug Registers DR4 and DR Debug Status Register (DR6) Debug Control Register (DR7) Breakpoint Field Recognition Debug Registers and Intel 64 Processors DEBUG EXCEPTIONS Debug Exception (#DB) Interrupt Vector Instruction-Breakpoint Exception Condition Data Memory and I/O Breakpoint Exception Conditions General-Detect Exception Condition Single-Step Exception Condition Task-Switch Exception Condition Breakpoint Exception (#BP) Interrupt Vector Debug Exceptions, Breakpoint Exceptions, and Restricted Transactional Memory (RTM) LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING OVERVIEW PAGE xiv Vol. 3A

15 CONTENTS IA32_DEBUGCTL MSR Monitoring Branches, Exceptions, and Interrupts Single-Stepping on Branches Branch Trace Messages Branch Trace Message Visibility Branch Trace Store (BTS) CPL-Qualified Branch Trace Mechanism Freezing LBR and Performance Counters on PMI LBR Stack LBR Stack and Intel 64 Processors LBR Stack and IA-32 Processors Last Exception Records and Intel 64 Architecture BTS and DS Save Area Bit Format of the DS Save Area Setting Up the DS Save Area Setting Up the BTS Buffer Setting Up CPL-Qualified BTS Writing the DS Interrupt Service Routine LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL CORE 2 DUO AND INTEL ATOM PROCESSOR FAMILY) LBR Stack LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON INTEL MICROARCHITECTURE CODE NAME NEHALEM LBR Stack Filtering of Last Branch Records LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON INTEL MICROARCHITECTURE CODE NAME SANDY BRIDGE LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON HASWELL MICROARCHITECTURE LBR Stack Enhancement LAST BRANCH, CALL STACK, INTERRUPT, AND EXCEPTION RECORDING FOR PROCESSORS BASED ON SKYLAKE MICROARCHITECTURE MSR_LBR_INFO_x MSR Streamlined Freeze_LBRs_On_PMI Operation LBR behavior on software C LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PROCESSORS BASED ON INTEL NETBURST MICROARCHITECTURE) MSR_DEBUGCTLA MSR LBR Stack for Processors Based on Intel NetBurst Microarchitecture Last Exception Records LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL CORE SOLO AND INTEL CORE DUO PROCESSORS) LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PENTIUM M PROCESSORS) LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (P6 FAMILY PROCESSORS) DEBUGCTLMSR Register Last Branch and Last Exception MSRs Monitoring Branches, Exceptions, and Interrupts TIME-STAMP COUNTER Invariant TSC IA32_TSC_AUX Register and RDTSCP Support Time-Stamp Counter Adjustment Invariant Time-Keeping PLATFORM SHARED RESOURCE MONITORING: CACHE MONITORING TECHNOLOGY Overview of Cache Monitoring Technology and Memory Bandwidth Monitoring Enabling Monitoring: Usage Flow Enumeration and Detecting Support of Cache Monitoring Technology and Memory Bandwidth Monitoring Monitoring Resource Type and Capability Enumeration Feature-Specific Enumeration Cache Monitoring Technology Memory Bandwidth Monitoring Monitoring Resource RMID Association Monitoring Resource Selection and Reporting Infrastructure Monitoring Programming Considerations Monitoring Dynamic Configuration PAGE Vol. 3A xv

16 CONTENTS Monitoring Operation With Power Saving Features Monitoring Operation with Other Operating Modes Monitoring Operation with RAS Features PLATFORM SHARED RESOURCE CONTROL: CACHE ALLOCATION TECHNOLOGY Cache Allocation Technology Architecture Code and Data Prioritization (CDP) Technology Enabling Cache Allocation Technology Usage Flow Enumeration and Detection Support of Cache Allocation Technology Cache Allocation Technology: Resource Type and Capability Enumeration Cache Mask Configuration Cache Mask Association Enumerating and Enabling CDP Technology Mapping Between CDP Masks and CAT Masks Disabling CDP Cache Allocation Technology Programming Considerations Cache Allocation Technology Dynamic Configuration Cache Allocation Technology Operation With Power Saving Features Cache Allocation Technology Operation with Other Operating Modes Associating Threads with CAT/CDP Classes of Service CHAPTER 18 PERFORMANCE MONITORING 18.1 PERFORMANCE MONITORING OVERVIEW ARCHITECTURAL PERFORMANCE MONITORING Architectural Performance Monitoring Version Architectural Performance Monitoring Version 1 Facilities Pre-defined Architectural Performance Events Architectural Performance Monitoring Version Architectural Performance Monitoring Version AnyThread Counting and Software Evolution Architectural Performance Monitoring Version Enhancement in IA32_PERF_GLOBAL_STATUS IA32_PERF_GLOBAL_STATUS_RESET and IA32_PERF_GLOBAL_STATUS_SET MSRS IA32_PERF_GLOBAL_INUSE MSR Full-Width Writes to Performance Counter Registers PERFORMANCE MONITORING (INTEL CORE SOLO AND INTEL CORE DUO PROCESSORS) PERFORMANCE MONITORING (PROCESSORS BASED ON INTEL CORE MICROARCHITECTURE) Fixed-function Performance Counters Global Counter Control Facilities At-Retirement Events Precise Event Based Sampling (PEBS) Setting up the PEBS Buffer PEBS Record Format Writing a PEBS Interrupt Service Routine Re-configuring PEBS Facilities PERFORMANCE MONITORING (PROCESSORS BASED ON INTEL ATOM MICROARCHITECTURE) PERFORMANCE MONITORING (PROCESSORS BASED ON THE SILVERMONT MICROARCHITECTURE) Enhancements of Performance Monitoring in the Processor Core Precise Event Based Sampling (PEBS) Offcore Response Event Average Offcore Request Latency Measurement PERFORMANCE MONITORING FOR PROCESSORS BASED ON INTEL MICROARCHITECTURE CODE NAME NEHALEM Enhancements of Performance Monitoring in the Processor Core Precise Event Based Sampling (PEBS) Load Latency Performance Monitoring Facility Off-core Response Performance Monitoring in the Processor Core Performance Monitoring Facility in the Uncore Uncore Performance Monitoring Management Facility Uncore Performance Event Configuration Facility Uncore Address/Opcode Match MSR Intel Xeon Processor 7500 Series Performance Monitoring Facility Performance Monitoring for Processors Based on Intel Microarchitecture Code Name Westmere Intel Xeon Processor E7 Family Performance Monitoring Facility PAGE xvi Vol. 3A

17 CONTENTS 18.8 PERFORMANCE MONITORING FOR PROCESSORS BASED ON INTEL MICROARCHITECTURE CODE NAME SANDY BRIDGE Global Counter Control Facilities In Intel Microarchitecture Code Name Sandy Bridge Counter Coalescence Full Width Writes to Performance Counters PEBS Support in Intel Microarchitecture Code Name Sandy Bridge PEBS Record Format Load Latency Performance Monitoring Facility Precise Store Facility Precise Distribution of Instructions Retired (PDIR) Off-core Response Performance Monitoring Uncore Performance Monitoring Facilities In Intel Core i7-2xxx, Intel Core i5-2xxx, Intel Core i3-2xxx Processor Series Uncore Performance Monitoring Events Intel Xeon Processor E5 Family Performance Monitoring Facility Intel Xeon Processor E5 Family Uncore Performance Monitoring Facility RD GENERATION INTEL CORE PROCESSOR PERFORMANCE MONITORING FACILITY Intel Xeon Processor E5 v2 and E7 v2 Family Uncore Performance Monitoring Facility TH GENERATION INTEL CORE PROCESSOR PERFORMANCE MONITORING FACILITY Precise Event Based Sampling (PEBS) Facility PEBS Data Format PEBS Data Address Profiling EventingIP Record Off-core Response Performance Monitoring Off-core Response Performance Monitoring in Intel Xeon Processors E5 v3 Series Performance Monitoring and Intel TSX Intel TSX and PEBS Support Uncore Performance Monitoring Facilities in the 4th Generation Intel Core Processors Intel Xeon Processor E5 v3 Family Uncore Performance Monitoring Facility INTEL CORE M PROCESSOR PERFORMANCE MONITORING FACILITY SIXTH GENERATION INTEL CORE PROCESSOR PERFORMANCE MONITORING FACILITY Precise Event Based Sampling (PEBS) Facility PEBS Data Format PEBS Events Data Address Profiling PEBS Facility for Front End Events FRONTEND_RETIRED Off-core Response Performance Monitoring PERFORMANCE MONITORING (PROCESSORS BASED ON INTEL NETBURST MICROARCHITECTURE) ESCR MSRs Performance Counters CCCR MSRs Debug Store (DS) Mechanism Programming the Performance Counters for Non-Retirement Events Selecting Events to Count Filtering Events Starting Event Counting Reading a Performance Counter s Count Halting Event Counting Cascading Counters EXTENDED CASCADING Generating an Interrupt on Overflow Counter Usage Guideline At-Retirement Counting Using At-Retirement Counting Tagging Mechanism for Front_end_event Tagging Mechanism For Execution_event Tagging Mechanism for Replay_event Precise Event-Based Sampling (PEBS) Detection of the Availability of the PEBS Facilities Setting Up the DS Save Area Setting Up the PEBS Buffer Writing a PEBS Interrupt Service Routine Other DS Mechanism Implications PAGE Vol. 3A xvii

18 CONTENTS Operating System Implications PERFORMANCE MONITORING AND INTEL HYPER-THREADING TECHNOLOGY IN PROCESSORS BASED ON INTEL NETBURST MICROARCHITECTURE ESCR MSRs CCCR MSRs IA32_PEBS_ENABLE MSR Performance Monitoring Events COUNTING CLOCKS Non-Halted Clockticks Non-Sleep Clockticks Incrementing the Time-Stamp Counter Non-Halted Reference Clockticks Cycle Counting and Opportunistic Processor Operation IA32_PERF_CAPABILITIES MSR ENUMERATION Filtering of SMM Handler Overhead PERFORMANCE MONITORING AND DUAL-CORE TECHNOLOGY PERFORMANCE MONITORING ON 64-BIT INTEL XEON PROCESSOR MP WITH UP TO 8-MBYTE L3 CACHE PERFORMANCE MONITORING ON L3 AND CACHING BUS CONTROLLER SUB-SYSTEMS Overview of Performance Monitoring with L3/Caching Bus Controller GBSQ Event Interface GSNPQ Event Interface FSB Event Interface FSB Sub-Event Mask Interface Common Event Control Interface PERFORMANCE MONITORING (P6 FAMILY PROCESSOR) PerfEvtSel0 and PerfEvtSel1 MSRs PerfCtr0 and PerfCtr1 MSRs Starting and Stopping the Performance-Monitoring Counters Event and Time-Stamp Monitoring Software Monitoring Counter Overflow PERFORMANCE MONITORING (PENTIUM PROCESSORS) Control and Event Select Register (CESR) Use of the Performance-Monitoring Pins Events Counted CHAPTER 19 PERFORMANCE-MONITORING EVENTS 19.1 ARCHITECTURAL PERFORMANCE-MONITORING EVENTS PERFORMANCE MONITORING EVENTS FOR NEXT GENERATION INTEL CORE PROCESSOR PERFORMANCE MONITORING EVENTS FOR THE INTEL CORE M AND FIFTH GENERATION INTEL CORE PROCESSORS PERFORMANCE MONITORING EVENTS FOR THE 4TH GENERATION INTEL CORE PROCESSORS Performance Monitoring Events in the Processor Core of Intel Xeon Processor E5 v3 Family PERFORMANCE MONITORING EVENTS FOR 3RD GENERATION INTEL CORE PROCESSORS Performance Monitoring Events in the Processor Core of Intel Xeon Processor E5 v2 Family and Intel Xeon Processor E7 v2 Family PERFORMANCE MONITORING EVENTS FOR 2ND GENERATION INTEL CORE I7-2XXX, INTEL CORE I5-2XXX, INTEL CORE I3-2XXX PROCESSOR SERIES PERFORMANCE MONITORING EVENTS FOR INTEL CORE I7 PROCESSOR FAMILY AND INTEL XEON PROCESSOR FAMILY PERFORMANCE MONITORING EVENTS FOR PROCESSORS BASED ON INTEL MICROARCHITECTURE CODE NAME WESTMERE PERFORMANCE MONITORING EVENTS FOR INTEL XEON PROCESSOR 5200, 5400 SERIES AND INTEL CORE 2 EXTREME PROCESSORS QX 9000 SERIES PERFORMANCE MONITORING EVENTS FOR INTEL XEON PROCESSOR 3000, 3200, 5100, 5300 SERIES AND INTEL CORE 2 DUO PROCESSORS PERFORMANCE MONITORING EVENTS FOR PROCESSORS BASED ON THE SILVERMONT MICROARCHITECTURE Performance Monitoring Events for Processors Based on the Airmont Microarchitecture PERFORMANCE MONITORING EVENTS FOR INTEL ATOM PROCESSORS PERFORMANCE MONITORING EVENTS FOR INTEL CORE SOLO AND INTEL CORE DUO PROCESSORS PENTIUM 4 AND INTEL XEON PROCESSOR PERFORMANCE-MONITORING EVENTS PERFORMANCE MONITORING EVENTS FOR INTEL PENTIUM M PROCESSORS P6 FAMILY PROCESSOR PERFORMANCE-MONITORING EVENTS PENTIUM PROCESSOR PERFORMANCE-MONITORING EVENTS PAGE xviii Vol. 3A

19 CONTENTS CHAPTER EMULATION 20.1 REAL-ADDRESS MODE Address Translation in Real-Address Mode Registers Supported in Real-Address Mode Instructions Supported in Real-Address Mode Interrupt and Exception Handling VIRTUAL-8086 MODE Enabling Virtual-8086 Mode Structure of a Virtual-8086 Task Paging of Virtual-8086 Tasks Protection within a Virtual-8086 Task Entering Virtual-8086 Mode Leaving Virtual-8086 Mode Sensitive Instructions Virtual-8086 Mode I/O I/O-Port-Mapped I/O Memory-Mapped I/O Special I/O Buffers INTERRUPT AND EXCEPTION HANDLING IN VIRTUAL-8086 MODE Class 1 Hardware Interrupt and Exception Handling in Virtual-8086 Mode Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate Handling an Interrupt or Exception With an 8086 Program Interrupt or Exception Handler Handling an Interrupt or Exception Through a Task Gate Class 2 Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism Class 3 Software Interrupt Handling in Virtual-8086 Mode Method 1: Software Interrupt Handling Methods 2 and 3: Software Interrupt Handling Method 4: Software Interrupt Handling Method 5: Software Interrupt Handling Method 6: Software Interrupt Handling PROTECTED-MODE VIRTUAL INTERRUPTS CHAPTER 21 MIXING 16-BIT AND 32-BIT CODE 21.1 DEFINING 16-BIT AND 32-BIT PROGRAM MODULES MIXING 16-BIT AND 32-BIT OPERATIONS WITHIN A CODE SEGMENT SHARING DATA AMONG MIXED-SIZE CODE SEGMENTS TRANSFERRING CONTROL AMONG MIXED-SIZE CODE SEGMENTS Code-Segment Pointer Size Stack Management for Control Transfer Controlling the Operand-Size Attribute For a Call Passing Parameters With a Gate Interrupt Control Transfers Parameter Translation Writing Interface Procedures CHAPTER 22 ARCHITECTURE COMPATIBILITY 22.1 PROCESSOR FAMILIES AND CATEGORIES RESERVED BITS ENABLING NEW FUNCTIONS AND MODES DETECTING THE PRESENCE OF NEW FEATURES THROUGH SOFTWARE INTEL MMX TECHNOLOGY STREAMING SIMD EXTENSIONS (SSE) STREAMING SIMD EXTENSIONS 2 (SSE2) STREAMING SIMD EXTENSIONS 3 (SSE3) ADDITIONAL STREAMING SIMD EXTENSIONS INTEL HYPER-THREADING TECHNOLOGY MULTI-CORE TECHNOLOGY SPECIFIC FEATURES OF DUAL-CORE PROCESSOR NEW INSTRUCTIONS IN THE PENTIUM AND LATER IA-32 PROCESSORS PAGE Vol. 3A xix

20 CONTENTS xx Vol. 3A PAGE Instructions Added Prior to the Pentium Processor OBSOLETE INSTRUCTIONS UNDEFINED OPCODES NEW FLAGS IN THE EFLAGS REGISTER Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors STACK OPERATIONS PUSH SP EFLAGS Pushed on the Stack X87 FPU Control Register CR0 Flags x87 FPU Status Word Condition Code Flags (C0 through C3) Stack Fault Flag x87 FPU Control Word x87 FPU Tag Word Data Types NaNs Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats Floating-Point Exceptions Denormal Operand Exception (#D) Numeric Overflow Exception (#O) Numeric Underflow Exception (#U) Exception Precedence CS and EIP For FPU Exceptions FPU Error Signals Assertion of the FERR# Pin Invalid Operation Exception On Denormals Alignment Check Exceptions (#AC) Segment Not Present Exception During FLDENV Device Not Available Exception (#NM) Coprocessor Segment Overrun Exception General Protection Exception (#GP) Floating-Point Error Exception (#MF) Changes to Floating-Point Instructions FDIV, FPREM, and FSQRT Instructions FSCALE Instruction FPREM1 Instruction FPREM Instruction FUCOM, FUCOMP, and FUCOMPP Instructions FPTAN Instruction Stack Overflow FSIN, FCOS, and FSINCOS Instructions FPATAN Instruction F2XM1 Instruction FLD Instruction FXTRACT Instruction Load Constant Instructions FSETPM Instruction FXAM Instruction FSAVE and FSTENV Instructions Transcendental Instructions Obsolete Instructions WAIT/FWAIT Prefix Differences Operands Split Across Segments and/or Pages FPU Instruction Synchronization SERIALIZING INSTRUCTIONS FPU AND MATH COPROCESSOR INITIALIZATION Intel 387 and Intel 287 Math Coprocessor Initialization Intel486 SX Processor and Intel 487 SX Math Coprocessor Initialization CONTROL REGISTERS MEMORY MANAGEMENT FACILITIES New Memory Management Control Flags Physical Memory Addressing Extension Global Pages Larger Page Sizes