TOP TOPSwitch-HX Family

Transcription

1 TOP TOPwitchHX Family Enhanced Ecomart, Integrated OffLine witcher with Advanced Feature et and Extended Power Range Product Highlights Lower ystem ost, Higher esign Flexibility Multimode operation maximizes effi ciency at all loads New eip7 package builds on PI s experience with high power and high reliability packages Low thermal impedance junctiontocase (2 per watt) Low height is ideal for adapters where space is limited imple mounting using a clip to aid low cost manufacturing No heatsink required up to 35 W using P, G and M packages with universal input voltage and up to 48 W at 23 A Output overvoltage protection (OP) is user programmable for latching/nonlatching shutdown with fast A reset Allows both primary and secondary sensing Line undervoltage (U) detection prevents turnoff glitches Line overvoltage (O) shutdown extends line surge limit Accurate programmable current limit Optimized line feedforward for line ripple rejection 132 khz frequency (254Y258Y and all E packages) reduces transformer and power supply size Half frequency option for video applications Frequency jittering reduces EMI fi lter cost Heatsink is connected to OURE for low EMI Improved autorestart delivers <3% of maximum power in short circuit and open loop fault conditions Accurate hysteretic thermal shutdown function automatically recovers without requiring a reset Fully integrated softstart for minimum startup stress Extended creepage between RAIN and all other pins improves fi eld reliability Output Power Table Figure 1. Typical Flyback Application. Ecomart Energy Efficient Energy effi cient over entire load range Noload consumption Less than 2 mw at 265 A for TOP Less than 3 mw at 265 A for TOP tandby power for 1 W input >6 mw output at 11 A input >5 mw output at 265 A input escription PI TOPwitchHX cost effectively incorporates a 7 power MOFET, high voltage switched current source, PWM control, oscillator, thermal shutdown circuit, fault protection and other control circuitry onto a monolithic device. February 28 A IN TOPwitchHX ONTROL 23 A ±15% A 23 A ±15% A Product 5 Open Open Product Adapter 5 Open Open 1 Peak Frame 2 3 Adapter 1 Peak Frame 2 3 Adapter 1 Adapter Frame 2 1 Frame 2 TOP252PN/GN 21 W 13 W TOP252EN 1 W 21 W 6 W 13 W 9 W 15 W 6.5 W 1 W TOP252MN 21 W 13 W TOP253EN 21 W 43 W 13 W 29 W TOP253PN/GN 38 W 25 W 15 W 25 W 9 W 15 W TOP253MN 43 W 29 W TOP254EN/YN 3 W 62 W 2 W 43 W TOP254PN/GN 47 W 3 W TOP255EN/YN 4 W 81 W 26 W 57 W 16 W 28 W 11 W 2 W TOP254MN 62 W 4 W TOP256EN/YN 6 W 119 W 4 W 86 W TOP255PN/GN 54 W 35 W 19 W 3 W 13 W 22 W TOP255MN 81 W 52 W TOP257EN/YN 85 W 157 W 55 W 119 W TOP256PN/GN 63 W 4 W TOP258EN/YN 15 W 195 W 7 W 148 W 21 W 34 W 15 W 26 W TOP256MN 98 W 64 W TOP259EN/YN 128 W 238 W 8 W 171 W TOP257PN/GN 7 W 45 W 25 W 41 W 19 W 3 W TOP26EN/YN 147 W 275 W 93 W 2 W TOP257MN 119 W 78 W TOP258PN/GN 77 W 5 W TOP261EN/YN 177 W 333 W 118 W 254 W 29 W 48 W 22 W 35 W TOP258MN 14 W 92 W Table 1. Output Power Table. (for notes see page 2). X F OUT

2 TOP Notes: 1. Minimum continuous power in a typical nonventilated enclosed adapter measured at 5 ambient. Use of an external heat sink will increase power capability. 2. Minimum continuous power in an open frame design at 5 ambient. 3. Peak power capability in any design at 5 ambient A or 11/115 A with doubler. 5. Packages: P: IP8, G: M8, M: IP1, Y: TO227, E: eip7. ee part ordering information. Y Package Option for TOP In order to improve noiseimmunity on large TOPwitchHX Y package parts, the F pin has been removed (TOP259261YN are fi xed at 66 khz switching frequency) and replaced with a IGNAL GROUN (G) pin. This pin acts as a low noise path for the pin capacitor and the X pin resistor. It is only required for the TOP259261YN package parts. A IN OUT TOPwitchHX ONTROL X G PI Figure 2. Typical Flyback Application TOP259YN, TOP26YN and TOP261YN. 2

3 TOP ection List Functional Block iagram... 4 Pin Functional escription... 6 TOPwitchHX Family Functional escription... 7 ONTROL () Pin Operation... 8 Oscillator and witching Frequency... 8 Pulse Width Modulator... 9 Maximum Load ycle... 9 Error Amplifi er... 9 Onhip urrent Limit with External Programmability... 9 Line Under etection (U)... 1 Line Overvoltage hutdown (O) Hysteretic or Latching Output Overvoltage Protection (OP) Line FeedForward with MAX Reduction Remote ON/OFF and ynchronization ofttart hutdown/autorestart Hysteretic OverTemperature Protection Bandgap Reference High Bias urrent ource Typical Uses of FREQUENY (F) Pin Typical Uses of OLTAGE MONITOR () and EXTERNAL URRENT LIMIT (X) Pins Typical Uses of MULTIFUNTION (M) Pin Application Examples A High Effi ciency, 35 W, ual Output Universal Power upply A High Effi ciency, 15 W, 2538 Power upply A High Effi ciency, 2 W ontinuous 8 W Peak, Universal Power upply A High Effi ciency, 65 W, Universal Power upply Key Application onsiderations TOPwitchHX vs.topwitchgx TOPwitchHX esign onsiderations TOPwitchHX Layout onsiderations Quick esign hecklist esign Tools Product pecifications and Test onditions Typical Performance haracteristics Package Outlines Part Ordering Information

4 TOP ONTROL () Z INTERNAL UPPLY I FB INTERNAL U OMPARATOR K P(UPPER) K P(LOWER) HUTOWN/ AUTORETART URRENT LIMIT OMPARATOR 1 RAIN () HUNT REGULATOR/ ERROR AMPLIFIER OFT TART I (LIMIT) URRENT LIMIT AJUT ON/OFF 16 BG T MULTI FUNTION (M) OP LINE ENE O/ U MAX TOP LOGI MAX TOP OFT TART OILLATOR WITH JITTER MAX LOK HYTERETI THERMAL HUTOWN OURE () ONTROLLE TURNON GATE RIER F REUTION R Q LEAING EGE BLANKING F REUTION K P(UPPER) K P(LOWER) OFT TART I FB I P(UPPER) I P(LOWER) PWM OFF PI OURE () Figure 3a. Functional Block iagram (P and G Packages). ONTROL () Z 1 INTERNAL UPPLY RAIN () EXTERNAL URRENT LIMIT (X) OLTAGE MONITOR () HUNT REGULATOR/ ERROR AMPLIFIER I FB URRENT LIMIT AJUT BG T I (LIMIT) ON/OFF OP O/ U LINE ENE MAX TOP LOGI INTERNAL U OMPARATOR MAX TOP OFT TART OILLATOR WITH JITTER OFT TART MAX LOK 16 HUTOWN/ AUTORETART HYTERETI THERMAL HUTOWN K P(UPPER) K P(LOWER) URRENT LIMIT OMPARATOR OURE () ONTROLLE TURNON GATE RIER F REUTION R Q LEAING EGE BLANKING F REUTION K P(UPPER) K P(LOWER) OFT TART I FB I P(UPPER) I P(LOWER) PWM OFF PI OURE () Figure 3b. Functional Block iagram (M Package). 4

5 TOP ONTROL () Z 1 INTERNAL UPPLY RAIN () EXTERNAL URRENT LIMIT (X) OLTAGE MONITOR () FREQUENY (F) HUNT REGULATOR/ ERROR AMPLIFIER I FB URRENT LIMIT AJUT BG T I (LIMIT) ON/OFF OP O/ U LINE ENE MAX K P(UPPER) K P(LOWER) TOP LOGI INTERNAL U OMPARATOR MAX TOP OFT TART 66k/132k F REUTION OFT TART I FB I P(UPPER) I P(LOWER) OILLATOR WITH JITTER F REUTION PWM OFT TART MAX LOK OFF 16 HUTOWN/ AUTORETART HYTERETI THERMAL HUTOWN R Q K P(UPPER) K P(LOWER) URRENT LIMIT OMPARATOR OURE () ONTROLLE TURNON GATE RIER LEAING EGE BLANKING PI OURE () Figure 3c. Functional Block iagram (TOP Y Package and eip Package). ONTROL () Z 1 INTERNAL UPPLY RAIN () EXTERNAL URRENT LIMIT (X) OLTAGE MONITOR () HUNT REGULATOR/ ERROR AMPLIFIER I FB URRENT LIMIT AJUT BG T I (LIMIT) ON/OFF OP O/ U LINE ENE MAX TOP LOGI INTERNAL U OMPARATOR MAX TOP OFT TART OILLATOR WITH JITTER OFT TART MAX LOK 16 HUTOWN/ AUTORETART HYTERETI THERMAL HUTOWN K P(UPPER) K P(LOWER) URRENT LIMIT OMPARATOR OURE () ONTROLLE TURNON GATE RIER F REUTION R Q LEAING EGE BLANKING OURE () F REUTION K P(UPPER) K P(LOWER) OFT TART I FB I P(UPPER) I P(LOWER) PWM OFF PI IGNAL GROUN (G) Figure 3d. Functional Block iagram TOP259YN, TOP26YN, TOP261YN. 5

6 TOP Pin Functional escription RAIN () Pin: Highvoltage power MOFET RAIN pin. The internal startup bias current is drawn from this pin through a switched highvoltage current source. Internal current limit sense point for drain current. ONTROL () Pin: Error amplifi er and feedback current input pin for duty cycle control. Internal shunt regulator connection to provide internal bias current during normal operation. It is also used as the connection point for the supply bypass and autorestart/ compensation capacitor. EXTERNAL URRENT LIMIT (X) Pin (Y, M and E package): pin for external current limit adjustment and remote ON/OFF. A connection to OURE pin disables all functions on this pin. OLTAGE MONITOR () Pin (Y & M package only): for O, U, line feed forward with MAX reduction, output overvoltage protection (OP), remote ON/OFF and device reset. A connection to the OURE pin disables all functions on this pin. MULTIFUNTION (M) Pin (P & G packages only): This pin combines the functions of the OLTAGE MONITOR () and EXTERNAL URRENT LIMIT (X) pins of the Y package into one pin. pin for O, U, line feed forward with MAX reduction, output overvoltage protection (OP), external current limit adjustment, remote ON/OFF and device reset. A connection to OURE pin disables all functions on this pin and makes TOPwitchHX operate in simple three terminal mode (like TOPwitchII). R L ONTROL X 4 M R IL 12 k U = I U R L (I = I U ) O =I O R L (I = I O ) For R L =4M U = 12.8 O = 451 = 76% = 41% For R IL = 12 k I LIMIT = 61% ee Figure 55b for other resistor values (R IL ) to select different I LIMIT values. PI E Package (eip7) Y Package (TO227) Figure 5. TOP Y and All M/E Package Line ense and Externally et urrent Limit. M M Package 1 1 X P and G Package XF Tab (Hidden) Internally onnected to OURE Pin Tab Internally onnected to OURE Pin Tab Internally onnected to OURE Pin X G Y Package X F Note: Y package for TOP Note: Y package for TOP PI Figure 6. R L ONTROL R L X R IL 12 k 4 M M 4 M G ONTROL U = I U R L (I = I U ) O =I O R L (I = I O ) For R L =4M U = 12.8 O = 451 = 76% = 41% U = I U R L M (I M = I U ) O =I O R L M (I M = I O ) For R L = 4 M U = 12.8 O = 451 = 76% = 41% For R IL = 12 k I LIMIT = 61% ee Figure 55b for other resistor values (R IL ) to select different I LIMIT values. TOP Y Package Line ense and External urrent Limit. PI PI Figure 4. Pin onfi guration (Top iew). Figure 7. P/G Package Line ense. 6

7 TOP Figure 8. R IL M ONTROL P/G Package Externally et urrent Limit. For R IL = 12 k I LIMIT = 61% For R IL = 19 k I LIMIT = 37% ee Figure 55b for other resistor values (R IL ) to select different I LIMIT values. PI FREQUENY (F) Pin (TOP Y package & E packages): pin for selecting switching frequency 132 khz if connected to OURE pin and 66 khz if connected to ONTROL pin. The switching frequency is internally set for fi xed 66 khz operation in the P, G, M package and TOP259YN, TOP26YN and TOP261YN. IGNAL GROUN (G) Pin (TOP259YN, TOP26YN & TOP261YN only): Return for pin capacitor and X pin resistor. OURE () Pin: Output MOFET source connection for high voltage power return. Primary side control circuit common and reference point. TOPwitchHX Family Functional escription Like TOPwitchGX, TOPwitchHX is an integrated switched mode power supply chip that converts a current at the control input to a duty cycle at the open drain output of a high voltage power MOFET. uring normal operation the duty cycle of the power MOFET decreases linearly with increasing ONTROL pin current as shown in Figure 9. In addition to the three terminal TOPwitch features, such as the high voltage startup, the cyclebycycle current limiting, loop compensation circuitry, autorestart and thermal shutdown, the TOPwitchHX incorporates many additional functions that reduce system cost, increase power supply performance and design fl exibility. A patented high voltage MO technology allows both the highvoltage power MOFET and all the low voltage control circuitry to be cost effectively integrated onto a single monolithic chip. Three terminals, FREQUENY, OLTAGEMONITOR, and EXTERNAL URRENT LIMIT (available in Y and E packages), two terminals, OLTAGEMONITOR and EXTERNAL URRENT LIMIT (available in M package) or one terminal MULTI FUNTION (available in P and G package) have been used to implement some of the new functions. These terminals can be connected to the OURE pin to operate the TOPwitchHX in a TOPwitchlike three terminal mode. However, even in this three terminal mode, the TOPwitchHX offers many transparent features that do not require any external components: uty ycle (%) rain Peak urrent To urrent Limit Ratio (%) Frequency (khz) Figure AutoRestart Full Frequency Mode I 1 I B Jitter I 1 lope = PWM Gain (constant over load range) ariable Frequency Mode ontrol Pin haracteristics (MultiMode Operation). ONTROL urrent ONTROL urrent I ONTROL 3 I OFF urrent PI A fully integrated 17 ms softstart signifi cantly reduces or eliminates output overshoot in most applications by sweeping both current limit and frequency from low to high to limit the peak currents and voltages during startup. A maximum duty cycle ( MAX ) of 78% allows smaller input storage capacitor, lower input voltage requirement and/or higher power capability. Multimode operation optimizes and improves the power supply effi ciency over the entire load range while maintaining good cross regulation in multioutput supplies. witching frequency of 132 khz reduces the transformer size with no noticeable impact on EMI. Frequency jittering reduces EMI in the full frequency mode at high load condition. I 2 Low Frequency Mode Multiycle Modulation 7

8 TOP Hysteretic overtemperature shutdown ensures automatic recovery from thermal fault. Large hysteresis prevents circuit board overheating. Packages with omitted pins and lead forming provide large drain creepage distance. Reduction of the autorestart duty cycle and frequency to improve the protection of the power supply and load during open loop fault, short circuit, or loss of regulation. Tighter tolerances on I 2 f power coeffi cient, current limit reduction, PWM gain and thermal shutdown threshold. The OLTAGEMONITOR () pin is usually used for line sensing by connecting a 4 MΩ resistor from this pin to the rectifi ed high voltage bus to implement line overvoltage (O), undervoltage (U) and dualslope line feedforward with MAX reduction. In this mode, the value of the resistor determines the O/U thresholds and the MAX is reduced linearly with a dual slope to improve line ripple rejection. In addition, it also provides another threshold to implement the latched and hysteretic output overvoltage protection (OP). The pin can also be used as a remote ON/OFF using the I U threshold. The EXTERNAL URRENT LIMIT (X) pin can be used to reduce the current limit externally to a value close to the operating peak current, by connecting the pin to OURE through a resistor. This pin can also be used as a remote ON/OFF input. For the P and G package the OLTAGEMONITOR and EXTERNAL URRENT LIMIT pin functions are combined on one MULTIFUNTION (M) pin. However, some of the functions become mutually exclusive. The FREQUENY (F) pin in the TOP Y and E packages set the switching frequency in the full frequency PWM mode to the default value of 132 khz when connected to OURE pin. A half frequency option of 66 khz can be chosen by connecting this pin to the ONTROL pin instead. Leaving this pin open is not recommended. In the P, G and M packages and the TOP Y packages, the frequency is set internally at 66 khz in the full frequency PWM mode. ONTROL () Pin Operation The ONTROL pin is a low impedance node that is capable of receiving a combined supply and feedback current. uring normal operation, a shunt regulator is used to separate the feedback signal from the supply current. ONTROL pin voltage is the supply voltage for the control circuitry including the MOFET gate driver. An external bypass capacitor closely connected between the ONTROL and OURE pins is required to supply the instantaneous gate drive current. The total amount of capacitance connected to this pin also sets the autorestart timing as well as control loop compensation. When rectifi ed high voltage is applied to the RAIN pin during startup, the MOFET is initially off, and the ONTROL pin capacitor is charged through a switched high voltage current source connected internally between the RAIN and ONTROL pins. When the ONTROL pin voltage reaches approximately 5.8, the control circuitry is activated and the softstart begins. The softstart circuit gradually increases the drain peak current and switching frequency from a low starting value to the maximum drain peak current at the full frequency over approximately 17 ms. If no external feedback/supply current is fed into the ONTROL pin by the end of the softstart, the high voltage current source is turned off and the ONTROL pin will start discharging in response to the supply current drawn by the control circuitry. If the power supply is designed properly, and no fault condition such as open loop or shorted output exists, the feedback loop will close, providing external ONTROL pin current, before the ONTROL pin voltage has had a chance to discharge to the lower threshold voltage of approximately 4.8 (internal supply undervoltage lockout threshold). When the externally fed current charges the ONTROL pin to the shunt regulator voltage of 5.8, current in excess of the consumption of the chip is shunted to OURE through an NMO current mirror as shown in Figure 3. The output current of that NMO current mirror controls the duty cycle of the power MOFET to provide closed loop regulation. The shunt regulator has a fi nite low output impedance Z that sets the gain of the error amplifi er when used in a primary feedback confi guration. The dynamic impedance Z of the ONTROL pin together with the external ONTROL pin capacitance sets the dominant pole for the control loop. When a fault condition such as an open loop or shorted output prevents the fl ow of an external current into the ONTROL pin, the capacitor on the ONTROL pin discharges towards 4.8. At 4.8, autorestart is activated, which turns the output MOFET off and puts the control circuitry in a low current standby mode. The highvoltage current source turns on and charges the external capacitance again. A hysteretic internal supply undervoltage comparator keeps within a window of typically 4.8 to 5.8 by turning the highvoltage current source on and off as shown in Figure 11. The autorestart circuit has a dividebysixteen counter, which prevents the output MOFET from turning on again until sixteen discharge/ charge cycles have elapsed. This is accomplished by enabling the output MOFET only when the dividebysixteen counter reaches the full count (15). The counter effectively limits TOPwitchHX power dissipation by reducing the autorestart duty cycle to typically 2%. Autorestart mode continues until output voltage regulation is again achieved through closure of the feedback loop. Oscillator and witching Frequency The internal oscillator linearly charges and discharges an internal capacitance between two voltage levels to create a triangular waveform for the timing of the pulse width modulator. This oscillator sets the pulse width modulator/current limit latch at the beginning of each cycle. The nominal full switching frequency of 132 khz was chosen to minimize transformer size while keeping the fundamental EMI frequency below 15 khz. The FREQUENY pin (available only in TOP Y and E packages), when shorted to the ONTROL pin, lowers the full switching frequency to 66 khz (half frequency), which may be preferable in some cases such as noise sensitive video applications or a high effi ciency standby mode. Otherwise, the FREQUENY pin should be connected to the OURE pin for the default 132 khz. In the M, P and G 8

9 TOP witching Frequency RAIN f O f O 4 ms Figure 1. witching Frequency Jitter (Idealized RAIN Waveforms). Time packages and the TOP Y package option, the full frequency PWM mode is set at 66 khz, for higher effi ciency and increased output power in all applications. To further reduce the EMI level, the switching frequency in the full frequency PWM mode is jittered (frequency modulated) by approximately ±2.5 khz for 66 khz operation or ±5 khz for 132 khz operation at a 25 Hz (typical) rate as shown in Figure 1. The jitter is turned off gradually as the system is entering the variable frequency mode with a fi xed peak drain current. Pulse Width Modulator The pulse width modulator implements multimode control by driving the output MOFET with a duty cycle inversely proportional to the current into the ONTROL pin that is in excess of the internal supply current of the chip (see Figure 9). The feedback error signal, in the form of the excess current, is fi ltered by an R network with a typical corner frequency of 7 khz to reduce the effect of switching noise in the chip supply current generated by the MOFET gate driver. To optimize power supply effi ciency, four different control modes are implemented. At maximum load, the modulator operates in full frequency PWM mode; as load decreases, the modulator automatically transitions, fi rst to variable frequency PWM mode, then to low frequency PWM mode. At light load, the control operation switches from PWM control to multicyclemodulation control, and the modulator operates in multicyclemodulation mode. Although different modes operate differently to make transitions between modes smooth, the simple relationship between duty cycle and excess ONTROL pin current shown in Figure 9 is maintained through all three PWM modes. Please see the following sections for the details of the operation of each mode and the transitions between modes. PI Full Frequency PWM mode: The PWM modulator enters full frequency PWM mode when the ONTROL pin current (I ) reaches I B. In this mode, the average switching frequency is kept constant at f O (66 khz for P, G and M packages and TOP Y, pin selectable 132 khz or 66 khz for Y and E packages). uty cycle is reduced from MAX through the reduction of the ontime when I is increased beyond I B. This operation is identical to the PWM control of all other TOPwitch families. TOPwitchHX only operates in this mode if the cyclebycycle peak drain current stays above k P(UPPER) *I LIMIT (set), where k P(UPPER) is 55% (typical) and I LIMIT (set) is the current limit externally set via the X or M pin. ariable Frequency PWM mode: When peak drain current is lowered to k P(UPPER) * I LIMIT (set) as a result of power supply load reduction, the PWM modulator initiates the transition to variable frequency PWM mode, and gradually turns off frequency jitter. In this mode, peak drain current is held constant at k P(UPPER) * I LIMIT (set) while switching frequency drops from the initial full frequency of f O (132 khz or 66 khz) towards the minimum frequency of f MM(MIN) (3 khz typical). uty cycle reduction is accomplished by extending the offtime. Low Frequency PWM mode: When switching frequency reaches f MM(MIN) (3 khz typical), the PWM modulator starts to transition to low frequency mode. In this mode, switching frequency is held constant at f MM(MIN) and duty cycle is reduced, similar to the full frequency PWM mode, through the reduction of the ontime. Peak drain current decreases from the initial value of k P(UPPER) * I LIMIT (set) towards the minimum value of k P(LOWER) *I LIMIT (set), where k P(LOWER) is 25% (typical) and I LIMIT (set) is the current limit externally set via the X or M pin. MultiycleModulation mode: When peak drain current is lowered to k P(LOWER) *I LIMIT (set), the modulator transitions to multicyclemodulation mode. In this mode, at each turnon, the modulator enables output switching for a period of T MM(MIN) at the switching frequency of f MM(MIN) (4 or 5 consecutive pulses at 3 khz) with the peak drain current of k P(LOWER) *I LIMIT (set), and stays off until the ONTROL pin current falls below I (OFF). This mode of operation not only keeps peak drain current low but also minimizes harmonic frequencies between 6 khz and 3 khz. By avoiding transformer resonant frequency this way, all potential transformer audible noises are greatly supressed. Maximum uty ycle The maximum duty cycle, MAX, is set at a default maximum value of 78% (typical). However, by connecting the OLTAGE MONITOR or MULTIFUNTION pin (depending on the package) to the rectifi ed high voltage bus through a resistor with appropriate value (4 MΩ typical), the maximum duty cycle can be made to decrease from 78% to 4% (typical) when input line voltage increases from 88 to 38, with dual gain slopes. Error Amplifier The shunt regulator can also perform the function of an error amplifi er in primary side feedback applications. The shunt regulator voltage is accurately derived from a temperaturecompensated bandgap reference. The ONTROL pin dynamic impedance Z sets the gain of the error amplifi er. The ONTROL pin clamps external circuit signals to the voltage level. The ONTROL pin current in excess of the supply current is separated by the shunt regulator and becomes the feedback current I fb for the pulse width modulator. Onhip urrent Limit with External Programmability The cyclebycycle peak drain current limit circuit uses the output MOFET ONresistance as a sense resistor. A current limit comparator compares the output MOFET onstate drain 9

10 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ TOP LINE RAIN OUT U Note: through 15 are the output states of the autorestart counter PI Figure 11. Typical Waveforms for (1) Power Up (2) Normal Operation (3) AutoRestart (4) Power own. to source voltage (ON) with a threshold voltage. High drain current causes (ON) to exceed the threshold voltage and turns the output MOFET off until the start of the next clock cycle. The current limit comparator threshold voltage is temperature compensated to minimize the variation of the current limit due to temperature related changes in R (ON) of the output MOFET. The default current limit of TOPwitchHX is preset internally. However, with a resistor connected between EXTERNAL URRENT LIMIT (X) pin (Y, E and M packages) or MULTI FUNTION (M) pin (P and G package) and OURE pin (for TOP Y, the X pin is connected to the IGNAL GROUN (G) pin), current limit can be programmed externally to a lower level between 3% and 1% of the default current limit. By setting current limit low, a larger TOPwitchHX than necessary for the power required can be used to take advantage of the lower R (ON) for higher effi ciency/smaller heat sinking requirements. TOPwitchHX current limit reduction initial tolerance through the X pin (or M pin) has been improved signifi cantly compare with previous TOPwitchGX. With a second resistor connected between the EXTERNAL URRENT LIMIT (X) pin (Y, E and M packages) or MULTIFUNTION (M) pin (P and G package) and the rectifi ed high voltage bus, the current limit is reduced with increasing line voltage, allowing a true power limiting operation against line variation to be implemented. When using an R clamp, this power limiting technique reduces maximum clamp voltage at high line. This allows for higher refl ected voltage designs as well as reducing clamp dissipation. The leading edge blanking circuit inhibits the current limit comparator for a short time after the output MOFET is turned on. The leading edge blanking time has been set so that, if a power supply is designed properly, current spikes caused by primaryside capacitances and secondaryside rectifi er reverse recovery time should not cause premature termination of the switching pulse. The current limit is lower for a short period after the leading edge blanking time. This is due to dynamic characteristics of the MOFET. uring startup and fault conditions the controller prevents excessive drain currents by reducing the switching frequency. Line Undervoltage etection (U) At power up, U keeps TOPwitchHX off until the input line voltage reaches the undervoltage threshold. At power down, U prevents autorestart attempts after the output goes out of regulation. This eliminates power down glitches caused by slow discharge of the large input storage capacitor present in applications such as standby supplies. A single resistor connected from the OLTAGEMONITOR pin (Y, E and M packages) or MULTIFUNTION pin (P and G packages) to the rectifi ed high voltage bus sets U threshold during power up. Once the power supply is successfully turned on, the U threshold is lowered to 44% of the initial U threshold to allow extended input voltage operating range (U low threshold). If the U low threshold is reached during operation without the power supply losing regulation, the device will turn off and stay off until U (high threshold) has been reached again. If the power supply loses regulation before reaching the U low threshold, the device will enter autorestart. At the end of each autorestart cycle (15), the U comparator is enabled. If the U high threshold is not exceeded, the MOFET will be disabled during the next cycle (see Figure 11). The U feature can be disabled independent of the O feature. Line Overvoltage hutdown (O) The same resistor used for U also sets an overvoltage 1

11 TOP threshold, which, once exceeded, will force TOPwitchHX to stop switching instantaneously (after completion of the current switching cycle). If this condition lasts for at least 1 μs, the TOPwitchHX output will be forced into off state. Unlike with TOPwitchGX, however, when the line voltage is back to normal with a small amount of hysteresis provided on the O threshold to prevent noise triggering, the state machine sets to 13 and forces TOPwitchHX to go through the entire autorestart sequence before attempting to switch again. The ratio of O and U thresholds is preset at 4.5, as can be seen in Figure 12. When the MOFET is off, the rectifi ed high voltage surge capability is increased to the voltage rating of the MOFET (7 ), due to the absence of the refl ected voltage and leakage spikes on the drain. The O feature can be disabled independent of the U feature. In order to reduce the noload input power of TOPwitchHX designs, the pin (or Mpin for P Package) operates at very low currents. This requires careful layout considerations when designing the PB to avoid noise coupling. Traces and components connected to the pin should not be adjacent to any traces carrying switching currents. These include the drain, clamp network, bias winding return or power traces from other converters. If the line sensing features are used, then the sense resistors must be placed within 1 mm of the pin to minimize the pin node area. The bus should then be routed to the line sense resistors. Note that external capacitance must not be connected to the pin as this may cause misoperaton of the pin related functions. Hysteretic or Latching Output Overvoltage Protection (OP) The detection of the hysteretic or latching output overvoltage protection (OP) is through the trigger of the line overvoltage threshold. The pin or Mpin voltage will drop by.5, and the controller measures the external attached impedance immediately after this voltage drops. If I or I M exceeds I O(L) (336 μa typical) longer than 1 μs, TOPwitchHX will latch into a permanent off state for the latching OP. It only can be reset if or M goes below 1 or goes below the powerupreset threshold ( (REET) ) and then back to normal. If I or I M does not exceed I O(L) or exceeds no longer than 1 μs, TOPwitchHX will initiate the line overvoltage and the hysteretic OP. Their behavior will be identical to the line overvoltage shutdown (O) that has been described in detail in the previous section. Monitor and External urrent Limit Pin Table* Figure Number Three Terminal Operation Line Undervoltage Line Overvoltage Line FeedForward ( MAX ) Output Overvoltage Protection Overload Power Limiting External urrent Limit Remote ON/OFF evice Reset *This table is only a partial list of many OLTAGE MONITOR and EXTERNAL URRENT LIMIT Pin onfi gurations that are possible. Table 2. OLTAGE MONITOR () Pin and EXTERNAL URRENT LIMIT (X) Pin onfi guration Options. MultiFunction Pin Table* Figure Number Three Terminal Operation Line Undervoltage Line Overvoltage Line FeedForward ( MAX ) Output Overvoltage Protection Overload Power Limiting External urrent Limit Remote ON/OFF evice Reset *This table is only a partial list of many MULTIFUNTIONAL Pin onfi gurations that are possible. Table 3. MULTIFUNTION (M) Pin onfi guration Options. 11

12 TOP M Pin X Pin Pin Output MOFET witching (Enabled) (isabled) I REM(N) I U I O I O(L) (NonLatching) (Latching) I LIMIT (efault) isabled when supply output goes out of regulation I urrent Limit I MAX (78%) Maximum uty ycle I Pin BG I X and Pins (Y, E and M Packages) and M Pin (P and G Packages) urrent (μa) Note: This figure provides idealized functional characteristics with typical performance values. Please refer to the parametric table and typical performance characteristics sections of the data sheet for measured data. For a detailed description of each functional pin operation refer to the Functional escription section of the data sheet. PI Figure 12. MULTIFUNTION (P and G package). OLTAGE MONITOR and EXTERNAL URRENT LIMIT (Y, E and M package) Pin haracteristics. The circuit examples shown in Figures 41, 42 and 43 show a simple method for implementing the primary sensed overvoltage protection. uring a fault condition resulting from loss of feedback, output voltage will rapidly rise above the nominal voltage. The increase in output voltage will also result in an increase in the voltage at the output of the bias winding. A voltage at the output of the bias winding that exceeds of the sum of the voltage rating of the Zener diode connected from the bias winding output to the pin (or Mpin) and pin (or Mpin) voltage, will cause a current in excess of I or I M to be injected into the pin (or Mpin), which will trigger the OP feature. The primary sensed OP protection circuit shown in Figures 41, 42 and 43 is triggered by a signifi cant rise in output voltage (and therefore bias winding voltage). If the power supply is operating under heavy load or low input line conditions when an open loop occurs, the output voltage may not rise signifi cantly. Under these conditions, a latching shutdown will not occur until load or line conditions change. Nevertheless, the operation provides the desired protection by preventing signifi cant rise in the output voltage when the line or load conditions do change. Primary side OP protection with the TOPwitchHX in a typical application will prevent a nominal 12 output from rising above approximately 2 under open loop conditions. If greater accuracy is required, a secondary sensed OP circuit is recommended. 12

13 TOP Line FeedForward with MAX Reduction The same resistor used for U and O also implements line voltage feedforward, which minimizes output line ripple and reduces power supply output sensitivity to line transients. Note that for the same ONTROL pin current, higher line voltage results in smaller operating duty cycle. As an added feature, the maximum duty cycle MAX is also reduced from 78% (typical) at a voltage slightly lower than the U threshold to 36% (typical) at the O threshold. MAX of 36% at high line was chosen to ensure that the power capability of the TOPwitchHX is not restricted by this feature under normal operation. TOPwitchHX provides a better fi t to the ideal feedforward by using two reduction slopes: 1% per μa for all bus voltage less than 195 (typical for 4 MΩ line impedance) and.25% per μa for all bus voltage more than 195. This dual slope line feedforward improves the line ripple rejection signifi cantly compared with the TOPwitchGX. Remote ON/OFF TOPwitchHX can be turned on or off by controlling the current into the OLTAGEMONITOR pin or out from the EXTERNAL URRENT LIMIT pin (Y, E and M packages) and into or out from the MULTIFUNTION pin (P and G package, see Figure 12). In addition, the OLTAGEMONITOR pin has a 1 threshold comparator connected at its input. This voltage threshold can also be used to perform remote ON/OFF control. When a signal is received at the OLTAGEMONITOR pin or the EXTERNAL URRENT LIMIT pin (Y, E and M packages) or the MULTIFUNTION pin (P and G package) to disable the output through any of the pin functions such as O, U and remote ON/OFF, TOPwitchHX always completes its current switching cycle before the output is forced off. As seen above, the remote ON/OFF feature can also be used as a standby or power switch to turn off the TOPwitchHX and keep it in a very low power consumption state for indefi nitely long periods. If the TOPwitchHX is held in remote off state for long enough time to allow the ONTROL pin to discharge to the internal supply undervoltage threshold of 4.8 (approximately 32 ms for a 47 μf ONTROL pin capacitance), the ONTROL pin goes into the hysteretic mode of regulation. In this mode, the ONTROL pin goes through alternate charge and discharge cycles between 4.8 and 5.8 (see ONTROL pin operation section above) and runs entirely off the high voltage input, but with very low power consumption (16 mw typical at 23 A with M or X pins open). When the TOPwitchHX is remotely turned on after entering this mode, it will initiate a normal startup sequence with softstart the next time the ONTROL pin reaches 5.8. In the worst case, the delay from remote on to startup can be equal to the full discharge/charge cycle time of the ONTROL pin, which is approximately 125 ms for a 47 μf ONTROL pin capacitor. This reduced consumption remote off mode can eliminate expensive and unreliable inline mechanical switches. It also allows for microprocessor controlled turnon and turnoff sequences that may be required in certain applications such as inkjet and laser printers. ofttart The 17 ms softstart sweeps the peak drain current and switching frequency linearly from minimum to maximum value by operating through the low frequency PWM mode and the variable frequency mode before entering the full frequency mode. In addition to startup, softstart is also activated at each restart attempt during autorestart and when restarting after being in hysteretic regulation of ONTROL pin voltage ( ), due to remote OFF or thermal shutdown conditions. This effectively minimizes current and voltage stresses on the output MOFET, the clamp circuit and the output rectifi er during startup. This feature also helps minimize output overshoot and prevents saturation of the transformer during startup. hutdown/autorestart To minimize TOPwitchHX power dissipation under fault conditions, the shutdown/autorestart circuit turns the power supply on and off at an autorestart duty cycle of typically 2% if an out of regulation condition persists. Loss of regulation interrupts the external current into the ONTROL pin. regulation changes from shunt mode to the hysteretic autorestart mode as described in ONTROL pin operation section. When the fault condition is removed, the power supply output becomes regulated, regulation returns to shunt mode, and normal operation of the power supply resumes. Hysteretic OverTemperature Protection Temperature protection is provided by a precision analog circuit that turns the output MOFET off when the junction temperature exceeds the thermal shutdown temperature (142 typical). When the junction temperature cools to below the lower hysteretic temperature point, normal operation resumes, thus providing automatic recovery. A large hysteresis of 75 (typical) is provided to prevent overheating of the P board due to a continuous fault condition. is regulated in hysteretic mode, and a 4.8 to 5.8 (typical) triangular waveform is present on the ONTROL pin while in thermal shutdown. Bandgap Reference All critical TOPwitchHX internal voltages are derived from a temperaturecompensated bandgap reference. This voltage reference is used to generate all other internal current references, which are trimmed to accurately set the switching frequency, MOFET gate drive current, current limit, and the line O/U/OP thresholds. TOPwitchHX has improved circuitry to maintain all of the above critical parameters within very tight absolute and temperature tolerances. High Bias urrent ource This highvoltage current source biases TOPwitchHX from the RAIN pin and charges the ONTROL pin external capacitance during startup or hysteretic operation. Hysteretic operation occurs during autorestart, remote OFF and overtemperature shutdown. In this mode of operation, the current source is switched on and off, with an effective duty cycle of approximately 35%. This duty cycle is determined by the ratio of ONTROL pin charge (I ) and discharge currents (I 1 and I 2 ). This current source is turned off during normal operation when the output MOFET is switching. The effect of the current source switching will be seen on the RAIN voltage waveform as small disturbances and is normal. 13

14 TOP ONTROL () Y, E and M Package 2 A TOPwitchHX EXTERNAL URRENT LIMIT (X) BG T (Negative urrent ense ON/OFF, urrent Limit Adjustment) OLTAGE MONITOR () REF 1 ( ense) (Positive urrent ense Undervoltage, Overvoltage, ON/OFF, Maximum uty ycle Reduction, Output Overvoltage Protection) 4 A PI Figure 13a. OLTAGE MONITOR () and EXTERNAL URRENT LIMIT (X) Pin implifi ed chematic. ONTROL () P and G Package 2 A TOPwitchHX MULTIFUNTION (M) BG T (Negative urrent ense ON/OFF, urrent Limit Adjustment) REF (Positive urrent ense Undervoltage, Overvoltage, Maximum uty ycle Reduction, Output Overvoltage Protection) 4 A PI Figure 13b. MULTIFUNTION (M) Pin implifi ed chematic. 14

15 TOP Typical Uses of FREQUENY (F) Pin ONTROL ONTROL F F PI PI Figure 14. Full Frequency Operation (132 khz). Figure 15. Half Frequency Operation (66 khz). 15

16 TOP Typical Uses of OLTAGE MONITOR () and EXTERNAL URRENT LIMIT (X) Pins TOP252258M TOP254258Y TOP259261Y X X F XG ONTROL ONTROL X F X G PI PI Figure 16a. Three Terminal Operation (OLTAGE MONITOR and EXTERNAL URRENT LIMIT Features isabled. FREQUENY Pin Tied to OURE or ONTROL Pin) for TOP Y Packages. Figure 16b. Three Terminal Operation (OLTAGE MONITOR and EXTERNAL URRENT LIMIT Features isabled for TOP Y Packages. eip U = I U R L (I = I U ) O =I O R L (I = I O ) X F R L 4 M For R L = 4 M U = 12.8 O = 451 = 76% = 41% ONTROL ONTROL X F PI PI Figure 16c. Three Terminal Operation (OLTAGE MONITOR and EXTERNAL URRENT LIMIT Features isabled. FREQUENY Pin Tied to OURE or ONTROL Pin) for TOP E Packages. Figure 17. Lineensing for Undervoltage, Overvoltage and Line FeedForward. R L 4 M U = I U R L (I = I U ) O =I O R L (I = I O ) For R L = 4 M U = 12.8 O = 451 ense Output 1 = 76% 375 = 41% R L U = I U R L (I = I U ) O =I O R L (I = I O ) For R L = 4 M U = 12.8 O = 451 ense Output 4 M R R OP OP 1 = 76% 375 = 41% Reset 1 k Q R ONTROL ONTROL R OP >3k PI PI Figure 18. Lineensing for Undervoltage, Overvoltage, Line FeedForward and Latched Output Overvoltage Protection. Figure 19. Lineensing for Undervoltage, Overvoltage, Line FeedForward and Hysteretic Output Overvoltage Protection. 16

17 TOP Typical Uses of OLTAGE MONITOR () and EXTERNAL URRENT LIMIT (X) Pins (cont.) 4 M U = R L I U (I = I U ) For alues hown U = 13.8 R L R L O = I O R L (I = I O ) 4 M For alues hown O = k ONTROL 55 k ONTROL 1N4148 PI PI Figure 2. Line ensing for Undervoltage Only (Overvoltage isabled). Figure 21. Lineensing for Overvoltage Only (Undervoltage isabled). Maximum uty ycle Reduced at Low Line and Further Reduction with Increasing Line. ONTROL For R IL = 12 k I LIMIT = 61% For R IL = 19 k I LIMIT = 37% ee Figure 55b for other resistor values (R IL ). R L 2.5 M ONTROL I LIMIT = 1 I LIMIT = 3 TOP259261YN would use the G pin as the return for R IL. X R IL TOP259261YN would use the G pin as the return for R IL. X R IL 6 k PI PI Figure 22. External et urrent Limit. Figure 23. urrent Limit Reduction with Line. Q R can be an optocoupler output or can be replaced by a manual switch. Q R can be an optocoupler output or can be replaced by a manual switch. ONTROL TOP259261YN would use the G pin as the return for Q R. ONTROL For R IL = 12 k I LIMIT = 61% For R IL = 19 k I LIMIT = 37% Q R X 47 K ON/OFF X R IL Q R TOP259261YN would use the G pin as the return for Q R. ON/OFF 16 k PI PI Figure 24. Activeon (Fail afe) Remote ON/OFF. Figure 25. Activeon Remote ON/OFF with Externally et urrent Limit. 17

18 TOP Typical Uses of OLTAGE MONITOR () and EXTERNAL URRENT LIMIT (X) Pins (cont.) TOP259261YN would use the G pin as the return for Q R. R L X 4 M ONTROL R IL U = I U R L (I = I U ) O =I O R L (I = I o ) = 76% = 41% Q R Q R can be an optocoupler output or can be replaced by a manual switch. 16 k For R IL = 12 k I LIMIT = 61% ON/OFF PI TOP259261YN would use the G pin as the return for R IL. R L X 4 M ONTROL R IL 12 k U = I U x R L (I = I U ) O =I O xr L (I = I o ) For R L =4M U = 12.8 O = = 76% 375 = 41% For R IL = 12 k I LIMIT = 61% ee Figure 55b for other resistor values (R IL ) to select different I LIMIT values. PI Figure 26. Activeon Remote ON/OFF with Lineense and External urrent Limit. Figure 27. Line ensing and Externally et urrent Limit. U = I U R L (I = I U ) O =I O R L (I = I O ) R L 4 M For R L = 4 M U = 12.8 O = 451 ense Output 1 = 76% 375 = 41% Reset 1 k Q R ONTROL PI Figure 28. Lineensing for Undervoltage, Overvoltage, Line FeedForward and Latched Output Overvoltage Protection with evice Reset. Typical Uses of MULTIFUNTION (M) Pin U = I U R L M (I M = I U ) O =I O R L M (I M = I O ) M ONTROL M R L 4 M M ONTROL For R L = 4 M U = 12.8 O = = 76% 375 = 41% PI PI Figure 29. Three Terminal Operation (MULTIFUNTION Features isabled). Figure 3. Line ensing for Undervoltage, Overvoltage and Line FeedForward. 18

19 TOP Typical Uses of MULTIFUNTION (M) Pin (cont.) R L 4 M M ONTROL U = I U R L M (I M = I U ) O =I O R L M (I M = I O ) For R L = 4 M U = 12.8 O = 451 ense Output 1 = 76% 375 = 41% R L For R L = 4 M U = 12.8 O = 451 ense Output 4 M R R OP OP M ONTROL U = I U R L M (I M = I U ) O =I O R L M (I M = I O ) 1 = 76% 375 = 41% R OP >3k PI PI Figure 31. Line ensing for Undervoltage, Overvoltage, Line FeedForward and Latched Output Overvoltage Protection. Figure 32. Line ensing for Undervoltage, Overvoltage, Line FeedForward and Hysteretic Output Overvoltage Protection. U = R L I U M (I M = I U ) O = I O R L M (I M = I O ) 4 M For alues hown U = M For alues hown O = R L R L 4 k 55 k 1N4148 M M 6.2 ONTROL ONTROL PI PI Figure 33. Line ensing for Undervoltage Only (Overvoltage isabled). Figure 34. Line ensing for Overvoltage Only (Undervoltage isabled). Maximum uty ycle Reduced at Low Line and Further Reduction with Increasing Line. M For R IL = 12 k I LIMIT = 61% For R IL = 19 k I LIMIT = 37% ee Figures 55b for other resistor values (R IL ) to select different I LIMIT values. R L 2.5 M M I LIMIT = 1 I LIMIT = 3 R IL ONTROL R IL 6 k ONTROL PI PI Figure 35. Externally et urrent Limit (Not Normally Required ee M Pin Operation escription). Figure 36. urrent Limit Reduction with Line (Not Normally Required ee M Pin Operation escription). 19

20 TOP Typical Uses of MULTIFUNTION (M) Pin (cont.) Q R can be an optocoupler output or can be replaced by a manual switch. Q R can be an optocoupler output or can be replaced by a manual switch. For R IL = 12 k M R IL M I LIMIT = 61% For R IL = 19 k I LIMIT = 37% Q R ONTROL ONTROL ON/OFF 47 k ON/OFF 16 k Q R PI PI Figure 37. Activeon (Fail afe) Remote ON/OFF. Figure 38. Activeon Remote ON/OFF with Externally et urrent Limit (see M Pin Operation escription). ON/OFF R IL 12 k 7 k Q R M ONTROL R M Q R can be an optocoupler output or can be replaced by a manual switch. 24 k R M = 2R IL Reset 1 k Q R R L M U = I U R L M (I M = I U ) O =I O R L M (I M = I O ) For R L = 4 M 4 M U = 12.8 O = 451 ONTROL ense Output 1 = 76% 375 = 41% PI PI Figure 39. Activeoff Remote ON/OFF with Externally et urrent Limit (see M Pin Operation escription). Figure 4. Lineensing for Undervoltage, Overvoltage, Line FeedForward and Latched Output Overvoltage Protection with evice Reset. 2

21 TOP Application Examples A High Efficiency, 35 W, ual Output Universal Power upply The circuit in Figure 41 takes advantage of several of the TOPwitchHX features to reduce system cost and power supply size and to improve effi ciency. This design delivers 35 W total continuous output power from a 9 A to 265 A input at an ambient of 5 º in an open frame confi guration. A nominal effi ciency of 84% at full load is achieved using TOP258P. With a IP8 package, this design provides 35 W continuous output power using only the copper area on the circuit board underneath the part as a heat sink. The different operating modes of the TOPwitchHX provide signifi cant improvement in the noload, standby, and light load performance of the power supply as compared to the previous generations of the TOPwitch. Resistors R3 and R4 provide line sensing, setting line U at 1 and line O at 45. iode 5, together with resistors R6, R7, capacitor 6 and T R1, forms a clamp network that limits the drain voltage of the TOPwitch after the integrated MOFET turns off. T R1 provides a defi ned maximum clamp voltage and typically only conducts during fault conditions such as overload. This allows the R clamp (R6, R7, 6 and 5) to be sized for normal operation, thereby maximizing effi ciency at light load. hould the feedback circuit fail, the output of the power supply may exceed regulation limits. This increased voltage at output will also result in an increased voltage at the output of the bias winding. Zener R2 will break down and current will fl ow into the M pin of the TOPwitch initiating a hysteretic overvoltage protection with automatic restart attempts. Resistor R5 will limit the current into the M pin to < 336 μa, thus setting hysteretic OP. If latching OP is desired, the value of R5 can be reduced to 2 Ω. The output voltage is controlled using the amplifi er TL431. iode 9, capacitor 2 and resistor R16 form the soft fi nish circuit. At startup, capacitor 2 is discharged. As the output voltage starts rising, current fl ows through the optocoupler diode inside U2A, resistor R13 and diode 9 to charge capacitor 2. This provides feedback to the circuit on the primary side. The current in the optocoupler diode U2A gradually decreases as the capacitor 2 becomes charged and the control amplifi er I U3 becomes operational. This ensures that the output voltage increases gradually and settles to the fi nal value without any overshoot. Resistor R16 ensures that the capacitor 2 is maintained charged at all times after startup, which effectively isolates 2 from the feedback circuit after startup. apacitor 2 discharges through R16 when the supply shuts down. Resistors R2, R21 and R18 form a voltage divider network. The output of this divider network is primarily dependent on the divider circuit formed using R2 and R21 and will vary to some extent for changes in voltage at the 15 output due to the connection of resistor R18 to the output of the divider network. Resistor R19 and Zener R3 improve cross regulation in case only the 5 output is loaded, which results in the 15 output operating at the higher end of the specifi cation nf 1 k nf 25 A R pf 1 L E N L1 6.8 mh F A A R1 1 M R2 1 M 3 22 nf 275 A 1 1N N4937 RT1 1 t O 2 1N47 4 1N F 4 R6 22 k 2 W R3 2. M R4 2. M R7 2 1/2 W 5 FR16 R1 P6KE2A R5 5.1 k R2 1N525B 2 TOPwitchHX M U1 ONTROL TOP258PN 8 1 nf T1 EER FR16 5 R pf 1 R1 4.7 U2B P251 1HA 7 B56 8 B53 R12 33 R16 1 k 9 47 F F F F 22 F nf 25 A R13 33 U2A P251 1HA 9 1N4148 U3 TL431 2% F 25 L2 3.3 H L3 3.3 H R17 1 k R F 5 R15 1 k F 25 R3 BZX55B % nf F 1 R k 1% R19 1 R k 1% R21 1 k 1% 12, 2 A RTN 5, 2.2 A RTN PI Figure W ual Output Power upply using TOP258PN. 21

22 TOP A High Efficiency, 15 W, Power upply The circuit shown in Figure 42 delivers 15 W 7.7 A) at 84% effi ciency using a TOP258Y from a 25 to 38 input. A input is shown, as typically at this power level a power factor correction stage would precede this supply, providing the input. apacitor 1 provides local decoupling, necessary when the supply is remote from the main PF output capacitor. The fl yback topology is still usable at this power level due to the high output voltage, keeping the secondary peak currents low enough so that the output diode and capacitors are reasonably sized. In this example, the TOP258YN is at the upper limit of its power capability. Resistors R3, R6 and R7 provide output power limiting, maintaining relatively constant overload power with input voltage. Line sensing is implemented by connecting a 4 MΩ resistor from the pin to the rail. Resistors R4 and R5 together form the 4 MΩ line sense resistor. If the input rail rises above 45, then TOPwitchHX will stop switching until the voltage returns to normal, preventing device damage. ue to the high primary current, a low leakage inductance transformer is essential. Therefore, a sandwich winding with a copper foil secondary was used. Even with this technique, the leakage inductance energy is beyond the power capability of a simple Zener clamp. Therefore, R1, R2 and 3 are added in parallel to R1 and R3, two series T diodes being used to reduce dissipation. uring normal operation, very little power is dissipated by R1 and R3, the leakage energy instead being dissipated by R1 and R2. However, R1 and R3 are essential to limit the peak drain voltage during startup and/or overload conditions to below the 7 rating of the TOPwitchHX MOFET. The schematic shows an additional turnoff snubber circuit consisting of R2, R21, R22, 5 and 18. This reduces turnoff losses in the TOPwitchHX. The secondary is rectifi ed and smoothed by 2, 3 and 5, 6, 7 and 8. Two windings are used and rectifi ed with separate diodes 2 and 3 to limit diode dissipation. Four capacitors are used to ensure their maximum ripple current specifi cation is not exceeded. Inductor L1 and capacitors 15 and 16 provide switching noise fi ltering. Output voltage is controlled using a TL431 reference I and R15, R16 and R17 to form a potential divider to sense the output voltage. Resistor R12 and R24 together limit the optocoupler LE current and set overall control loop gain. ontrol loop compensation is achieved using components 12, 13, 2 and R13. iode 6, resistor R23 and capacitor 19 form a soft fi nish network. This feeds current into the control pin prior to output regulation, preventing output voltage overshoot and ensuring startup under low line, full load conditions. uffi cient heat sinking is required to keep the TOPwitchHX device below 11 when operating under full load, low line and maximum ambient temperature. Airfl ow may also be required if a large heat sink area is not acceptable F1 4 A RT1 5 t O 1 22 F 4 R3 8.6 k 1% R6 4.7 M R7 4.7 M R2 1.5 k 2 W R k 2 W R k 2 W 5 1N pf 1 k R4 2. M R5 2. ONTROL X R1, R3 P6KE1A R1 R2 68 k 68 k 2 W 2 W R TOPwitchHX U1 TOP258YN F 11 1 nf nf 1 k 1 BY26 R F 1 R2 1N5258B nf 25 A 4 T1 EI35 13, , N F 5 R W 22.5 W R pf 1 k 2 MBR21T 3 MBR21T R18 R23 15 k.125 W U2 P817B 19 1 F pf 1 k R W 6 1N F 5 R W U2 P817A U3 TL431 2% R11 1 k.125 W F nf 5 R13 56 k.125 W F L H 13 1 nf 5 R k 1% R % R k 1% 19, 7.7 A RTN PI Figure W, 19 Power upply using TOP258YN. 22

23 TOP A High Efficiency, 2 W continuous 8 W Peak, Universal Power upply The circuit shown in Figure 43 takes advantage of several of TOPwitchHX features to reduce system cost and power supply size and to improve power supply effi ciency while delivering signifi cant peak power for a short duration. This design delivers continuous 2 W and peak 8 W at 32 from an 9 A to 264 A input. A nominal effi ciency of 82% at full load is achieved using TOP258MN. The Mpackage part has an optimized current limit to enable design of power supplies capable of delivering high power for a short duration. Resistor R12 sets the current limit of the part. Resistors R11 and R14 provide line feed forward information that reduces the current limit with increasing bus voltage, thereby maintaining a constant overload power level with increasing line voltage. Resistors R1 and R2 implement the line undervoltage and overvoltage function and also provide feed forward compensation for reducing line frequency ripple at the output. The overvoltage feature inhibits TOPwitchHX switching during a line surge extending the high voltage withstand to 7 without device damage. The snubber circuit comprising of R7, R17, R25, 5 and 2 limits the maximum drain voltage and dissipates energy stored in the leakage inductance of transformer T1. This clamp confi guration maximizes energy effi ciency by preventing 5 from discharging below the value of R7 during the lower frequency operating modes of TOPwitchHX. Resistor R25 damps high frequency ringing for reduced EMI. A combined output overvoltage and over power protection circuit is provided via the latching shutdown feature of TOPwitchHX and R2, 9, R22 and R5. hould the bias winding output voltage across 13 rise due to output overload or an open loop fault (opto coupler failure), then R5 conducts triggering the latching shutdown. To prevent false triggering due to short duration overload, a delay is provided by R2, R22 and 9. To reset the supply following a latching shutdown, the pin must fall below the reset threshold. To prevent the long reset delay associated with the input capacitor discharging, a fast A reset circuit is used. The A input is rectifi ed and fi ltered by 13 and 3. While the A supply is present, Q3 is on and Q1 is off, allowing normal device operation. However when A is removed, Q1 pulls down the pin and resets the latch. The supply will then return to normal operation when A is again applied. Transistor Q2 provides an additional lower U threshold to the level programmed via R1, R2 and the pin. At low input A voltage, Q2 turns off, allowing the X pin to fl oat and thereby disabling switching. A simple feedback circuit automatically regulates the output voltage. Zener R3 sets the output voltage together with the voltage drop across series resistor R8, which sets the gain of the circuit. Resistors R1 and 28 provide a phase boost to improve loop bandwidth. iodes 6 and 7 are lowloss chottky rectifi ers, and capacitor 2 is the output fi lter capacitor. Inductor L3 is a common mode choke to limit radiated EMI when long output cables are used and the output return is connected to safety earth ground. Example applications where this occurs include P peripherals, such as inkjet printers. L1 5.3 mh R23 1M 8 1N N nf 275 A A R24 1M F A 9 1N47 1 1N47 t o 13 1N47 R3 2M R4 2M 3 1 nf 4 RT1 1 R26 68 k 3 12 F 4 R1 2M R21 1M.125 W R15 1k R2 2M Q1 2N394 R M R M Q3 2N394 R18 39 k R k 1% Q2 2N394 R7 BZY R17 1k.5 W ONTROL X TOPwitchHX U4 TOP258MN R nf 1k 2 FR17 R5 1N525B nf nf 25 A N T1 EF25 R22 2 M R F F 5 5 LL4148 R pf.5 W 1 k 9 1 F 1 67 TP nF 25 A R2 13 k R nf F 5 U2A P F L H R8 1.5 k R3 1N5255B 28 R9 2k PI L3 47 H ma, 2.5 A PK nf 5 RTN Figure W ontinuous, 8 W Peak, Universal Power upply using TOP258MN. 23

24 TOP A High Efficiency, 65 W, Universal Power upply The circuit shown in Figure 44 delivers 65 W 3.42 A) at 88% effi ciency using a TOP26EN operating over an input voltage range of 9 A to 265 A. apacitors 1 and 6 and inductors L1 and L2 provide common mode and differential mode EMI fi ltering. apacitor 2 is the bulk fi lter capacitor that ensures low ripple input to the fl yback converter stage. apacitor 4 provides decoupling for switching currents reducing differential mode EMI. In this example, the TOP26EN is used at reduced current limit to improve effi ciency. Resistors R5, R6 and R7 provide power limiting, maintaining relatively constant overload power with input voltage. Line sensing is implemented by connecting a 4 MΩ impedance from the pin to the rail. Resistors R3 and R4 together form the 4 MΩ line sense resistor. If the input rail rises above 45, then TOP witchhx will stop switching until the voltage returns to normal, preventing device damage. This circuit features a high effi ciency clamp network consisting of diode 1, zener R1, capacitor 5 together with resistors R8 and R9. The snubber clamp is used to dissipate the energy into the leakage reactance of the transformer. At light load levels, very little power is dissipated by R1 improving effi ciency as compared to a conventional R clamp network. The secondary output form the transformer is rectifi ed by diode 2 and fi ltered by capacitors 13 and 14. Ferrite Bead L3 and capacitors 15 form a second stage fi lter and effectively reduce the switching noise to the output. Output voltage is controlled using a LM431 reference I. Resistor R19 and R2 form a potential divider to sense the output voltage. Resistor R16 limits the optocoupler LE current and sets the overall control loop gain. ontrol loop compensation is achieved using 18 and R21. The components connected to the control pin on the primary side 8, 9 and R15 set the low frequency pole and zero to further shape the control loop response. apacitor 17 provides a soft fi nish during startup. Optocoupler U2 is used for isolation of the feedback signal. iode 4 and capacitor 1 form the bias winding rectifi er and fi lter. hould the feedback loop break due to a defective component, a rising bias winding voltage will cause the zener R2 to break down and trigger the over voltage protection which will inhibit switching. An optional secondary side over voltage protection feature which offers higher precision (as compared to sensing via the bias winding) is implemented using R2, R14 and U2. Excess voltage at the output will cause current to fl ow through the optocoupler U3 LE which in turn will inject current in the pin through resistor R13, thereby triggering the over voltage protection feature nf 1 k R1 BZY nf 25 A T1 RM1 FL nf 1 R F 47 F L3 Ferrite Bead F 25 19, 3.42 A L E N A L1 12 mh R1 R2 2.2 M 2.2 M 1 3KBP8M BR1 R8 1 1 L4937 R9 1 k 5 BA19W 3 BA19W F1 33 nf 4 A 275 A TOPwitchHX U1 TOP26EN 3 47 pf 25 A L2 Ferrite Bead 2 12 F 4 R3 2. M R4 2. M R7 15 k 1% R5 5.1 M R6 6.8 M 4 1 nf 4 ONTROL X F 8 1 nf FL2 3 2 R k 7 1 nf 25 R R14 1 R F F 5 4 BA19W 2 MBR21T 16 1 F 5 R1 R k 1N5248B 18 U3B P357A U2B LTY817 R11 2 M F nf 5 R16 68 U2A LTY N4148 U4 LM431 2% 18 1 nf R k R21 1 k R2 1 k R3 BZX R18 47 U3A P357A RTN PI Figure W, 19 Power upply Using TOP26EN. 24

25 TOP Key Application onsiderations TOPwitchHX vs. TOPwitchGX Table 4 compares the features and performance differences between TOPwitchHX and TOPwitchGX. Many of the new features eliminate the need for additional discrete components. Other features increase the robustness of design, allowing cost savings in the transformer and other power components. TOPwitchHX vs. TOPwitchGX Function TOPwitchGX TOPwitchHX TOPwitchHX Advantages Ecomart Linear frequency reduction to 3 khz (@ 132 khz) for duty cycles < 1% Multimode operation with linear frequency reduction to 3 khz (@ 132 khz) and multicycle modulation (virtually no audible noise) Improved effi ciency over load (e.g. at 25% load point) Improved standby effi ciency Improved noload consumption Output Overvoltage Protection (OP) Not available User programmable primary or secondary hysteretic or latching OP Protects power supply output during open loop fault Maximum design fl exibility Line FeedForward with uty ycle Reduction Linear reduction ual slope reduction with lower, more accurate onset point Improved line ripple rejection maller bus capacitor witching Frequency IP8 Package 132 khz 66 khz Increased output power for given MOFET size due to higher effi ciency Lowest MOFET On Resistance in IP8 Package 3. Ω (TOP246P) 1.8 Ω (TOP258P) Increased output power in designs without external heatsink I 2 f Trimming Not available 1% / 2% Increased output power for given core size Reduced overload power Autorestart uty ycle 5.6% 2% Reduced delivered average output power during open loop faults Frequency Jitter ±4 132 khz ±2 66 khz ±5 132 khz ± khz Reduced EMI fi lter cost Thermal hutdown 13 to to 15 Increased design margin External urrent Limit 3%1% of I LIMIT 3%1% of I LIMIT, additional trim at.7 I LIMIT Reduced tolerances when current limit is set externally Line U etection Threshold 5 μa (2 MΩ sense impedance) 25 μa (4 MΩ sense impedance) Reduced dissipation for lower noload consumption ofttart 1 ms duty cycle and current limit ramp 17 ms sweep through multimode characteristic Reduced peak current and voltage component stress at startup mooth output voltage rise Table 4. omparison Between TOPwitchGX and TOPwitchHX. 25

26 TOP TOPwitchHX esign onsiderations Power Table The data sheet power table (Table 1) represents the maximum practical continuous output power based on the following conditions: output. chottky or high effi ciency output diode. 135 refl ected voltage ( OR ) and effi ciency estimates. A 1 minimum for A and 25 minimum for 23 A. uffi cient heat sinking to keep device temperature 1. Power levels shown in the power table for the M/P package device assume 6.45 cm 2 of 61 g/m 2 copper heat sink area in an enclosed adapter, or 19.4 cm 2 in an open frame. The provided peak power depends on the current limit for the respective device. TOPwitchHX election electing the optimum TOPwitchHX depends upon required maximum output power, effi ciency, heat sinking constraints, system requirements and cost goals. With the option to externally reduce current limit, an Y, E or M package TOPwitchHX may be used for lower power applications where higher effi ciency is needed or minimal heat sinking is available. apacitor The input capacitor must be chosen to provide the minimum voltage required for the TOPwitchHX converter to maintain regulation at the lowest specifi ed input voltage and maximum output power. ince TOPwitchHX has a high MAX limit and an optimized dual slope line feed forward for ripple rejection, it is possible to use a smaller input capacitor. For TOPwitchHX, a capacitance of 2 μf per watt is possible for universal input with an appropriately designed transformer. Primary lamp and Output Reflected OR A primary clamp is necessary to limit the peak TOPwitchHX drain to source voltage. A Zener clamp requires few parts and takes up little board space. For good effi ciency, the clamp Zener should be selected to be at least 1.5 times the output refl ected voltage OR, as this keeps the leakage spike conduction time short. When using a Zener clamp in a universal input application, a OR of less than 135 is recommended to allow for the absolute tolerances and temperature variations of the Zener. This will ensure effi cient operation of the clamp circuit and will also keep the maximum drain voltage below the rated breakdown voltage of the TOPwitchHX MOFET. A high OR is required to take full advantage of the wider MAX of TOPwitchHX. An R clamp provides tighter clamp voltage tolerance than a Zener clamp and allows a OR as high as 15. R clamp dissipation can be minimized by reducing the external current limit as a function of input line voltage (see Figures 23 and 36). The R clamp is more cost effective than the Zener clamp but requires more careful design (see Quick esign hecklist). Output iode The output diode is selected for peak inverse voltage, output current, and thermal conditions in the application (including 26 heat sinking, air circulation, etc.). The higher MAX of TOPwitchHX, along with an appropriate transformer turns ratio, can allow the use of a 8 chottky diode for higher effi ciency on output voltages as high as 15 (see Figure 41). Bias Winding apacitor ue to the low frequency operation at noload, a 1 μf bias winding capacitor is recommended. ofttart Generally, a power supply experiences maximum stress at startup before the feedback loop achieves regulation. For a period of 17 ms, the onchip softstart linearly increases the drain peak current and switching frequency from their low starting values to their respective maximum values. This causes the output voltage to rise in an orderly manner, allowing time for the feedback loop to take control of the duty cycle. This reduces the stress on the TOPwitchHX MOFET, clamp circuit and output diode(s), and helps prevent transformer saturation during startup. Also, softstart limits the amount of output voltage overshoot and, in many applications, eliminates the need for a softfi nish capacitor. EMI The frequency jitter feature modulates the switching frequency over a narrow band as a means to reduce conducted EMI peaks associated with the harmonics of the fundamental switching frequency. This is particularly benefi cial for average detection mode. As can be seen in Figure 45, the benefi ts of jitter increase with the order of the switching harmonic due to an increase in frequency deviation. evices in the P, G or M package and TOP259261YN operate at a nominal switching frequency of 66 khz. The FREQUENY pin of devices in the TOP Y and E packages offer a switching frequency option of 132 khz or 66 khz. In applications that require heavy snubber on the drain node for reducing high frequency radiated noise (for example, video noise sensitive applications such as Rs, s, monitors, Ts, etc.), operating at 66 khz will reduce snubber loss, resulting in better effi ciency. Also, in applications where transformer size is not a concern, use of the 66 khz option will provide lower EMI and higher effi ciency. Note that the second harmonic of 66 khz is still below 15 khz, above which the conducted EMI specifi cations get much tighter. For 1 W or below, it is possible to use a simple inductor in place of a more costly A input common mode choke to meet worldwide conducted EMI limits. Transformer esign It is recommended that the transformer be designed for maximum operating fl ux density of 3 Gauss and a peak fl ux density of 42 Gauss at maximum current limit. The turns ratio should be chosen for a refl ected voltage ( OR ) no greater than 135 when using a Zener clamp or 15 (max) when using an R clamp with current limit reduction with line voltage (overload protection). For designs where operating current is signifi cantly lower than the default current limit, it is recommended to use an externally set current limit close to the operating peak current to reduce peak fl ux density and peak power (see Figures 22 and 35). In most applications, the tighter current limit tolerance, higher switching frequency and softstart features of TOPwitchHX contribute to a smaller transformer when compared to TOPwitchGX.

27 TOP Amplitude (db ) EN5522B (QP) EN5522B (A) Frequency (MHz) Figure 45a. Fixed Frequency Operation Without Jitter. Amplitude (db ) TOPwitchHX (with jitter) 1 EN5522B (QP) EN5522B (A) Frequency (MHz) Figure 45b. TOPwitchHX Full Range EMI can (132 khz With Jitter) With Identical ircuitry and onditions. tandby onsumption Frequency reduction can signifi cantly reduce power loss at light or no load, especially when a Zener clamp is used. For very low secondary power consumption, use a TL431 regulator for feedback control. A typical TOPwitchHX circuit automatically enters MM mode at no load and the low frequency mode at light load, which results in extremely low losses under noload or standby conditions. High Power esigns The TOPwitchHX family contains parts that can deliver up to 333 W. High power designs need special considerations. Guidance for high power designs can be found in the esign Guide for TOPwitchHX (AN43). TOPwitchHX Layout onsiderations PI PI Primary ide onnections Use a single point (Kelvin) connection at the negative terminal of the input fi lter capacitor for the TOPwitchHX OURE pin and bias winding return. This improves surge capabilities by returning surge currents from the bias winding directly to the input fi lter capacitor. The ONTROL pin bypass capacitor should be located as close as possible to the OURE and ONTROL pins, and its OURE connection trace should not be shared by the main MOFET switching currents. All OURE pin referenced components connected to the MULTI FUNTION (Mpin), OLTAGE MONITOR (pin) or EXTERNAL URRENT LIMIT (Xpin) pins should also be located closely between their respective pin and OURE. Once again, the OURE connection trace of these components should not be shared by the main MOFET switching currents. It is very critical that OURE pin switching currents are returned to the input capacitor negative terminal through a separate trace that is not shared by the components connected to ONTROL, MULTIFUNTION, OLTAGE MONITOR or EXTERNAL URRENT LIMIT pins. This is because the OURE pin is also the controller ground reference pin. Any traces to the M, or X pins should be kept as short as possible and away from the RAIN trace to prevent noise coupling. OLTAGE MONITOR resistors (R1 and R2 in Figures 46, 47, 48, R3 and R4 in Figure 49, and R14 in Figure 5) should be located close to the M or pin to minimize the trace length on the M or pin side. Resistors connected to the M, or X pin should be connected as close to the bulk cap positive terminal as possible while routing these connections away from the power switching circuitry. In addition to the 47 μf ONTROL pin capacitor, a high frequency bypass capacitor in parallel may be used for better noise immunity. The feedback optocoupler output should also be located close to the ONTROL and OURE pins of TOPwitchHX. Yapacitor The Ycapacitor should be connected close to the secondary output return pin(s) and the positive primary input pin of the transformer. Heat inking The tab of the Y package (TO22) and E package (eip7) are internally electrically tied to the OURE pin. To avoid circulating currents, a heat sink attached to the tab should not be electrically tied to any primary ground/source nodes on the P board. When using a P (IP8), G (M8) or M (IP1) package, a copper area underneath the package connected to the OURE pins will act as an effective heat sink. On double sided boards, topside and bottom side areas connected with vias can be used to increase the effective heat sinking area. In addition, suffi cient copper area should be provided at the anode and cathode leads of the output diode(s) for heat sinking. In Figures 46 to 5 a narrow trace is shown between the output rectifi er and output fi lter capacitor. This trace acts as a thermal relief between the rectifi er and fi lter capacitor to prevent excessive heating of the capacitor. The TOPwitchHX has multiple pins and may operate at high power levels. The following guidelines should be carefully followed. 27

28 TOP Isolation Barrier Optional PB slot for external heatsink in contact with OURE pins 2 R4 Y1 apacitor 6 T1 Filter apacitor R1 R3 1 R9 Output Rectifier H J1 JP1 1 U1 1 M Transformer 3 7 Output Filter apacitor L1 R1 R2 Maximize hatched copper areas ( ) for optimum heat sinking 3 4 R8 R6 R7 R2 2 R8 5 JP2 U2 R13 R14 R12 U3 9 R11 R1 8 J2 Out PI Figure 46. Layout onsiderations for TOPwitchHX Using PPackage. Isolation Barrier Optional PB slot for external heatsink in contact with OURE pins 2 R6 Y1 apacitor 6 T1 Filter apacitor R1 R5 R12 Output Rectifier H J1 1 U1 1 X Transformer 3 7 Output Filter apacitor L1 JP1 R1 R2 R3 R4 Maximize hatched copper areas ( ) for optimum heat sinking R7 4 R8 3 R9 R2 R1 2 R11 5 JP2 U2 9 R14 U3 R15 R16 R17 R13 8 J2 Out PI Figure 47. Layout onsiderations for TOPwitchHX Using MPackage. 28

29 TOP Isolation Barrier H Filter apacitor J1 1 H1 R1 2 R4 R3 1 U1 F X Y1 apacitor 6 Transformer T1 3 R Output Rectifier Output Filter apacitor L1 JP1 R1 R2 R7 R8 4 R1 2 5 U3 9 R13 8 R3 R4 R9 R11 R2 JP2 U2 R16 R12 R15 R17 R14 J2 Out PI Figure 48. Layout onsiderations for TOPwitchHX Using TOP YPackage. Isolation Barrier Filter apacitor R1 R6 6 5 R7 T1 Y1 apacitor 7 16 R12 Output Filter apacitor H J1 4 H1 X G U5 8 Transformer 8 R3 R L3 JP1 R11 R14 R22 R9 R8 6 1 U4 21 R21 R2 18 R2 R5 R1 JP2 U2 R15 R17 R13 J2 Out PI Figure 49. Layout onsiderations for TOPwitchHX Using TOP YPackage. 29

30 TOP Isolation Barrier H Filter apacitor J1 4 R4 R3 8 H1 U1 F X R6 R R8 R1 R7 T1 Y1 apacitor 7 Transformer R12 L3 H52 Output Rectifier Output Filter apacitor R11 R5 R14 R R1 U R2 19 R9 JP2 U2 R15 R17 R13 R21 J2 Out PI Figure 5a. Layout onsiderations for TOPwitchHX Using EPackage and Operating at 66 KHz. Isolation Barrier H Filter apacitor J1 4 H51 R6 5 6 R7 Y1 apacitor R12 H52 Output Rectifier R4 R3 8 U1 F X 9 R1 R22 Transformer 17 L3 Output Filter apacitor R11 R5 R14 R8 R2 6 R9 1 R1 JP2 U2 U4 21 R17 R13 R15 18 R21 R2 19 J2 Out PI Figure 5b. Layout onsiderations for TOPwitchHX Using EPackage and Operating at 132 KHz. 3

31 TOP Quick esign hecklist In order to reduce the noload input power of TOPwitchHX designs, the pin (or Mpin for P Package) operates at very low current. This requires careful layout considerations when designing the PB to avoid noise coupling. Traces and components connected to the pin should not be adjacent to any traces carrying switching currents. These include the drain, clamp network, bias winding return or power traces from other converters. If the line sensing features are used, then the sense resistors must be placed within 1 mm of the pin to minimize the pin node area. The bus should then be routed to the line sense resistors. Note that external capacitance must not be connected to the pin as this may cause misoperaton of the pin related functions. As with any power supply design, all TOPwitchHX designs should be verifi ed on the bench to make sure that components specifi cations are not exceeded under worstcase conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage erify that peak does not exceed 675 at highest input voltage and maximum overload output power. Maximum overload output power occurs when the output is overloaded to a level just before the power supply goes into autorestart (loss of regulation) Maximum drain current At maximum ambient temperature, maximum input voltage and maximum output load, verify drain current waveforms at startup for any signs of transformer saturation and excessive leading edge current spikes. TOPwitchHX has a leading edge blanking time of 22 ns to prevent premature termination of the ONcycle. erify that the leading edge current spike is below the allowed current limit envelope (see Figure 53) for the drain current waveform at the end of the 22 ns blanking period. Thermal check At maximum output power, both minimum and maximum voltage and ambient temperature; verify that temperature specifi cations are not exceeded for TOPwitchHX, transformer, output diodes and output capacitors. Enough thermal margin should be allowed for the parttopart variation of the R (ON) of TOPwitchHX, as specifi ed in the data sheet. The margin required can either be calculated from the values in the parameter table or it can be accounted for by connecting an external resistance in series with the RAIN pin and attached to the same heat sink, having a resistance value that is equal to the difference between the measured R (ON) of the device under test and the worst case maximum specifi cation. esign Tools Uptodate information on design tools can be found at the Power Integrations website: 31

32 TOP Absolute Maximum Ratings (2) RAIN Peak....3 to 7 RAIN Peak urrent: TOP A RAIN Peak urrent: TOP A RAIN Peak urrent: TOP A RAIN Peak urrent: TOP A RAIN Peak urrent: TOP A RAIN Peak urrent: TOP A RAIN Peak urrent: TOP A RAIN Peak urrent: TOP A RAIN Peak urrent: TOP A RAIN Peak urrent: TOP A ONTROL...3 to 9 ONTROL urrent... 1 ma OLTAGE MONITOR Pin...3 to 9 URRENT LIMIT Pin...3 to 4.5 MULTIFUNTION Pin...3 to 9 FREQUENY Pin....3 to 9 torage Temperature...65 to 15 Operating Junction Temperature... 4 to 15 Lead Temperature (1)...26 Notes: 1. 1/16 in. from case for 5 seconds. 2. Maximum ratings specifi ed may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. Thermal Impedance Thermal Impedance: Y Package: (θ JA )...8 /W (1) (θ J ) /W (2) P, G and M Packages: (θ JA )...7 /W (3) ; 6 /W (4) (θ J ) /W (5) E Package: (θ JA )...15 /W (1) (θ J ) /W (2) Parameter ontrol Functions witching Frequency in Full Frequency Mode (average) Frequency Jitter Frequency Jitter Modulation Rate ymbol f O = 25 Δf onditions OURE = ; = 4 to 125 ee Figure 54 (Unless Otherwise pecified) Notes: 1. Free standing with no heatsink. 2. Measured at the back surface of tab. 3. oldered to.36 sq. in. (232 mm 2 ), 2 oz. (61 g/m 2 ) copper clad. 4. oldered to 1 sq. in. (645 mm 2 ), 2 oz. (61 g/m 2 ) copper clad. 5. Measured on the OURE pin close to plastic interface. Min Typ Max Units FREQUENY Pin onnected to OURE E Package and TOP TOP258 in Y Package FREQUENY Pin onnected to ONTROL M/P/G/Y/E Packages 132 khz Operation ±5 66 khz Operation ±2.5 f M 25 Hz Maximum uty ycle MAX I = I 1, M = I I or I I or () M M() I or I M = 95 μa 3 ofttart Time t OFT = ms PWM Gain reg = 25 PWM Gain Temperature rift External Bias urrent I B 66 khz Operation 132 khz Operation TOP TOP TOP khz khz % %/ma ee Note A.1 %/ma/ TOP TOP TOP TOP TOP TOP ma 32

33 TOP Parameter ymbol onditions OURE = ; = 4 to 125 (Unless Otherwise pecified) Min Typ Max Units ontrol Functions (cont.) ONTROL urrent at % uty ycle ynamic Impedance ynamic Impedance Temperature rift ONTROL Pin Internal Filter Pole Upper Peak urrent to et urrent Limit Ratio Lower Peak urrent to et urrent Limit Ratio I (OFF) 66 khz Operation 132 khz Operation TOP TOP TOP TOP TOP TOP Z I = 4 ma; = 25, ee Figure Ω ma.18 %/ 7 khz k P(UPPER) = % k P(LOWER) = % Multiycle Modulation witching Frequency f MM(MIN) = 25 3 khz Minimum Multiycle Modulation On Period hutdown/autorestart ontrol Pin harging urrent T MM(MIN) = μs I (H) = 25 = = harging urrent Temperature rift ee Note A.5 %/ AutoRestart Upper Threshold (AR)U 5.8 AutoRestart Lower Threshold (AR)L MultiFunction (M), Monitor () and External urrent Limit (X) s AutoRestart Hysteresis (AR)hyst.8 1. AutoRestart uty ycle (AR) 2 4 % AutoRestart Frequency f (AR).5 Hz Line Undervoltage Threshold μa Threshold urrent and Hysteresis (M or Pin) I U = 25 Hysteresis 14 μa Line Overvoltage Threshold μa Threshold urrent and Hysteresis (M or Pin) I O = 25 Hysteresis 4 μa ma 33

34 TOP Parameter ymbol onditions OURE = ; = 4 to 125 (Unless Otherwise pecified) Min Typ Max Units MultiFunction (M), Monitor () and External urrent Limit (X) s Output Overvoltage Latching hutdown Threshold urrent I O(L) = μa or M Pin Reset Remote ON/OFF Negative Threshold urrent and Hysteresis (M or X Pin) or M Pin hort ircuit urrent X or M Pin hort ircuit urrent or M Pin (Positive urrent) or M Pin Hysteresis (Positive urrent) X or M Pin (Negative urrent) Maximum uty ycle Reduction Onset Threshold urrent (TH) or M(TH) = I REM (N) = 25 Threshold Hysteresis 5 I () or I M() = 25, M = μa I X() or I M() or M X, M = Normal Mode AutoRestart Mode I or I M = I U I or I M = I O TOP252TOP TOP258TOP (hyst) or M(hyst) I or I M = I O.2.5 I X or I M = 5 μa X or M I X or I M = 15 μa I () or I M() I I B, = μa μa μa Maximum uty ycle Reduction lope = 25 I () < I <48 μa or I M() < I M <48 μa 1. I or I M 48 μa.25 %/μa Remote OFF RAIN upply urrent I (RMT) RAIN = 15 Remote ON elay t R(ON) TurnOn From Remote ON to rain ee Note B X, or M Pin Floating or M Pin horted to ONTROL 66 khz khz ma μs Remote OFF etup Time t R(OFF) Minimum Time Before rain TurnOn to isable ycle ee Note B Frequency FREQUENY Pin Threshold 66 khz khz 1.5 F ee Note B 2.9 μs FREQUENY Pin urrent I F = 25 F = μa 34

35 TOP Parameter ymbol onditions OURE = ; = 4 to 125 (Unless Otherwise pecified) Min Typ Max Units ircuit Protection TOP252PN/GN/MN = 25 di/dt = 45 ma/μs TOP252EN = 25 di/dt = 9 ma/μs TOP253PN/GN = 25 di/dt = 8 ma/μs TOP253MN = 25 di/dt = 9 ma/μs TOP253EN = 25 di/dt = 18 ma/μs TOP254PN/GN = 25 di/dt = 15 ma/μs TOP254MN = 25 di/dt = 135 ma/μs TOP254YN/EN = 25 di/dt = 27 ma/μs TOP255PN/GN = 25 di/dt = 12 ma/μs TOP255MN = 25 di/dt = 175 ma/μs elf Protection urrent Limit (ee Note ) I LIMIT TOP255YN/EN = 25 TOP256PN/GN = 25 TOP256MN = 25 di/dt = 35 ma/μs di/dt = 14 ma/μs di/dt = 22 ma/μs A TOP256YN/EN = 25 di/dt = 53 ma/μs TOP257PN/GN = 25 di/dt = 155 ma/μs TOP257MN = 25 di/dt = 265 ma/μs TOP257YN/EN = 25 di/dt = 75 ma/μs TOP258PN/GN = 25 di/dt = 17 ma/μs TOP258MN = 25 di/dt = 31 ma/μs TOP258YN/EN = 25 di/dt = 89 ma/μs TOP259YN/EN = 25 di/dt = 165 ma/μs TOP26YN/EN = 25 di/dt = 124 ma/μs TOP261YN/EN = 25 di/dt = 153 ma/μs

36 TOP Parameter ymbol onditions OURE = ; = 4 to 125 (Unless Otherwise pecified) Min Typ Max Units ircuit Protection (cont.) Initial urrent Limit I INIT ee Note B.7 I LIMIT(MIN) A Power oefficient P OEFF = 25, ee Note I X or I M 165 μa.9 I 2 I 2 f 1.2 I 2 f I X or I M 117 μa.9 I 2 I 2 f 1.2 I 2 f Leading Edge Blanking Time t LEB = 25, ee Figure ns urrent Limit elay t IL() 1 ns Thermal hutdown Temperature Thermal hutdown Hysteresis PowerUp Reset Threshold Output ONtate Resistance RAIN upply A 2 khz (REET) Figure 54 (1 Open ondition) R (ON) TOP252 I = 5 ma TOP253 I = 1 ma TOP254 I = 15 ma TOP255 I = 2 ma TOP256 I = 3 ma TOP257 I = 4 ma TOP258 I = 5 ma TOP259 I = 6 ma TOP26 I = 7 ma TOP261 I = 8 ma 85, ee Note E = = = = = = = = = = = = = = = = = = = = Ω 36

37 TOP Parameter ymbol onditions OURE = ; = 4 to 125 (Unless Otherwise pecified) Min Typ Max Units Output (cont.) OFFtate rain Leakage urrent I, M = Floating, I = 4 ma, = 56, = μa Breakdown B, M = Floating, I = 4 ma, = 25 ee Note F 7 Rise Time t R Measured in a Typical Flyback 1 ns Fall Time t F onverter Application 5 ns upply haracteristics ontrol upply/ ischarge urrent I 1 I 2 Output MOFET Enabled X,, M = 66 khz Operation 132 khz Operation TOP TOP TOP TOP TOP TOP Output MOFET isabled X,, M = ma NOTE: A. For specifi cations with negative values, a negative temperature coeffi cient corresponds to an increase in magnitude with increasing temperature, and a positive temperature coeffi cient corresponds to a decrease in magnitude with increasing temperature. B. Guaranteed by characterization. Not tested in production... For externally adjusted current limit values, please refer to Figures 55a and 55b (urrent Limit vs. External urrent Limit Resistance) in the Typical Performance haracteristics section. The tolerance specifi ed is only valid at full current limit. I 2 f calculation is based on typical values of I LIMIT and f O, i.e. I LIMIT(TYP)2 f O, where f O = 66 khz or 132 khz depending on package / F pin connection. ee f O specifi cation for detail. E. F. The TOPwitchHX will start up at 18 drain voltage. The capacitance of electrolytic capacitors drops signifi cantly at temperatures below. For reliable start up at 18 in sub zero temperatures, designers must ensure that circuit capacitors meet recommended capacitance values. Breakdown voltage may be checked against minimum B specifi cation by ramping the RAIN pin voltage up to but not exceeding minimum B. 37

38 TOP t 2 H 9% t 1 9% RAIN OLTAGE = t 1 t 2 1% PI Figure 51. uty ycle Measurement. ONTROL Pin urrent (ma) ynamic 1 Impedance = lope ONTROL Pin () Figure 52. ONTROL Pin I haracteristic. PI RAIN urrent (normalized) t LEB (Blanking Time) I INIT(MIN) Time ( s) Figure 53. rain urrent Operating Envelope. PI P or G Package (M Pin) TOP Y, E or M Packages (X and Pins) 3 kω 1 47 Ω 5 W 3 kω kω M Ω 2 47 μf.1 μf TOPwitchHX ONTROL 4 F X 3 6 kω TOP Y (X and Pins) 3 kω ONTROL 55 G X NOTE: 1. This test circuit is not applicable for current limit or output characteristic measurements. 2. For P, G and M packages, short all OURE pins together. PI Figure 54. TOPwitchHX General Test ircuit. 38

39 TOP Typical Performance haracteristics 1.1 PI Maximum 1.9 Normalized urrent Limit Minimum Notes: 1. Maximum and Minimum levels are based on characterization; 2. = O to 125 O Typical Normalized di/dt I X or I M ( μa ) Figure 55a. Normalized urrent Limit vs. X or M Pin urrent. Normalized urrent Limit Maximum Typical Notes: 1. Maximum and Minimum levels are based on characterization; 2. = O to 125 O ; 3. Includes the variation of X or M pin voltage PI Normalized di/dt Minimum R IL ( kω ) Figure 55b. Normalized urrent Limit vs. External urrent Limit Resistance. 39

40 TOP Typical Performance haracteristics (cont.) Breakdown (Normalized to 25 ) PI176B331 Output Frequency (Normalized to 25 ) PI Junction Temperature ( ) Figure 56. Breakdown vs. Temperature Junction Temperature ( ) Figure 57. Frequency vs. Temperature. urrent Limit (Normalized to 25 ) PI urrent Limit (Normalized to 25 ) PI Junction Temperature ( ) Figure 58. Internal urrent Limit vs. Temperature. Figure Junction Temperature ( ) External urrent Limit vs. Temperature with R IL = 1.5 kω. Overvoltage Threshold (Normalized to 25 ) PI Under Threshold (Normalized to 25 ) PI Junction Temperature ( ) Figure 6. Overvoltage Threshold vs. Temperature Junction Temperature ( ) Figure 61. Undervoltage Threshold vs. Temperature. 4

41 TOP Typical Performance haracteristics (cont.) OLTAGE MONITOR Pin () OLTAGEMONITOR Pin urrent ( A) Figure 62a. LINEENE Pin vs. urrent. PI EXTERNAL URRENT LIMIT Pin () X = I X (I X ) 2 with 18 A I X 25 A EXTERNAL URRENT LIMIT Pin urrent ( A) Figure 62b. EXTERNAL URRENT LIMIT Pin vs. urrent. PI MULTIFUNTION Pin () ee expanded version (Figure 63b) MULTIFUNTION Pin urrent ( A) Figure 63a. MULTIFUNTION Pin vs. urrent. PI MULTIFUNTION Pin () M = I M (I M ) 2 with 18 A I M 25 A MULTIFUNTION Pin urrent ( A) Figure 63b. MULTIFUNTION Pin vs. urrent (Expanded). PI ONTROL urrent (Normalized to 25 ) caling Factors: TOP TOP TOP TOP TOP TOP TOP TOP TOP253.2 TOP252.1 PI Onset Threshold urrent (Normalized to 25 ) PI Junction Temperature ( ) Figure 64. ontrol urrent Out at % uty ycle vs. Temperature Junction Temperature ( ) Figure 65. Maximum uty ycle Reduction Onset Threshold urrent vs. Temperature. 41

42 TOP Typical Performance haracteristics (cont.) RAIN urrent (A) T AE = 25 T AE = Figure 66. Output haracteristics. rain () caling Factors: TOP TOP TOP259 1,17 TOP TOP TOP TOP TOP TOP253.2 TOP252.1 PI ONTROL Pin urrent (ma) = 5 caling Factors: TOP TOP TOP259 1,17 TOP TOP TOP TOP TOP TOP253.2 TOP Figure 67. I vs. RAIN. rain Pin () PI RAIN apacitance (pf) caling Factors: TOP TOP TOP TOP TOP TOP TOP TOP TOP253.2 TOP252.1 PI Power (mw) caling Factors: TOP TOP TOP TOP TOP TOP TOP TOP TOP253.2 TOP khz 66 khz PI rain Pin () Figure 68. O vs. RAIN rain Pin () Figure 69. RAIN apacitance Power. Remote OFF RAIN upply urrent (Normalized to 25 ) Junction Temperature ( ) Figure 7. Remote OFF RAIN upply urrent vs. Temperature. PI

43 TOP TO (3.71).156 (3.96).39 (9.91).42 (1.67).18 (2.74) REF.165 (4.19).185 (4.7).234 (5.94).261 (6.63).45 (1.14).55 (1.4).86 (21.84).88 (22.35).461 (11.71).495 (12.57) 7 TYP..8 (2.3).12 (3.5).57 (14.48) REF..67 (17.2) REF. PIN 1.5 (1.27).5 (1.27).5 (1.27).2 (5.8).18 (4.58).1 (2.54) PIN 1 PIN 7.15 (3.81).68 (1.73) MIN.24 (.61).34 (.86).5 (1.27) B.15 (3.81) B.5 (1.27).1 (.25) M.15 (3.81) PIN 1 & 7 PIN 2 & 4.4 (1.2).6 (1.52).12 (.3).4 (1.2).24 (.61).6 (1.52).19 (4.83).21 (5.33) Notes: 1. ontrolling dimensions are inches. Millimeter dimensions are shown in parentheses. 2. Pin numbers start with Pin 1, and continue from left to right when viewed from the front. 3. imensions do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed.6 (.15mm) on any side. 4. Minimum metal to metal spacing at the package body for omitted pin locations is.68 in. (1.73 mm). 5. Position of terminals to be measured at a location.25 (6.35) below the package body. 6. All terminals are solder plated. Y7 MOUNTING HOLE PATTERN PI

44 TOP IP8.24 (6.1).26 (6.6) Pin 1 E.4 (.1).367 (9.32).387 (9.83).57 (1.45).68 (1.73) (NOTE 6) Notes: 1. Package dimensions conform to JEE specification M1AB (Issue B 7/85) for standard dualinline (IP) package with.3 inch row spacing. 2. ontrolling dimensions are inches. Millimeter sizes are shown in parentheses. 3. imensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed.6 (.15) on any side. 4. Pin locations start with Pin 1, and continue counterclockwise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted. 5. Minimum metal to metal spacing at the package body for the omitted lead location is.137 inch (3.48 mm). 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be perpendicular to plane T..125 (3.18).145 (3.68).15 (.38) MINIMUM T EATING PLANE.12 (3.5).14 (3.56).8 (.2).15 (.38).1 (2.54) B.14 (.36).22 (.56).48 (1.22).137 (3.48).53 (1.35) MINIMUM T E.1 (.25) M.3 (7.62) B (NOTE 7).3 (7.62).39 (9.91) P8 PI IP (6.1).26 (6.6) Notes: 1. Package dimensions conform to JEE specification M ontrolling dimensions are inches. Millimeter sizes are shown in parentheses. 3. imensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed.6 (.15) on any side. 4., E and F are reference datums. 5. imensioning and tolerancing conform to AME Y14.5M (9.32).387 (9.83).3 (7.62).34 ( (5.8) Max.125 (3.18).145 (3.68) EATING PLANE.2 (.51) Min E F.12 (3.5).14 (3.56).8 (.2).15 (.38).7 (1.78) B.3 B.14 (.36).1 (.25) M F E.22 (.56).3 (.76).4 (1.2).3 (7.62).39 (9.91) P1 PI

45 TOP M8 E.24 (6.1).26 (6.6) Pin (3.18).145 (3.68).4 (.1).1 (2.54) (B).367 (9.32).387 (9.83).372 (9.45).388 (9.86) E.1 (.25).137 (3.48) MINIMUM.57 (1.45).68 (1.73) (NOTE 5) Pin 1 older Pad imensions Notes: 1. ontrolling dimensions are inches. Millimeter sizes are shown in parentheses. 2. imensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed.6 (.15) on any side. 3. Pin locations start with Pin 1, and continue counterclockwise to Pin 8 when viewed from the top. Pin 3 is omitted. 4. Minimum metal to metal spacing at the package body for the omitted lead location is.137 inch (3.48 mm). 5. Lead width measured at package body. 6. and E are referenced datums on the package body..32 (.81).37 (.94).48 (1.22).53 (1.35).9 (.23).4 (.1).12 (.3).4 (.1).36 (.91).44 (1.12) 8 G8 PI

46 TOP eip7 B A 2.43 (1.24).397 (1.8).81 (2.6).77 (1.96).224 (5.69) Ref (8.25).32 (8.13).519 (13.18) Ref..177 (4.5) Ref. Pin #1 I...14 (3.56).12 (3.5).16 (.41) Ref..27 (5.26).187 (4.75).7 (1.78) Ref..5 (1.27) (.41) 6.47 (1.19) A A.33 (.84).11 (.28).1 (2.54) 6.28 (.71).2 M.51 M.118 (3.).1 M.25 M A B FRONT IEW IE IEW BAK IEW 1 Ref. All Around.378 (9.6) Ref..21 (.53).19 (.48).48 (1.22).46 (1.17).19 (.48) Ref..6 (1.52) Ref (.84).28 (.71) 3.16 (.41).11 (.28) Base Metal.12 (.3) Ref..3 (.76) Ref. Notes: 1. imensioning and tolerancing per AME Y14.5M imensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. imensions noted are inclusive of plating thickness. 4. oes not include interlead flash or protrusions. 5. ontrolling dimensions in inches (mm). EN IEW ection A A PI Part Ordering Information TOP 258 P N TL TOPwitch Product Family HX eries Number Package Identifier P Plastic IP8 G Plastic M8 M Plastic IP1 Y Plastic TO227 E Plastic eip7 Pin Finish N Pure Matte Tin (PbFree) (P, G, M, E and Y Packages) Tape & Reel and Other Options Blank tandard onfi gurations TL G Package (1 min/mult.) 46

47 TOP Notes 47

48 Revision Notes ate B ata heet Release 2/8 For the latest updates, visit our website: Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATION MAKE NO WARRANTY HEREIN AN PEIFIALLY ILAIM ALL WARRANTIE INLUING, WITHOUT LIMITATION, THE IMPLIE WARRANTIE OF MERHANTABILITY, FITNE FOR A PARTIULAR PURPOE, AN NONINFRINGEMENT OF THIR PARTY RIGHT. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.. and foreign patents, or potentially by pending U.. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at. Power Integrations grants its customers a license under certain patent rights as set forth at Life upport Policy POWER INTEGRATION PROUT ARE NOT AUTHORIZE FOR UE A RITIAL OMPONENT IN LIFE UPPORT EIE OR YTEM WITHOUT THE EXPRE WRITTEN APPROAL OF THE PREIENT OF POWER INTEGRATION. As used herein: A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifi cant injury or death to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPwitch, Tinywitch, Linkwitch, PAwitch, Peakwitch, Ecomart, lampless, Ehield, Filterfuse, takfet, PI Expert and PI FAT are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. 28, Power Integrations, Inc. Power Integrations Worldwide ales upport Locations World Headquarters 5245 Hellyer Avenue an Jose, A 95138, UA. Main: ustomer ervice: Phone: Fax: [email protected] hina (hanghai) Rm 8788A Pacheer ommercial entre, 555 Nanjing Rd. West hanghai, P.R Phone: Fax: [email protected] hina (henzhen) Rm A, B & 4th Floor, Block, Electronics cience and Technology Bldg., 27 hennan Zhong Rd, henzhen, Guangdong, hina, Phone: Fax: [email protected] Germany Rueckertstrasse , Munich Germany Phone: Fax: [email protected].. India #1, 14th Main Road asanthanagar Bangalore5652 India Phone: Fax: [email protected] Italy ia e Amicis Bresso MI Italy Phone: Fax: [email protected] Japan Kosei ai3 Bldg , hinyokomana, Kohokuku Yokohamashi Kanagwan Japan Phone: Fax: [email protected] Korea RM 62, 6FL Korea ity Air Terminal B/, 1596 amsungong, KangnamGu, eoul, , Korea Phone: Fax: [email protected] ingapore 51 Newton Road #158/1 Goldhill Plaza ingapore, 389 Phone: Fax: [email protected] Taiwan 5F, No. 318, Nei Hu Rd., ec. 1 Nei Hu ist. Taipei, Taiwan 114, R.O.. Phone: Fax: [email protected] Europe HQ 1st Floor, t. James s House East treet, Farnham urrey GU9 7TJ United Kingdom Phone: 44 () Fax: 44 () [email protected] Applications Hotline World Wide Applications Fax World Wide