Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium Processor Family, and Desktop Intel Celeron Processor Family

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1 Deskop 4h Generaon Inel Core, Deskop Inel Penum, and Deskop Inel Celeron Processor Famly Daashee Volume 1 of 2 March 2015 Order No.:

2 You may no use or faclae he use of hs documen n connecon wh any nfrngemen or oher legal analyss concernng Inel producs descrbed heren. You agree o gran Inel a non-exclusve, royaly-free lcense o any paen clam hereafer drafed whch ncludes subjec maer dsclosed heren. No lcense (express or mpled, by esoppel or oherwse) o any nellecual propery rghs s graned by hs documen. All nformaon provded here s subjec o change whou noce. Conac your Inel represenave o oban he laes Inel produc specfcaons and roadmaps. The producs descrbed may conan desgn defecs or errors known as erraa whch may cause he produc o devae from publshed specfcaons. Curren characerzed erraa are avalable on reques. Copes of documens whch have an order number and are referenced n hs documen may be obaned by callng or vs hp:// Inel echnologes feaures and benefs depend on sysem confguraon and may requre enabled hardware, sofware or servce acvaon. Learn more a hp:// or from he OEM or realer. No compuer sysem can be absoluely secure. Inel Hyper-Threadng Technology (Inel HT Technology) s avalable on selec Inel Core processors. I requres an Inel HT Technology enabled sysem. Consul your PC manufacurer. Performance wll vary dependng on he specfc hardware and sofware used. No avalable on Inel Core For more nformaon ncludng deals on whch processors suppor Inel HT Technology, vs hp:// Inel Hgh Defnon Audo (Inel HD Audo) requres an Inel HD Audo enabled sysem. Consul your PC manufacurer for more nformaon. Sound qualy wll depend on equpmen and acual mplemenaon. For more nformaon abou Inel HD Audo, refer o hp:// desgn/chpses/hdaudo.hm. Inel 64 archecure requres a sysem wh a 64-b enabled processor, chpse, IOS and sofware. Performance wll vary dependng on he specfc hardware and sofware you use. Consul your PC manufacurer for more nformaon. For more nformaon, vs hp:// conen/www/us/en/archecure-and-echnology/mcroarchecure/nel-64-archecure-general.hml. Inel Vrualzaon Technology (Inel VT) requres a compuer sysem wh an enabled Inel processor, IOS, and vrual machne monor (VMM). Funconaly, performance or oher benefs wll vary dependng on hardware and sofware confguraons. Sofware applcaons may no be compable wh all operang sysems. Consul your PC manufacurer. For more nformaon, vs hp:// The orgnal equpmen manufacurer mus provde TPM funconaly, whch requres a TPM-suppored IOS. TPM funconaly mus be nalzed and may no be avalable n all counres. For Enhanced Inel SpeedSep Technology, see he Processor Spec Fnder a hp://ark.nel.com/ or conac your Inel represenave for more nformaon. Inel AES-NI requres a compuer sysem wh an AES-NI enabled processor, as well as non-inel sofware o execue he nsrucons n he correc sequence. AES-NI s avalable on selec Inel processors. For avalably, consul your reseller or sysem manufacurer. For more nformaon, see hp://sofware.nel.com/en-us/arcles/nel-advanced-encrypon-sandard-nsrucons-aes-n/. Inel Acve Managemen Technology (Inel AMT) should be used by a knowledgeable IT admnsraor and requres enabled sysems, sofware, acvaon, and connecon o a corporae nework. Inel AMT funconaly on moble sysems may be lmed n some suaons. Your resuls wll depend on your specfc mplemenaon. Learn more by vsng Inel Acve Managemen Technology. No compuer sysem can provde absolue secury under all condons. Inel Trused Execuon Technology (Inel TXT) requres a compuer wh Inel Vrualzaon Technology, an Inel TXT-enabled processor, chpse, IOS, Auhencaed Code Modules and an Inel TXT-compable measured launched envronmen (MLE). Inel TXT also requres he sysem o conan a TPM v1.s. For more nformaon, vs hp:// secury. Requres a sysem wh Inel Turbo oos Technology. Inel Turbo oos Technology and Inel Turbo oos Technology 2.0 are only avalable on selec Inel processors. Consul your PC manufacurer. Performance vares dependng on hardware, sofware, and sysem confguraon. For more nformaon, vs hps://www-ssl.nel.com/conen/www/us/en/archecure-and-echnology/urbo-boos/urbo-boos-echnology.hml. Inel Advanced Vecor Exensons (Inel AVX) are desgned o acheve hgher hroughpu o ceran neger and floang pon operaons. Due o varyng processor power characerscs, ulzng AVX nsrucons may cause a) some pars o operae a less han he raed frequency and b) some pars wh Inel Turbo oos Technology 2.0 o no acheve any or maxmum urbo frequences. Performance vares dependng on hardware, sofware, and sysem confguraon and you should consul your sysem manufacurer for more nformaon. Inel Advanced Vecor Exensons refers o Inel AVX, Inel AVX2 or Inel AVX-512. For more nformaon on Inel Turbo oos Technology 2.0, vs hps://www-ssl.nel.com/conen/www/us/en/ archecure-and-echnology/urbo-boos/urbo-boos-echnology.hml Inel, Inel Core, Celeron, Penum, Inel SpeedSep, and he Inel logo are rademarks of Inel Corporaon n he U.S. and/or oher counres. *Oher names and brands may be clamed as he propery of ohers. Copyrgh , Inel Corporaon. All rghs reserved. Daashee Volume 1 of 2 March Order No.:

3 Conens Processor Conens Revson Hsory Inroducon Suppored Technologes Inerfaces Power Managemen Suppor Thermal Managemen Suppor Package Suppor Termnology Relaed Documens Inerfaces Sysem Memory Inerface Sysem Memory Technology Suppored Sysem Memory Tmng Suppor Sysem Memory Organzaon Modes PCI Express* Inerface PCI Express* Suppor PCI Express* Archecure PCI Express* Confguraon Mechansm Drec Meda Inerface (DMI) Processor Graphcs Processor Graphcs Conroller (GT) D and Vdeo Engnes for Graphcs Processng Mul Graphcs Conrollers Mul-Monor Suppor Dgal Dsplay Inerface (DDI) Inel Flexble Dsplay Inerface (Inel FDI) Plaform Envronmenal Conrol Inerface (PECI) PECI us Archecure Technologes Inel Vrualzaon Technology (Inel VT) Inel Trused Execuon Technology (Inel TXT) Inel Hyper-Threadng Technology (Inel HT Technology) Inel Turbo oos Technology Inel Advanced Vecor Exensons 2.0 (Inel AVX2) Inel Advanced Encrypon Sandard New Insrucons (Inel AES-NI) Inel Transaconal Synchronzaon Exensons - New Insrucons (Inel TSX-NI) Inel 64 Archecure x2apic Power Aware Inerrup Roung (PAIR) Execue Dsable Supervsor Mode Execuon Proecon (SMEP) Power Managemen Advanced Confguraon and Power Inerface (ACPI) Saes Suppored Processor Core Power Managemen Enhanced Inel SpeedSep Technology Key Feaures Low-Power Idle Saes March 2015 Daashee Volume 1 of 2 Order No.:

4 Processor Conens Requesng Low-Power Idle Saes Core C-Sae Rules Package C-Saes Package C-Saes and Dsplay Resoluons Inegraed Memory Conroller (IMC) Power Managemen Dsablng Unused Sysem Memory Oupus DRAM Power Managemen and Inalzaon DRAM Runnng Average Power Lmaon (RAPL) DDR Elecrcal Power Gang (EPG) PCI Express* Power Managemen Drec Meda Inerface (DMI) Power Managemen Graphcs Power Managemen Inel Rapd Memory Power Managemen (Inel RMPM) Graphcs Render C-Sae Inel Graphcs Dynamc Frequency Thermal Managemen Deskop Processor Thermal Profles Processor (PCG 2013D and PCG 2014) Thermal Profle Processor (PCG 2013C) Thermal Profle Processor (PCG 2013) Thermal Profle Processor (PCG 2013A) Thermal Profle Thermal Merology Fan Speed Conrol Scheme wh Dgal Thermal Sensor (DTS) Fan Speed Conrol Scheme wh Dgal Thermal Sensor (DTS) Thermal Specfcaons Processor Temperaure Adapve Thermal Monor THERMTRIP# Sgnal Dgal Thermal Sensor Dgal Thermal Sensor Accuracy (Taccuracy) Inel Turbo oos Technology Thermal Consderaons Inel Turbo oos Technology Power Conrol and Reporng Package Power Conrol Turbo Tme Parameer Sgnal Descrpon Sysem Memory Inerface Sgnals Memory Reference Compensaon Sgnals Rese and Mscellaneous Sgnals PCI Express* Inerface Sgnals Dsplay Inerface Sgnals Drec Meda Inerface (DMI) Phase Locked Loop (PLL) Sgnals Tesably Sgnals Error and Thermal Proecon Sgnals Power Sequencng Sgnals Processor Power Sgnals Sense Sgnals Ground and Non-Crcal o Funcon (NCTF) Sgnals Processor Inernal Pull-Up / Pull-Down Termnaons Daashee Volume 1 of 2 March Order No.:

5 Conens Processor 7.0 Elecrcal Specfcaons Inegraed Volage Regulaor Power and Ground Lands V CC Volage Idenfcaon (VID) Reserved or Unused Sgnals Sgnal Groups Tes Access Por (TAP) Connecon DC Specfcaons Volage and Curren Specfcaons Plaform Envronmen Conrol Inerface (PECI) DC Characerscs Inpu Devce Hyseress Package Mechancal Specfcaons Processor Componen Keep-Ou Zone Package Loadng Specfcaons Package Handlng Gudelnes Package Inseron Specfcaons Processor Mass Specfcaon Processor Maerals Processor Markngs Processor Land Coordnaes Processor Sorage Specfcaons Processor all and Sgnal Informaon March 2015 Daashee Volume 1 of 2 Order No.:

6 Processor Fgures Fgures 1 Plaform lock Dagram Inel Flex Memory Technology Operaons PCI Express* Relaed Regser Srucures n he Processor PCI Express* Typcal Operaon 16 Lanes Mappng Processor Graphcs Conroller Un lock Dagram Processor Dsplay Archecure DsplayPor* Overvew HDMI* Overvew PECI Hos-Clens Connecon Example Devce o Doman Mappng Srucures Processor Power Saes Idle Power Managemen reakdown of he Processor Cores Thread and Core C-Sae Enry and Ex Package C-Sae Enry and Ex Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013D and PCG 2014) Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013C) Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013) Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013A) Thermal Tes Vehcle (TTV) Case Temperaure (T CASE ) Measuremen Locaon Dgal Thermal Sensor (DTS) 1.1 Defnon Pons Dgal Thermal Sensor (DTS) Thermal Profle Defnon Package Power Conrol Inpu Devce Hyseress Processor Package Assembly Skech Processor Top-Sde Markngs Processor Package Land Coordnaes Processor Package Land/Pn Sde Componens Daashee Volume 1 of 2 March Order No.:

7 Tables Processor Tables 1 Termnology Relaed Documens Processor DIMM Suppor by Produc Suppored UDIMM Module Confguraons Suppored SO-DIMM Module Confguraons (AIO Only) DDR3 / DDR3L Sysem Memory Tmng Suppor PCI Express* Suppored Confguraons n Deskop Producs Processor Suppored Audo Formas over HDMI*and DsplayPor* Vald Three Dsplay Confguraons hrough he Processor DsplayPor and embedded DsplayPor* Resoluons for 1, 2, 4 Lanes Lnk Daa Rae of RR, HR, and HR Sysem Saes Processor Core / Package Sae Suppor Inegraed Memory Conroller Saes PCI Express* Lnk Saes Drec Meda Inerface (DMI) Saes G, S, and C Inerface Sae Combnaons D, S, and C Inerface Sae Combnaon Coordnaon of Thread Power Saes a he Core Level Coordnaon of Core Power Saes a he Package Level Deepes Package C-Sae Avalable Deskop Processor Thermal Specfcaons Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013D and PCG 2014) Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013C) Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013) Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013A) Dgal Thermal Sensor (DTS) 1.1 Thermal Soluon Performance Above T CONTROL Thermal Margn Slope oundary Condons, Performance Targes, and T CASE Specfcaons Inel Turbo oos Technology 2.0 Package Power Conrol Sengs Sgnal Descrpon uffer Types Memory Channel A Sgnals Memory Channel Sgnals Memory Reference and Compensaon Sgnals Rese and Mscellaneous Sgnals PCI Express* Graphcs Inerface Sgnals Dsplay Inerface Sgnals Drec Meda Inerface (DMI) Processor o PCH Seral Inerface Phase Locked Loop (PLL) Sgnals Tesably Sgnals Error and Thermal Proecon Sgnals Power Sequencng Sgnals Processor Power Sgnals Sense Sgnals Ground and Non-Crcal o Funcon (NCTF) Sgnals Processor Inernal Pull-Up / Pull-Down Termnaons Volage Regulaor (VR) 12.5 Volage Idenfcaon Sgnal Groups Processor Core Acve and Idle Mode DC Volage and Curren Specfcaons Memory Conroller (V DDQ ) Supply DC Volage and Curren Specfcaons IO_OUT, VCOMP_OUT, and IO_TERM DDR3 / DDR3L Sgnal Group DC Specfcaons Dgal Dsplay Inerface Group DC Specfcaons embedded DsplayPor* (edp*) Group DC Specfcaons March 2015 Daashee Volume 1 of 2 Order No.:

8 Processor Tables 54 CMOS Sgnal Group DC Specfcaons GTL Sgnal Group and Open Dran Sgnal Group DC Specfcaons PCI Express* DC Specfcaons Plaform Envronmen Conrol Inerface (PECI) DC Elecrcal Lms Processor Loadng Specfcaons Package Handlng Gudelnes Processor Maerals Processor Sorage Specfcaons Processor all Ls by Sgnal Name Daashee Volume 1 of 2 March Order No.:

9 Revson Hsory Processor Revson Hsory Revson Descrpon Dae 001 Inal Release June Added Deskop 4h Generaon Inel Core , , S, , , T, , and T processors Added Deskop Inel Penum G3430, G3420, G3220, G3420T, G3220T processors Updaed Secon 4.2.4, Core C-Sae Rules Updaed Secon 4.2.5, Package C-Saes Mnor eds hroughou for clary Sepember Mnor eds hroughou for clary November Added Deskop Inel Celeron G1830, G1820, and G1820T processors Added Secon 4.2.6, "Package C-Saes and Dsplay Resoluons" December Updaed Table 39, "Tesably Sgnals" March Added Deskop 4h Generaon Inel Core , S, T, T, , S, T, , S, T, , S, T, , , T, , T processors Added Deskop Inel Penum G3450, G3440, G3440T, G3240, G3240T processors Added Deskop Inel Celeron G1850, G1840, G1840T processors Added Secon 5.5, Thermal Specfcaons Added Deskop 4h Generaon Inel Core K, K processors Added Deskop Inel Penum G3258 processor Added Deskop 4h Generaon Inel Core , T, , T processors Added Deskop Inel Penum G3460, G3450T, G3250, G3250T processor Added PCG 2014 Updaed Table 21, Deskop Processor Thermal Specfcaons Updaed Table 26, Dgal Thermal Sensor (DTS) 1.1 Thermal Soluon Performance Above T CONTROL Updaed Table 27, Thermal Margn Slope. Updaed Table 28, oundary Condons, Performance Tages, and T CASE Specfcaons. Updaed Table 48, Processor Core Acve and Idle Mode DC Volage and Curren Specfcaons. Added Fgure 27, 2014 Processor Package Land/Pn Sde Componens. Added Deskop 4h Generaon Inel Core T, , T processors Added Deskop Inel Penum G3470, G3460T, G3260, G3260T processor May 2014 June 2014 July 2014 July 2014 March 2015 March 2015 Daashee Volume 1 of 2 Order No.:

10 Processor Inroducon 1.0 Inroducon The Deskop 4h Generaon Inel Core processor famly, Deskop Inel Penum processor famly, and Deskop Inel Celeron processor famly are 64-b, mul-core processors bul on 22-nanomeer process echnology. The processors are desgned for a wo-chp plaform conssng of a processor and Plaform Conroller Hub (PCH). The processors are desgned o be used wh he Inel 8 Seres chpse. See he followng fgure for an example plaform block dagram. Throughou hs documen, he Deskop 4h Generaon Inel Core processor famly, Deskop Inel Penum processor famly, and Deskop Inel Celeron processor famly may be referred o smply as "processor". Throughou hs documen, he Deskop 4h Generaon Inel Core processor famly refers o he Deskop 4h Generaon Inel Core , S, T, K, T, , R, K, , S, T, T, , S, T, K, R, K, , S, T, R, , S, T, R, S, T, , , S, T, , S, , S, , T, , T, , T, , , T, , T, , , T, T, , and T processors. Throughou hs documen, he Deskop Inel Penum processor famly refers o he Inel Penum G3470, G3460, G3460T, G3450, G3450T, G3440, G3440T, G3430, G3420, G3420T, G3258, G3260, G3260T, G3250, G3250T, G3240, G3240T, G3220, and G3220T processors. Throughou hs documen, he Deskop Inel Celeron processor famly refers o he Inel Celeron G1850, G1840, G1840T, G1830, G1820, and G1820T processors. Noe: Some processor feaures are no avalable on all plaforms. Refer o he processor Specfcaon Updae documen for deals. Daashee Volume 1 of 2 March Order No.:

11 Inroducon Processor Fgure 1. Plaform lock Dagram PCI Express* DIMMs / CH Dgal Dsplay Inerface (DDI) (3 nerfaces) Processor CH A CH Sysem Memory Inel Flexble Dsplay Inerface (Inel FDI) (x2) Drec Meda Inerface 2.0 (DMI 2.0) (x4) US 3.0 (up o 6 Pors) Analog Dsplay (VGA) US 2.0 (8 Pors) SATA, 6 G/s (up o 6 Pors) Plaform Conroller Hub (PCH) Inegraed LAN PCI Express* 2.0 (up o 8 Pors) SPI Flash SPI Inel Hgh Defnon Audo (Inel HD Audo) Trused Plaform Module (TPM) 1.2 Super IO / EC LPC GPIOs SMus Suppored Technologes Inel Vrualzaon Technology (Inel VT) Inel Acve Managemen Technology 9.5 (Inel AMT 9.5 ) Inel Trused Execuon Technology (Inel TXT) Inel Sreamng SIMD Exensons 4.2 (Inel SSE4.2) Inel Hyper-Threadng Technology (Inel HT Technology) Inel 64 Archecure Execue Dsable Inel Turbo oos Technology 2.0 March 2015 Daashee Volume 1 of 2 Order No.:

12 Processor Inroducon Inel Advanced Vecor Exensons 2.0 (Inel AVX2) Inel Advanced Encrypon Sandard New Insrucons (Inel AES-NI) PCLMULQDQ Insrucon Inel Secure Key Inel Transaconal Synchronzaon Exensons - New Insrucons (Inel TSX- NI) PAIR Power Aware Inerrup Roung SMEP Supervsor Mode Execuon Proecon Enhanced Inel Speedsep Technology Noe: 1.2 The avalably of he feaures may vary beween processor SKUs. Inerfaces The processor suppors he followng nerfaces: DDR3/DDR3L Drec Meda Inerface (DMI) Dgal Dsplay Inerface (DDI) PCI Express* 1.3 Power Managemen Suppor Processor Core Full suppor of ACPI C-saes as mplemened by he followng processor C-saes: C0, C1, C1E, C3, C6, C7 Enhanced Inel SpeedSep Technology Sysem S0, S3, S4, S5 Memory Conroller Condonal self-refresh Dynamc power-down PCI Express* L0s and L1 ASPM power managemen capably DMI L0s and L1 ASPM power managemen capably Processor Graphcs Conroller Inel Rapd Memory Power Managemen (Inel RMPM) Inel Smar 2D Dsplay Technology (Inel S2DDT) Graphcs Render C-sae (RC6) Daashee Volume 1 of 2 March Order No.:

13 Inroducon Processor Inel Seamless Dsplay Refresh Rae Swchng wh edp por Inel Dsplay Power Savng Technology (Inel DPST) 1.4 Thermal Managemen Suppor Dgal Thermal Sensor Adapve Thermal Monor THERMTRIP# and PROCHOT# suppor On-Demand Mode Memory Open and Closed Loop Throlng Memory Thermal Throlng Exernal Thermal Sensor (TS-on-DIMM and TS-on-oard) Render Thermal Throlng Fan speed conrol wh DTS 1.5 Package Suppor The processor socke ype s noed as LGA1150. The package s a 37.5 x 37.5 mm Flp Chp Land Grd Array (FCLGA 1150). See he approprae Processor Thermal Mechancal Desgn Gudelnes and LGA1150 Socke Applcaon Gude for complee deals on he package. 1.6 Table 1. Termnology Termnology Term Descrpon APD /D/F GA LC LT PP CKE CLTM DDI DDR3 DLL DMA DMI DP DTS Acve Power-down us/devce/funcon all Grd Array acklgh Compensaon lock Level Transfer s per pxel Clock Enable Closed Loop Thermal Managemen Dgal Dsplay Inerface Thrd-generaon Double Daa Rae SDRAM memory echnology Delay-Locked Loop Drec Memory Access Drec Meda Inerface DsplayPor* Dgal Thermal Sensor connued... March 2015 Daashee Volume 1 of 2 Order No.:

14 Processor Inroducon Term Descrpon DVI* EC ECC edp* EPG EU FMA FSC HDCP HDMI* HFM DCT IHS GFX GSA GUI IMC Inel 64 Technology Inel DPST Inel FDI Inel TSX-NI Inel TXT Inel VT Inel VT-d IOV ISI ITPM LCD LFM LFP LPDDR3 Dgal Vsual Inerface. DVI* s he nerface specfed by he DDWG (Dgal Dsplay Workng Group) Embedded Conroller Error Correcon Code embedded DsplayPor* Elecrcal Power Gang Execuon Un Floang-pon fused Mulply Add nsrucons Fan Speed Conrol Hgh-bandwdh Dgal Conen Proecon Hgh Defnon Mulmeda Inerface Hgh Frequency Mode Inverse Dscree Cosne Transform Inegraed Hea Spreader Graphcs Graphcs n Sysem Agen Graphcal User Inerface Inegraed Memory Conroller 64-b memory exensons o he IA-32 archecure Inel Dsplay Power Savng Technology Inel Flexble Dsplay Inerface Inel Transaconal Synchronzaon Exensons - New Insrucons Inel Trused Execuon Technology Inel Vrualzaon Technology. Processor vrualzaon, when used n conjuncon wh Vrual Machne Monor sofware, enables mulple, robus ndependen sofware envronmens nsde a sngle plaform. Inel Vrualzaon Technology (Inel VT) for Dreced I/O. Inel VT-d s a hardware asss, under sysem sofware (Vrual Machne Manager or OS) conrol, for enablng I/O devce vrualzaon. Inel VT-d also brngs robus secury by provdng proecon from erran DMAs by usng DMA remappng, a key feaure of Inel VT-d. I/O Vrualzaon Iner-Symbol Inerference Inegraed Trused Plaform Module Lqud Crysal Dsplay Low Frequency Mode. LFM s Pn n he P-sae able. I can be read a MSR CEh [47:40]. Local Fla Panel Low-Power Thrd-generaon Double Daa Rae SDRAM memory echnology MCP Mul-Chp Package connued... Daashee Volume 1 of 2 March Order No.:

15 Inroducon Processor Term Descrpon MFM MLE MLC MSI MSL MSR NCTF ODT OLTM PCG PCH PECI Ψ ca PEG Mnmum Frequency Mode. MFM s he mnmum rao suppored by he processor and can be read from MSR CEh [55:48]. Measured Launched Envronmen Md-Level Cache Message Sgnaled Inerrup Mosure Sensve Labelng Model Specfc Regsers Non-Crcal o Funcon. NCTF locaons are ypcally redundan ground or non-crcal reserved, so he loss of he solder jon connuy a end of lfe condons wll no affec he overall produc funconaly. On-De Termnaon Open Loop Thermal Managemen Plaform Compably Gude (PCG) (prevously known as FM) provdes a desgn arge for meeng all planned processor frequency requremens. Plaform Conroller Hub. The chpse wh cenralzed plaform capables ncludng he man I/O nerfaces along wh dsplay connecvy, audo feaures, power managemen, manageably, secury, and sorage feaures. The Plaform Envronmen Conrol Inerface (PECI) s a one-wre nerface ha provdes a communcaon channel beween Inel processor and chpse componens o exernal monorng devces. Case-o-amben hermal characerzaon parameer (ps). A measure of hermal soluon performance usng oal package power. Defned as (T CASE - T LA ) / Toal Package Power. PCI Express* Graphcs. Exernal Graphcs usng PCI Express* Archecure. I s a hgh-speed seral nerface where confguraon s sofware compable wh he exsng PCI specfcaons. PL1, PL2 Power Lm 1 and Power Lm 2 PPD Processor Processor Core Processor Graphcs Rank SCI SF SMM SMX Sorage Condons Pre-charge Power-down The 64-b mul-core componen (package) The erm processor core refers o S de self, whch can conan mulple execuon cores. Each execuon core has an nsrucon cache, daa cache, and 256-K L2 cache. All execuon cores share he L3 cache. Inel Processor Graphcs A un of DRAM correspondng o four o egh devces n parallel, gnorng ECC. These devces are usually, bu no always, mouned on a sngle sde of a SO-DIMM. Sysem Conrol Inerrup. SCI s used n he ACPI proocol. Srps and Fans Sysem Managemen Mode Safer Mode Exensons A non-operaonal sae. The processor may be nsalled n a plaform, n a ray, or loose. Processors may be sealed n packagng or exposed o free ar. Under hese condons, processor landngs should no be conneced o any supply volages, have any I/Os based, or receve any clocks. Upon exposure o free ar (ha s, unsealed packagng or a devce removed from packagng maeral), he processor mus be handled n accordance wh mosure sensvy labelng (MSL) as ndcaed on he packagng maeral. connued... March 2015 Daashee Volume 1 of 2 Order No.:

16 Processor Inroducon Term Descrpon SVID TAC TAP T CASE TCC T CONTROL TDP TL TTV TM V CC V DDQ VF VID VS VLD VMM VR V SS x1 x2 x4 x8 x16 Seral Volage Idenfcaon Thermal Averagng Consan Tes Access Pon The case emperaure of he processor, measured a he geomerc cener of he opsde of he TTV IHS. Thermal Conrol Crcu T CONTROL s a sac value ha s below he TCC acvaon emperaure and used as a rgger pon for fan speed conrol. When DTS > T CONTROL, he processor mus comply o he TTV hermal profle. Thermal Desgn Power: Thermal soluon should be desgned o dsspae hs arge power level. TDP s no he maxmum power ha he processor can dsspae. Translaon Look-asde uffer Thermal Tes Vehcle. A mechancally equvalen package ha conans a ressve heaer n he de o evaluae hermal soluons. Thermal Monor. A power reducon feaure desgned o decrease emperaure afer he processor has reached s maxmum operang emperaure. Processor core power supply DDR3/DDR3L power supply. Verex Fech Volage Idenfcaon Verex Shader Varable Lengh Decodng Vrual Machne Monor Volage Regulaor Processor ground Refers o a Lnk or Por wh one Physcal Lane Refers o a Lnk or Por wh wo Physcal Lanes Refers o a Lnk or Por wh four Physcal Lanes Refers o a Lnk or Por wh egh Physcal Lanes Refers o a Lnk or Por wh sxeen Physcal Lanes 1.7 Table 2. Relaed Documens Relaed Documens Documen Deskop 4h Generaon Inel Core, Deskop Inel Penum, and Deskop Inel Celeron Daashee, Volume 2 of 2 Deskop 4h Generaon Inel Core, Deskop Inel Penum, and Deskop Inel Celeron Specfcaon Updae Documen Number / Locaon connued... Daashee Volume 1 of 2 March Order No.:

17 Inroducon Processor Documen Deskop 4h Generaon Inel Core, Deskop Inel Penum, Deskop Inel Celeron, and Inel Xeon Processor E v3 Produc Famly Thermal Mechancal Desgn Gudelnes Documen Number / Locaon LGA1150 Socke Applcaon Gude Inel 8 Seres / C220 Seres Chpse Famly Plaform Conroller Hub (PCH) Daashee Inel 8 Seres / C220 Seres Chpse Famly Plaform Conroller Hub (PCH) Specfcaon Updae Inel 8 Seres / C220 Seres Chpse Famly Plaform Conroller Hub (PCH) Thermal Mechancal Specfcaons and Desgn Gudelnes Inel 9 Seres Chpse Famly Plaform Conroller Hub (PCH) Daashee Inel 9 Seres Chpse Famly Plaform Conroller Hub (PCH) Specfcaon Updae Inel 9 Seres Chpse Famly Plaform Conroller Hub (PCH) Thermal Mechancal Specfcaons and Desgn Gudelnes Advanced Confguraon and Power Inerface 3.0 PCI Local us Specfcaon 3.0 PCI Express ase Specfcaon, Revson 2.0 DDR3 SDRAM Specfcaon DsplayPor* Specfcaon Inel 64 and IA-32 Archecures Sofware Developer's Manuals hp:// hp:// specfcaons hp:// hp:// hp:// hp:// producs/processor/ manuals/ndex.hm March 2015 Daashee Volume 1 of 2 Order No.:

18 Processor Inerfaces 2.0 Inerfaces 2.1 Sysem Memory Inerface Two channels of DDR3/DDR3L Unbuffered Dual In-Lne Memory Modules (UDIMM) or DDR3/DDR3L Unbuffered Small Oulne Dual In-Lne Memory Modules (SO- DIMM) wh a maxmum of wo DIMMs per channel. Sngle-channel and dual-channel memory organzaon modes Daa burs lengh of egh for all memory organzaon modes Memory daa ransfer raes of 1333 MT/s and 1600 MT/s 64-b wde channels DDR3/DDR3L I/O Volage of 1.5 V for Deskop The ype of he DIMM modules suppored by he processor s dependen on he PCH SKU n he arge plaform: Deskop PCH plaforms suppor non-ecc UDIMMs only All In One plaforms (AIO) suppor SO-DIMMs Theorecal maxmum memory bandwdh of: 21.3 G/s n dual-channel mode assumng 1333 MT/s 25.6 G/s n dual-channel mode assumng 1600 MT/s 1Gb, 2Gb, and 4Gb DDR3/DDR3L DRAM devce echnologes are suppored Usng 4Gb DRAM devce echnologes, he larges sysem memory capacy possble s 32 G, assumng Dual Channel Mode wh four x8 dual ranked DIMM memory confguraon Up o 64 smulaneous open pages, 32 per channel (assumng 8 ranks of 8 bank devces) Processor on-de VREF generaon for DDR DQ Read and Wre as well as CMD/ADD Command launch modes of 1n/2n On-De Termnaon (ODT) Asynchronous ODT Inel Fas Memory Access (Inel FMA): Jus-n-Tme Command Schedulng Command Overlap Ou-of-Order Schedulng Daashee Volume 1 of 2 March Order No.:

19 Inerfaces Processor Sysem Memory Technology Suppored The Inegraed Memory Conroller (IMC) suppors DDR3/DDR3L proocols wh wo ndependen, 64-b wde channels each accessng one or wo DIMMs. The ype of memory suppored by he processor s dependen on he PCH SKU n he arge plaform. Noe: Noe: Table 3. The IMC suppors a maxmum of wo DDR3/DDR3L DIMMs per channel; hus, allowng up o four devce ranks per channel. The suppor of DDR3/DDR3L frequences and number of DIMMs per channel s SKU dependen. Processor DIMM Suppor by Produc Processor Cores Package DIMM per Channel DDR3 / DDR3L Dual Core Quad Core ulga ulga 1 DPC 1333/ DPC 1333/ DPC 1333/ DPC 1333/1600 DDR3/DDR3L Daa Transfer Raes: 1333 MT/s (PC ) 1600 MT/s (PC ) AIO plaform DDR3/DDR3L SO-DIMM Modules: Raw Card Sngle Ranked x8 unbuffered non-ecc Raw Card F Dual Ranked x8 (planar) unbuffered non-ecc Deskop plaform UDIMM Modules: Raw Card A Sngle Ranked x8 unbuffered non-ecc Raw Card Dual Ranked x8 unbuffered non-ecc Sandard 1Gb, 2Gb, and 4Gb echnologes and addressng are suppored for x8 devces. There s no suppor for memory modules wh dfferen echnologes or capaces on oppose sdes of he same memory module. If one sde of a memory module s populaed, he oher sde s eher dencal or empy. Table 4. Suppored UDIMM Module Confguraons Raw Card Verson DIMM Capacy DRAM Devce Technology DRAM Organzaon # of DRAM Devces # of Physcal Devces Ranks # of Row / Col Address s # of anks Insde DRAM Page Sze Deskop Plaforms Unbuffered / Non-ECC Suppored DIMM Module Confguraons A 1 G 1 Gb 128 M X /10 8 8K connued... March 2015 Daashee Volume 1 of 2 Order No.:

20 Processor Inerfaces Raw Card Verson DIMM Capacy DRAM Devce Technology DRAM Organzaon # of DRAM Devces # of Physcal Devces Ranks # of Row / Col Address s # of anks Insde DRAM Page Sze 2 G 1 Gb 128 M X /10 8 8K 4 G 2 Gb 256 M X /10 8 8K 4 G 4 Gb 512 M X /10 8 8K 8 G 4 Gb 512 M X /10 8 8K Noe: Table 5. DIMM module suppor s based on avalably and s subjec o change. Suppored SO-DIMM Module Confguraons (AIO Only) Raw Card Verson DIMM Capacy DRAM Organzaon # of DRAM Devces # of Row/Col Address s # of anks Insde DRAM Page Sze 1 G 128 M x /10 8 8K 2 G 256 M x /10 8 8K 4 G 512 M x /10 8 8K 2 G 128 M x /10 8 8K F 4 G 256 M x /10 8 8K 8 G 512 M x /10 8 8K Noe: Sysem memory confguraons are based on avalably and are subjec o change. Sysem Memory Tmng Suppor The IMC suppors he followng DDR3/DDR3L Speed n, CAS Wre Laency (CWL), and command sgnal mode mngs on he man memory nerface: CL = CAS Laency RCD = Acvae Command o READ or WRITE Command delay RP = PRECHARGE Command Perod CWL = CAS Wre Laency Command Sgnal modes = 1N ndcaes a new command may be ssued every clock and 2N ndcaes a new command may be ssued every 2 clocks. Command launch mode programmng depends on he ransfer rae and memory confguraon. Table 6. DDR3 / DDR3L Sysem Memory Tmng Suppor Segmen Transfer Rae (MT/s) CL (CK) RCD (CK) RP (CK) CWL (CK) DPC CMD Mode All segmens /9 8/9 8/ /11 10/11 10/ N/2N 2 2N 1 1N/2N 2 2N Daashee Volume 1 of 2 March Order No.:

21 Inerfaces Processor Noe: Sysem memory mng suppor s based on avalably and s subjec o change. Sysem Memory Organzaon Modes The Inegraed Memory Conroller (IMC) suppors wo memory organzaon modes sngle-channel and dual-channel. Dependng upon how he DIMM Modules are populaed n each memory channel, a number of dfferen confguraons can exs. Sngle-Channel Mode In hs mode, all memory cycles are dreced o a sngle-channel. Sngle-channel mode s used when eher Channel A or Channel DIMM connecors are populaed n any order, bu no boh. Dual-Channel Mode Inel Flex Memory Technology Mode The IMC suppors Inel Flex Memory Technology Mode. Memory s dvded no symmerc and asymmerc zones. The symmerc zone sars a he lowes address n each channel and s conguous unl he asymmerc zone begns or unl he op address of he channel wh he smaller capacy s reached. In hs mode, he sysem runs wh one zone of dual-channel mode and one zone of sngle-channel mode, smulaneously, across he whole memory array. Noe: Fgure 2. Channels A and can be mapped for physcal channel 0 and 1 respecvely or vce versa; however, channel A sze mus be greaer or equal o channel sze. Inel Flex Memory Technology Operaons TOM C Non nerleaved access C Dual channel nerleaved access CH A CH CH A and CH can be confgured o be physcal channels 0 or 1 The larges physcal memory amoun of he smaller sze memory module C The remanng physcal memory amoun of he larger sze memory module Dual-Channel Symmerc Mode Dual-Channel Symmerc mode, also known as nerleaved mode, provdes maxmum performance on real world applcaons. Addresses are png-ponged beween he channels afer each cache lne (64-bye boundary). If here are wo requess, and he second reques s o an address on he oppose channel from he frs, ha reques can be sen before daa from he frs reques has reurned. If wo consecuve cache lnes are requesed, boh may be rereved smulaneously, snce hey are ensured o March 2015 Daashee Volume 1 of 2 Order No.:

22 Processor Inerfaces be on oppose channels. Use Dual-Channel Symmerc mode when boh Channel A and Channel DIMM connecors are populaed n any order, wh he oal amoun of memory n each channel beng he same. When boh channels are populaed wh he same memory capacy and he boundary beween he dual channel zone and he sngle channel zone s he op of memory, he IMC operaes compleely n Dual-Channel Symmerc mode. Noe: The DRAM devce echnology and wdh may vary from one channel o he oher. Sysem Memory Frequency In all modes, he frequency of sysem memory s he lowes frequency of all memory modules placed n he sysem, as deermned hrough he SPD regsers on he memory modules. The sysem memory conroller suppors one or wo DIMM connecors per channel. The usage of DIMM modules wh dfferen laences s allowed, bu n ha case, he wors laency (among wo channels) wll be used. For dual-channel modes, boh channels mus have a DIMM connecor populaed and for sngle-channel mode only a sngle channel may have one or boh DIMM connecors populaed. Noe: In a wo-dimm Per Channel (2DPC) layou memory confguraon, he furhes DIMM from he processor of any gven channel mus always be populaed frs. Inel Fas Memory Access (Inel FMA) Technology Enhancemens The followng secons descrbe he Jus-n-Tme Schedulng, Command Overlap, and Ou-of-Order Schedulng Inel FMA echnology enhancemens. Jus-n-Tme Command Schedulng The memory conroller has an advanced command scheduler where all pendng requess are examned smulaneously o deermne he mos effcen reques o be ssued nex. The mos effcen reques s pcked from all pendng requess and ssued o sysem memory Jus-n-Tme o make opmal use of Command Overlappng. Thus, nsead of havng all memory access requess go ndvdually hrough an arbraon mechansm forcng requess o be execued one a a me, he requess can be sared whou nerferng wh he curren reques allowng for concurren ssung of requess. Ths allows for opmzed bandwdh and reduced laency whle mananng approprae command spacng o mee sysem memory proocol. Command Overlap Command Overlap allows he nseron of he DRAM commands beween he Acvae, Pre-charge, and Read/Wre commands normally used, as long as he nsered commands do no affec he currenly execung command. Mulple commands can be ssued n an overlappng manner, ncreasng he effcency of sysem memory proocol. Ou-of-Order Schedulng Whle leveragng he Jus-n-Tme Schedulng and Command Overlap enhancemens, he IMC connuously monors pendng requess o sysem memory for he bes use of bandwdh and reducon of laency. If here are mulple requess o he same open page, hese requess would be launched n a back-o-back manner o make opmum use of he open memory page. Ths ably o reorder requess on he fly allows he IMC o furher reduce laency and ncrease bandwdh effcency. Daashee Volume 1 of 2 March Order No.:

23 Inerfaces Processor Daa Scramblng The sysem memory conroller ncorporaes a Daa Scramblng feaure o mnmze he mpac of excessve d/d on he plaform sysem memory VRs due o successve 1s and 0s on he daa bus. Pas experence has demonsraed ha raffc on he daa bus s no random and can have energy concenraed a specfc specral harmoncs creang hgh d/d, whch s generally lmed by daa paerns ha exce resonance beween he package nducance and on de capacances. As a resul, he sysem memory conroller uses a daa scramblng feaure o creae pseudo-random paerns on he sysem memory daa bus o reduce he mpac of any excessve d/d. 2.2 PCI Express* Inerface Ths secon descrbes he PCI Express* nerface capables of he processor. See he PCI Express ase* Specfcaon 3.0 for deals on PCI Express* PCI Express* Suppor The PCI Express* lanes (PEG[15:0] TX and RX) are fully-complan o he PCI Express ase Specfcaon, Revson 3.0. The processor wh he PCH suppor he confguraons shown n he followng able (may vary dependng on PCH SKUs). Table 7. PCI Express* Suppored Confguraons n Deskop Producs Confguraon Deskop 1x8, 2x4 GFX, I/O 2x8 1x16 GFX, I/O GFX, I/O The por may negoae down o narrower wdhs. Suppor for x16/x8/x4/x2/x1 wdhs for a sngle PCI Express* mode. 2.5 GT/s, 5.0 GT/s and 8 GT/s PCI Express* b raes are suppored. Gen 1 Raw b-rae on he daa pns of 2.5 GT/s, resulng n a real bandwdh per par of 250 M/s gven he 8b/10b encodng used o ransm daa across hs nerface. Ths also does no accoun for packe overhead and lnk manenance. Maxmum heorecal bandwdh on he nerface of 4 G/s n each drecon smulaneously, for an aggregae of 8 G/s when x16 Gen 1. Gen 2 Raw b-rae on he daa pns of 5.0 GT/s, resulng n a real bandwdh per par of 500 M/s gven he 8b/10b encodng used o ransm daa across hs nerface. Ths also does no accoun for packe overhead and lnk manenance. Maxmum heorecal bandwdh on he nerface of 8 G/s n each drecon smulaneously, for an aggregae of 16 G/s when x16 Gen 2. Gen 3 raw b-rae on he daa pns of 8.0 GT/s, resulng n a real bandwdh per par of 984 M/s usng 128b/130b encodng o ransm daa across hs nerface. Ths also does no accoun for packe overhead and lnk manenance. Maxmum heorecal bandwdh on he nerface of 16 G/s n each drecon smulaneously, for an aggregae of 32 G/s when x16 Gen 3. Herarchcal PCI-complan confguraon mechansm for downsream devces. Tradonal PCI syle raffc (asynchronous snooped, PCI orderng). March 2015 Daashee Volume 1 of 2 Order No.:

24 Processor Inerfaces PCI Express* exended confguraon space. The frs 256 byes of confguraon space alases drecly o he PCI Compably confguraon space. The remanng poron of he fxed 4-K block of memory-mapped space above ha (sarng a 100h) s known as exended confguraon space. PCI Express* Enhanced Access Mechansm. Accessng he devce confguraon space n a fla memory mapped fashon. Auomac dscovery, negoaon, and ranng of lnk ou of rese. Tradonal AGP syle raffc (asynchronous non-snooped, PCI-X Relaxed orderng). Peer segmen desnaon posed wre raffc (no peer-o-peer read raffc) n Vrual Channel 0: DMI -> PCI Express* Por 0 64-b downsream address forma, bu he processor never generaes an address above 64 G (s 63:36 wll always be zeros). 64-b upsream address forma, bu he processor responds o upsream read ransacons o addresses above 64 G (addresses where any of s 63:36 are nonzero) wh an Unsuppored Reques response. Upsream wre ransacons o addresses above 64 G wll be dropped. Re-ssues Confguraon cycles ha have been prevously compleed wh he Confguraon Rery saus. PCI Express* reference clock s 100-MHz dfferenal clock. Power Managemen Even (PME) funcons. Dynamc wdh capably. Message Sgnaled Inerrup (MSI and MSI-X) messages. Polary nverson Noe: The processor does no suppor PCI Express* Ho-Plug. PCI Express* Archecure Compably wh he PCI addressng model s mananed o ensure ha all exsng applcaons and drvers operae unchanged. The PCI Express* confguraon uses sandard mechansms as defned n he PCI Plugand-Play specfcaon. The processor PCI Express* pors suppor Gen 3. A 8 GT/s, Gen 3 operaon resuls n wce as much bandwdh per lane as compared o Gen 2 operaon. The 16 lanes PEG can operae a 2.5 GT/s, 5 GT/s, or 8 GT/s. Gen 3 PCI Express* uses a 128b/130b encodng ha s abou 23% more effcen han he 8b/10b encodng used n Gen 1 and Gen 2. The PCI Express* archecure s specfed n hree layers Transacon Layer, Daa Lnk Layer, and Physcal Layer. See he PCI Express ase Specfcaon 3.0 for deals of PCI Express* archecure PCI Express* Confguraon Mechansm The PCI Express* (exernal graphcs) lnk s mapped hrough a PCI-o-PCI brdge srucure. Daashee Volume 1 of 2 March Order No.:

25 Inerfaces Processor Fgure 3. PCI Express* Relaed Regser Srucures n he Processor PCI Express* Devce PEG0 PCI-PCI rdge represenng roo PCI Express pors (Devce 1 and Devce 6) PCI Compable Hos rdge Devce (Devce 0) DMI PCI Express* exends he confguraon space o 4096 byes per-devce/funcon, as compared o 256 byes allowed by he convenonal PCI specfcaon. PCI Express* confguraon space s dvded no a PCI-compable regon (ha consss of he frs 256 byes of a logcal devce's confguraon space) and an exended PCI Express* regon (ha consss of he remanng confguraon space). The PCI-compable regon can be accessed usng eher he mechansms defned n he PCI specfcaon or usng he enhanced PCI Express* confguraon access mechansm descrbed n he PCI Express* Enhanced Confguraon Mechansm secon. The PCI Express* Hos rdge s requred o ranslae he memory-mapped PCI Express* confguraon space accesses from he hos processor o PCI Express* confguraon cycles. To manan compably wh PCI confguraon addressng mechansms, s recommended ha sysem sofware access he enhanced confguraon space usng 32-b operaons (32-b algned) only. See he PCI Express ase Specfcaon for deals of boh he PCI-compable and PCI Express* Enhanced confguraon mechansms and ransacon rules. PCI Express* Por The PCI Express* nerface on he processor s a sngle, 16-lane (x16) por ha can also be confgured a narrower wdhs. The PCI Express* por s beng desgned o be complan wh he PCI Express ase Specfcaon, Revson 3.0. PCI Express* Lanes Connecon The followng fgure demonsraes he PCIe* lane mappng. March 2015 Daashee Volume 1 of 2 Order No.:

26 Processor Inerfaces Fgure 4. PCI Express* Typcal Operaon 16 Lanes Mappng 0 Lane Lane Lane Lane Lane Lane Lane X 16 Conroller Lane 7 Lane 8 Lane Lane X 4 Conroller X 8 Conroller Lane 11 Lane 12 Lane 13 Lane 14 Lane Drec Meda Inerface (DMI) Drec Meda Inerface (DMI) connecs he processor and he PCH. Nex generaon DMI2 s suppored. Noe: Only DMI x4 confguraon s suppored. DMI 2.0 suppor. Complan o Drec Meda Inerface Second Generaon (DMI2). Four lanes n each drecon. Daashee Volume 1 of 2 March Order No.:

27 Inerfaces Processor 5 GT/s pon-o-pon DMI nerface o PCH s suppored. Raw b-rae on he daa pns of 5.0 G/s, resulng n a real bandwdh per par of 500 M/s gven he 8b/10b encodng used o ransm daa across hs nerface. Does no accoun for packe overhead and lnk manenance. Maxmum heorecal bandwdh on nerface of 2 G/s n each drecon smulaneously, for an aggregae of 4 G/s when DMI x4. Shares 100-MHz PCI Express* reference clock. 64-b downsream address forma, bu he processor never generaes an address above 64 G (s 63:36 wll always be zeros). 64-b upsream address forma, bu he processor responds o upsream read ransacons o addresses above 64 G (addresses where any of s 63:36 are nonzero) wh an Unsuppored Reques response. Upsream wre ransacons o addresses above 64 G wll be dropped. Suppors he followng raffc ypes o or from he PCH: DMI -> DRAM DMI -> processor core (Vrual Legacy Wres (VLWs), Resewarn, or MSIs only) Processor core -> DMI APIC and MSI nerrup messagng suppor: Message Sgnaled Inerrup (MSI and MSI-X) messages Downsream SMI, SCI and SERR error ndcaon. Legacy suppor for ISA regme proocol (PHOLD/PHOLDA) requred for parallel por DMA, floppy drve, and LPC bus masers. DC couplng no capacors beween he processor and he PCH. Polary nverson. PCH end-o-end lane reversal across he lnk. Suppors Half Swng low-power/low-volage. DMI Error Flow DMI can only generae SERR n response o errors, never SCI, SMI, MSI, PCI INT, or GPE. Any DMI relaed SERR acvy s assocaed wh Devce 0. DMI Lnk Down The DMI lnk gong down s a faal, unrecoverable error. If he DMI daa lnk goes o daa lnk down, afer he lnk was up, hen he DMI lnk hangs he sysem by no allowng he lnk o reran o preven daa corrupon. Ths lnk behavor s conrolled by he PCH. Downsream ransacons ha had been successfully ransmed across he lnk pror o he lnk gong down may be processed as normal. No compleons from downsream, non-posed ransacons are reurned upsream over he DMI lnk afer a lnk down even. March 2015 Daashee Volume 1 of 2 Order No.:

28 Processor Inerfaces 2.4 Processor Graphcs The processor graphcs conans a generaon 7.5 graphcs core archecure. Ths enables subsanal gans n performance and lower power consumpon over prevous generaons. Up o 20 Execuon Uns are suppored dependng on he processor SKU. Nex Generaon Inel Clear Vdeo Technology HD Suppor s a collecon of vdeo playback and enhancemen feaures ha mprove he end user s vewng experence Encode / ranscode HD conen Playback of hgh defnon conen ncludng lu-ray Dsc* Superor mage qualy wh sharper, more colorful mages Playback of lu-ray* dsc S3D conen usng HDMI (1.4a specfcaon complan wh 3D) DrecX* Vdeo Acceleraon (DXVA) suppor for accelerang vdeo processng Full AVC/VC1/MPEG2 HW Decode Advanced Scheduler 2.0, 1.0, XPDM suppor Wndows* 8, Wndows* 7, OSX, Lnux* operang sysem suppor DrecX* 11.1, DrecX* 11, DrecX* 10.1, DrecX* 10, DrecX* 9 suppor. OpenGL* 4.0, suppor Swchable Graphcs suppor on AIO plaforms wh MxM soluons only 2.5 Processor Graphcs Conroller (GT) The Graphcs Engne Archecure ncludes 3D compue elemens, Mul-forma HW asssed decode/encode ppelne, and Md-Level Cache (MLC) for superor hgh defnon playback, vdeo qualy, and mproved 3D performance and meda. The Dsplay Engne handles delverng he pxels o he screen. GSA (Graphcs n Sysem Agen) s he prmary channel nerface for dsplay memory accesses and PCI-lke raffc n and ou. Daashee Volume 1 of 2 March Order No.:

29 Inerfaces Processor Fgure 5. Processor Graphcs Conroller Un lock Dagram D and Vdeo Engnes for Graphcs Processng The Gen 7.5 3D engne provdes he followng performance and power-managemen enhancemens. 3D Ppelne The 3D graphcs ppelne archecure smulaneously operaes on dfferen prmves or on dfferen porons of he same prmve. All he cores are fully programmable, ncreasng he versaly of he 3D Engne. 3D Engne Execuon Uns Suppors up o 20 EUs.The EUs perform 128-b wde execuon per clock. Suppor SIMD8 nsrucons for verex processng and SIMD16 nsrucons for pxel processng. Verex Fech (VF) Sage The VF sage execues 3DPRIMITIVE commands. Some enhancemens have been ncluded o beer suppor legacy D3D APIs as well as SGI OpenGL*. March 2015 Daashee Volume 1 of 2 Order No.:

30 Processor Inerfaces Verex Shader (VS) Sage The VS sage performs shadng of verces oupu by he VF funcon. The VS un produces an oupu verex reference for every npu verex reference receved from he VF un, n he order receved. Geomery Shader (GS) Sage The GS sage receves npus from he VS sage. Compled applcaon-provded GS programs, specfyng an algorhm o conver he verces of an npu objec no some oupu prmves. For example, a GS shader may conver lnes of a lne srp no polygons represenng a correspondng segmen of a blade of grass cenered on he lne. Or could use adjacency nformaon o deec slhouee edges of rangles and oupu polygons exrudng ou from he edges. Clp Sage The Clp sage performs general processng on ncomng 3D objecs. However, also ncludes specalzed logc o perform a Clp Tes funcon on ncomng objecs. The Clp Tes opmzes generalzed 3D Clppng. The Clp un examnes he poson of ncomng verces, and acceps/rejecs 3D objecs based on s Clp algorhm. Srps and Fans (SF) Sage The SF sage performs seup operaons requred o raserze 3D objecs. The oupus from he SF sage o he Wndower sage conan mplemenaon-specfc nformaon requred for he raserzaon of objecs and also suppors clppng of prmves o some exen. Wndower / IZ (WIZ) Sage The WIZ un performs an early deph es, whch removes falng pxels and elmnaes unnecessary processng overhead. The Wndower uses he parameers provded by he SF un n he objec-specfc raserzaon algorhms. The WIZ un raserzes objecs no he correspondng se of pxels. The Wndower s also capable of performng dherng, whereby he lluson of a hgher resoluon when usng low-bpp channels n color buffers s possble. Color dherng dffuses he sharp color bands seen on smooh-shaded objecs. Vdeo Engne The Vdeo Engne handles he non-3d (meda/vdeo) applcaons. I ncludes suppor for VLD and MPEG2 decode n hardware. 2D Engne The 2D Engne conans LT (lock Level Transfer) funconaly and an exensve se of 2D nsrucons. To ake advanage of he 3D durng engne s funconaly, some LT funcons make use of he 3D renderer. Processor Graphcs VGA Regsers The 2D regsers consss of orgnal VGA regsers and ohers o suppor graphcs modes ha have color dephs, resoluons, and hardware acceleraon feaures ha go beyond he orgnal VGA sandard. Daashee Volume 1 of 2 March Order No.:

31 Inerfaces Processor Logcal 128- Fxed LT and 256 Fll Engne Ths LT engne acceleraes he GUI of Mcrosof Wndows* operang sysems. The 128-b LT engne provdes hardware acceleraon of block ransfers of pxel daa for many common Wndows operaons. The LT engne can be used for he followng: Move recangular blocks of daa beween memory locaons Daa algnmen To perform logcal operaons (raser ops) The recangular block of daa does no change, as s ransferred beween memory locaons. The allowable memory ransfers are beween: cacheable sysem memory and frame buffer memory, frame buffer memory and frame buffer memory, and whn sysem memory. Daa o be ransferred can conss of regons of memory, paerns, or sold color flls. A paern s always 8 x 8 pxels wde and may be 8, 16, or 32 bs per pxel. The LT engne expands monochrome daa no a color deph of 8, 16, or 32 bs. LTs can be eher opaque or ransparen. Opaque ransfers move he daa specfed o he desnaon. Transparen ransfers compare desnaon color o source color and wre accordng o he mode of ransparency seleced. Daa s horzonally and vercally algned a he desnaon. If he desnaon for he LT overlaps wh he source memory locaon, he LT engne specfes whch area n memory o begn he LT ransfer. Hardware s ncluded for all 256 raser operaons (source, paern, and desnaon) defned by Mcrosof*, ncludng ransparen LT. The LT engne has nsrucons o nvoke LT and srech LT operaons, permng sofware o se up nsrucon buffers and use bach processng. The LT engne can perform hardware clppng durng LTs Mul Graphcs Conrollers Mul-Monor Suppor The processor suppors smulaneous use of he Processor Graphcs Conroller (GT) and a x16 PCI Express* Graphcs (PEG) devce. The processor suppors a maxmum of 2 dsplays conneced o he PEG card n parallel wh up o 2 dsplays conneced o he processor and PCH. Noe: 2.6 When supporng Mul Graphcs Mul Monors, "drag and drop" beween monors and he 2x8PEG s no suppored. Dgal Dsplay Inerface (DDI) The processor suppors: Three Dgal Dsplay (x4 DDI) nerfaces ha can be confgured as DsplayPor*, HDMI*, or DVI. DsplayPor* can be confgured o use 1, 2, or 4 lanes dependng on he bandwdh requremens and lnk daa rae of RR (1.62 GT/s), HR (2.7 GT/s) and HR2 (5.4 GT/s). When confgured as HDMI*, DDIx4 por can suppor 2.97 GT/s. In addon, Dgal Por D ( x4 DDI) nerface can also be confgured o carry embedded DsplayPor* (edpx4). ul-n dsplays are only suppored on Dgal Por D. One dedcaed Inel FDI Por for legacy VGA suppor on he PCH. March 2015 Daashee Volume 1 of 2 Order No.:

32 Memory \ Confg Inerface Panel Fng Por Mux DDI Pors, C, and D PCH Dsplay Processor Inerfaces The HDMI* nerface suppors HDMI wh 3D, 4K, Deep Color, and x.v.color. The DsplayPor* nerface suppors he VESA DsplayPor* Sandard Verson 1, Revson 2. The processor suppors Hgh-bandwdh Dgal Conen Proecon (HDCP) for hgh-defnon conen playback over dgal nerfaces. The processor also negraes dedcaed a Mn HD audo conroller o drve audo on negraed dgal dsplay nerfaces, such as HDMI* and DsplayPor*. The HD audo conroller on he PCH would connue o suppor down CODECs, and so on. The processor Mn HD audo conroller suppors wo Hgh-Defnon Audo sreams smulaneously on any of he hree dgal pors. The processor suppors sreamng any 3 ndependen and smulaneous dsplay combnaon of DsplayPor*/HDMI*/DVI/eDP*/VGA monors wh he excepon of 3 smulaneous dsplay suppor of HDMI*/DVI. In he case of 3 smulaneous dsplays, wo Hgh Defnon Audo sreams over he dgal dsplay nerfaces are suppored. Each dgal por s capable of drvng resoluons up o 3840x2160 a 60 Hz hrough DsplayPor* and 4096x2304 a 24 Hz/2560x1600 a 60 Hz usng HDMI*. DsplayPor* Aux CH, DDC channel, Panel power sequencng, and HPD are suppored hrough he PCH. Fgure 6. Processor Dsplay Archecure edp* Mux Transcoder edp* DP encoder Tmng, VDIP DPT, SRID DP Aux Dsplay Ppe A Transcoder A DP / HDMI Tmng, VDIP FDI FDI RX Dsplay Ppe Transcoder DP / HDMI Tmng, VDIP C DP / HDMI / DVI DP / HDMI / DVI Dsplay Ppe C Transcoder C DP / HDMI Tmng, VDIP D DP / HDMI / DVI / edp HD Audo Conroller Audo Codec Dsplay s he presenaon sage of graphcs. Ths nvolves: Pullng rendered daa from memory Converng raw daa no pxels lendng surfaces no a frame Daashee Volume 1 of 2 March Order No.:

33 Inerfaces Processor Organzng pxels no frames Oponally scalng he mage o he desred sze Re-mng daa for he nended arge Formang daa accordng o he por oupu sandard DsplayPor* DsplayPor* s a dgal communcaon nerface ha uses dfferenal sgnalng o acheve a hgh-bandwdh bus nerface desgned o suppor connecons beween PCs and monors, projecors, and TV dsplays. DsplayPor* s also suable for dsplay connecons beween consumer elecroncs devces, such as hgh-defnon opcal dsc players, se op boxes, and TV dsplays. A DsplayPor* consss of a Man Lnk, Auxlary channel, and a Ho-Plug Deec sgnal. The Man Lnk s a undreconal, hgh-bandwdh, and low laency channel used for ranspor of sochronous daa sreams such as uncompressed vdeo and audo. The Auxlary Channel (AUX CH) s a half-duplex bdreconal channel used for lnk managemen and devce conrol. The Ho-Plug Deec (HPD) sgnal serves as an nerrup reques for he snk devce. The processor s desgned n accordance wh he VESA DsplayPor* Sandard Verson 1.2a. The processor suppors VESA DsplayPor* PHY Complance Tes Specfcaon 1.2a and VESA DsplayPor* Lnk Layer Complance Tes Specfcaon 1.2a. Fgure 7. DsplayPor* Overvew Source Devce DsplayPor Tx Man Lnk (Isochronous Sreams) Snk Devce DsplayPor Rx AUX CH (Lnk/Devce Manageme) Ho-Plug Deec (Inerrup Reques) Hgh-Defnon Mulmeda Inerface (HDMI*) The Hgh-Defnon Mulmeda Inerface* (HDMI*) s provded for ransmng uncompressed dgal audo and vdeo sgnals from DVD players, se-op boxes, and oher audovsual sources o elevson ses, projecors, and oher vdeo dsplays. I can carry hgh qualy mul-channel audo daa and all sandard and hgh-defnon consumer elecroncs vdeo formas. The HDMI dsplay nerface connecng he processor and dsplay devces uses ranson mnmzed dfferenal sgnalng (TMDS) o carry audovsual nformaon hrough he same HDMI cable. HDMI ncludes hree separae communcaons channels TMDS, DDC, and he oponal CEC (consumer elecroncs conrol). CEC s no suppored on he processor. As shown n he followng fgure, he HDMI cable carres four dfferenal pars ha March 2015 Daashee Volume 1 of 2 Order No.:

34 Processor Inerfaces make up he TMDS daa and clock channels. These channels are used o carry vdeo, audo, and auxlary daa. In addon, HDMI carres a VESA DDC. The DDC s used by an HDMI Source o deermne he capables and characerscs of he Snk. Audo, vdeo, and auxlary (conrol/saus) daa s ransmed across he hree TMDS daa channels. The vdeo pxel clock s ransmed on he TMDS clock channel and s used by he recever for daa recovery on he hree daa channels. The dgal dsplay daa sgnals drven navely hrough he PCH are AC coupled and needs level shfng o conver he AC coupled sgnals o he HDMI complan dgal sgnals. The processor HDMI nerface s desgned n accordance wh he Hgh-Defnon Mulmeda Inerface wh 3D, 4K, Deep Color, and x.v.color. Fgure 8. HDMI* Overvew HDMI Source HDMI Tx TMDS Daa Channel 0 HDMI Snk HDMI Rx TMDS Daa Channel 1 TMDS Daa Channel 2 TMDS Clock Channel Ho-Plug Deec Dsplay Daa Channel (DDC) CEC Lne (oponal) Dgal Vdeo Inerface The processor Dgal Pors can be confgured o drve DVI-D. DVI uses TMDS for ransmng daa from he ransmer o he recever, whch s smlar o he HDMI proocol excep for he audo and CEC. Refer o he HDMI secon for more nformaon on he sgnals and daa ransmsson. To drve DVI-I hrough he back panel he VGA DDC sgnals are conneced along wh he dgal daa and clock sgnals from one of he Dgal Pors. When a sysem has suppor for a DVI-I por, hen eher VGA or he DVI-D hrough a sngle DVI-I connecor can be drven, bu no boh smulaneously. The dgal dsplay daa sgnals drven navely hrough he processor are AC coupled and need level shfng o conver he AC coupled sgnals o he HDMI complan dgal sgnals. Daashee Volume 1 of 2 March Order No.:

35 Inerfaces Processor embedded DsplayPor* embedded DsplayPor* (edp*) s an embedded verson of he DsplayPor sandard orened owards applcaons such as noebook and All-In-One PCs. Dgal Por D can be confgured as edp. Lke DsplayPor, embedded DsplayPor also consss of a Man Lnk, Auxlary channel, and an oponal Ho-Plug Deec sgnal. The edp on he processor can be confgured for 2 or 4 lanes. The processor suppors embedded DsplayPor* (edp*) Sandard Verson 1.2 and VESA embedded DsplayPor* Sandard Verson 1.2. Inegraed Audo HDMI and dsplay por nerfaces carry audo along wh vdeo. Processor suppors wo DMA conrollers o oupu wo Hgh Defnon audo sreams on wo dgal pors smulaneously. Suppors only he nernal HDMI and DP CODECs. Table 8. Processor Suppored Audo Formas over HDMI*and DsplayPor* Audo Formas HDMI* DsplayPor* AC-3 Dolby* Dgal Yes Yes Dolby Dgal Plus Yes Yes DTS-HD* Yes Yes LPCM, 192 khz/24 b, 8 Channel Yes Yes Dolby TrueHD, DTS-HD Maser Audo* (Lossless lu-ray Dsc* Audo Forma) Yes Yes The processor wll connue o suppor Slen sream. Slen sream s an negraed audo feaure ha enables shor audo sreams, such as sysem evens o be heard over he HDMI and DsplayPor monors. The processor suppors slen sreams over he HDMI and DsplayPor nerfaces a 44.1 khz, 48 khz, 88.2 khz, 96 khz, khz, and 192 khz samplng raes. Mulple Dsplay Confguraons The followng mulple dsplay confguraon modes are suppored (wh approprae drver sofware): Sngle Dsplay s a mode wh one dsplay por acvaed o dsplay he oupu o one dsplay devce. Inel Dsplay Clone s a mode wh up o hree dsplay pors acvaed o drve he dsplay conen of same color deph seng bu poenally dfferen refresh rae and resoluon sengs o all he acve dsplay devces conneced. Exended Deskop s a mode wh up o hree dsplay pors acvaed o drve he conen wh poenally dfferen color deph, refresh rae, and resoluon sengs on each of he acve dsplay devces conneced. The dgal pors on he processor can be confgured o suppor DsplayPor*/HDMI/ DVI. For Deskop desgns, dgal por D can be confgured as edpx4 n addon o dedcaed x2 por for Inel FDI for VGA. The followng able shows examples of vald hree dsplay confguraons hrough he processor. March 2015 Daashee Volume 1 of 2 Order No.:

36 Processor Inerfaces Table 9. Vald Three Dsplay Confguraons hrough he Processor Dsplay 1 Dsplay 2 Dsplay 3 Maxmum Resoluon Dsplay 1 Maxmum Resoluon Dsplay 2 Maxmum Resoluon Dsplay 3 HDMI HDMI DP 24 Hz 60 Hz 60 Hz DVI DVI DP 60 Hz 60 Hz DP DP DP 60 Hz VGA DP HDMI 60 Hz edp DP HDMI 60 Hz 60 Hz 60 Hz 24 Hz 60 Hz 24 Hz 60 Hz edp DP DP 60 Hz 60 Hz edp HDMI HDMI 60 Hz 24 Hz 60 Hz Noes: 1. Requres suppor of 2 channel DDR3/DDR3L 1600 MT/s confguraon for drvng 3 smulaneous 60 Hz dsplay resoluons 2. DP and edp resoluons n he above able are suppored for 4 lanes wh lnk daa rae HR2. The followng able shows he DP/eDP resoluons suppored for 1, 2, or 4 lanes dependng on lnk daa rae of RR, HR, and HR2. Table 10. DsplayPor and embedded DsplayPor* Resoluons for 1, 2, 4 Lanes Lnk Daa Rae of RR, HR, and HR2 Lnk Daa Rae Lane Coun RR 1064x x x1400 HR 1280x x x1800 HR2 1920x x x2160 Any 3 dsplays can be suppored smulaneously usng he followng rules: Maxmum of 2 HDMIs Maxmum of 2 DVIs Maxmum of 1 HDMI and 1 DVI Any 3 DsplayPor One VGA One edp Hgh-bandwdh Dgal Conen Proecon (HDCP) HDCP s he echnology for proecng hgh-defnon conen agans unauhorzed copy or unrecepve beween a source (compuer, dgal se op boxes, and so on) and he snk (panels, monor, and TVs). The processor suppors HDCP 1.4 for conen proecon over wred dsplays (HDMI*, DVI, and DsplayPor*). The HDCP 1.4 keys are negraed no he processor and cusomers are no requred o physcally confgure or handle he keys. Daashee Volume 1 of 2 March Order No.:

37 Inerfaces Processor 2.7 Inel Flexble Dsplay Inerface (Inel FDI) The Inel Flexble Dsplay Inerface (Inel FDI) passes dsplay daa from he processor (source) o he PCH (snk) for dsplay hrough a dsplay nerface on he PCH. Inel FDI suppors 2 lanes a 2.7 GT/s fxed frequency. Ths can be confgured o 1 or 2 lanes dependng on he bandwdh requremens. Inel FDI suppors 8 bs per color only. Sde band sync pn (FDI_CSYNC). Sde band nerrup pn (DISP_INT). Ths carres combned nerrup for HPDs of all he pors, AUX and I 2 C compleon evens, and so on. Inel FDI s no encryped as drves only VGA and conen proecon s no suppored on VGA. 2.8 Plaform Envronmenal Conrol Inerface (PECI) PECI s an Inel propreary nerface ha provdes a communcaon channel beween Inel processors and exernal componens, lke Super I/O (SIO) and Embedded Conrollers (EC), o provde processor emperaure, Turbo, TDP, and memory hrolng conrol mechansms and many oher servces. PECI s used for plaform hermal managemen and real me conrol and confguraon of processor feaures and performance PECI us Archecure The PECI archecure s based on a wred-or bus ha he clens (as processor PECI) can pull up hgh (wh srong drve). The dle sae on he bus s near zero. The followng fgure demonsraes PECI desgn and connecvy. Whle he hos/ orgnaor can be a hrd pary PECI hos, one of he PECI clens s a processor PECI devce. March 2015 Daashee Volume 1 of 2 Order No.:

38 Processor Inerfaces Fgure 9. PECI Hos-Clens Connecon Example V TT V TT Q1 nx PECI Q3 nx Q2 1X C PECI <10pF/Node Hos / Orgnaor PECI Clen Addonal PECI Clens Daashee Volume 1 of 2 March Order No.:

39 Technologes Processor 3.0 Technologes Ths chaper provdes a hgh-level descrpon of Inel echnologes mplemened n he processor. The mplemenaon of he feaures may vary beween he processor SKUs. Deals on he dfferen echnologes of Inel processors and oher relevan exernal noes are locaed a he Inel echnology web se: hp:// 3.1 Inel Vrualzaon Technology (Inel VT) Inel Vrualzaon Technology (Inel VT) makes a sngle sysem appear as mulple ndependen sysems o sofware. Ths allows mulple, ndependen operang sysems o run smulaneously on a sngle sysem. Inel VT comprses echnology componens o suppor vrualzaon of plaforms based on Inel archecure mcroprocessors and chpses. Inel Vrualzaon Technology (Inel VT) for IA-32, Inel 64 and Inel Archecure (Inel VT-x) added hardware suppor n he processor o mprove he vrualzaon performance and robusness. Inel Vrualzaon Technology for Dreced I/O (Inel VT-d) exends Inel VT-x by addng hardware asssed suppor o mprove I/O devce vrualzaon performance. Inel VT-x specfcaons and funconal descrpons are ncluded n he Inel 64 and IA-32 Archecures Sofware Developer s Manual, Volume 3 and s avalable a: hp:// The Inel VT-d specfcaon and oher Inel VT documens can be referenced a: hp:// hps://sharedspaces.nel.com/ses/pcdc/sepages/ingredens/ngreden.aspx? ng=vt Inel VT-x Objecves Inel VT-x provdes hardware acceleraon for vrualzaon of IA plaforms. Vrual Machne Monor (VMM) can use Inel VT-x feaures o provde an mproved relable vrualzed plaform. y usng Inel VT-x, a VMM s: Robus: VMMs no longer need o use paravrualzaon or bnary ranslaon. Ths means ha off-he-shelf operang sysems and applcaons can be run whou any specal seps. Enhanced: Inel VT enables VMMs o run 64-b gues operang sysems on IA x86 processors. March 2015 Daashee Volume 1 of 2 Order No.:

40 Processor Technologes More relable: Due o he hardware suppor, VMMs can now be smaller, less complex, and more effcen. Ths mproves relably and avalably and reduces he poenal for sofware conflcs. More secure: The use of hardware ransons n he VMM srenghens he solaon of VMs and furher prevens corrupon of one VM from affecng ohers on he same sysem. Inel VT-x Feaures The processor suppors he followng Inel VT-x feaures: Exended Page Table (EPT) Accessed and Dry s EPT A/D bs enabled VMMs o effcenly mplemen memory managemen and page classfcaon algorhms o opmze VM memory operaons, such as defragmenaon, pagng, lve mgraon, and check-ponng. Whou hardware suppor for EPT A/D bs, VMMs may need o emulae A/D bs by markng EPT pagng-srucures as no-presen or read-only, and ncur he overhead of EPT page-faul VM exs and assocaed sofware processng. Exended Page Table Poner (EPTP) swchng EPTP swchng s a specfc VM funcon. EPTP swchng allows gues sofware (n VMX non-roo operaon, suppored by EPT) o reques a dfferen EPT pagng-srucure herarchy. Ths s a feaure by whch sofware n VMX nonroo operaon can reques a change of EPTP whou a VM ex. Sofware can choose among a se of poenal EPTP values deermned n advance by sofware n VMX roo operaon. Pause loop exng Suppor VMM schedulers seekng o deermne when a vrual processor of a mulprocessor vrual machne s no performng useful work. Ths suaon may occur when no all vrual processors of he vrual machne are currenly scheduled and when he vrual processor n queson s n a loop nvolvng he PAUSE nsrucon. The new feaure allows deecon of such loops and s hus called PAUSE-loop exng. The processor core suppors he followng Inel VT-x feaures: Exended Page Tables (EPT) EPT s hardware asssed page able vrualzaon. I elmnaes VM exs from he gues operang sysem o he VMM for shadow page-able manenance. Vrual Processor IDs (VPID) Ably o assgn a VM ID o ag processor core hardware srucures (such as TLs). Ths avods flushes on VM ransons o gve a lower-cos VM ranson me and an overall reducon n vrualzaon overhead. Gues Preempon Tmer Mechansm for a VMM o preemp he execuon of a gues operang sysem afer an amoun of me specfed by he VMM. The VMM ses a mer value before enerng a gues. The feaure ads VMM developers n flexbly and Qualy of Servce (QoS) guaranees. Daashee Volume 1 of 2 March Order No.:

41 Technologes Processor Descrpor-Table Exng Descrpor-able exng allows a VMM o proec a gues operang sysem from an nernal (malcous sofware based) aack by prevenng relocaon of key sysem daa srucures lke IDT (nerrup descrpor able), GDT (global descrpor able), LDT (local descrpor able), and TSS (ask segmen selecor). A VMM usng hs feaure can nercep (by a VM ex) aemps o relocae hese daa srucures and preven hem from beng ampered by malcous sofware. Inel VT-d Objecves The key Inel VT-d objecves are doman-based solaon and hardware-based vrualzaon. A doman can be absracly defned as an solaed envronmen n a plaform o whch a subse of hos physcal memory s allocaed. Inel VT-d provdes acceleraed I/O performance for a vrualzed plaform and provdes sofware wh he followng capables: I/O devce assgnmen and secury: for flexbly assgnng I/O devces o VMs and exendng he proecon and solaon properes of VMs for I/O operaons. DMA remappng: for supporng ndependen address ranslaons for Drec Memory Accesses (DMA) from devces. Inerrup remappng: for supporng solaon and roung of nerrups from devces and exernal nerrup conrollers o approprae VMs. Relably: for recordng and reporng o sysem sofware DMA and nerrup errors ha may oherwse corrup memory or mpac VM solaon. Inel VT-d accomplshes address ranslaon by assocang a ransacon from a gven I/O devce o a ranslaon able assocaed wh he Gues o whch he devce s assgned. I does hs by means of he daa srucure n he followng llusraon. Ths able creaes an assocaon beween he devce's PCI Express* us/devce/funcon (/D/F) number and he base address of a ranslaon able. Ths daa srucure s populaed by a VMM o map devces o ranslaon ables n accordance wh he devce assgnmen resrcons above, and o nclude a mul-level ranslaon able (VT-d Table) ha conans Gues specfc address ranslaons. March 2015 Daashee Volume 1 of 2 Order No.:

42 Processor Technologes Fgure 10. Devce o Doman Mappng Srucures (Dev 31, Func 7) Conex enry 255 (Dev 0, Func 1) (Dev 0, Func 0) Conex enry 0 (us 255) Roo enry 255 Conex enry Table For bus N Address Translaon Srucures for Doman A (us N) Roo enry N (us 0) Roo enry 0 Roo enry able Conex enry 255 Conex enry 0 Conex enry Table For bus 0 Address Translaon Srucures for Doman Inel VT-d funconaly, ofen referred o as an Inel VT-d Engne, has ypcally been mplemened a or near a PCI Express hos brdge componen of a compuer sysem. Ths mgh be n a chpse componen or n he PCI Express funconaly of a processor wh negraed I/O. When one such Inel VT-d engne receves a PCI Express ransacon from a PCI Express bus, uses he /D/F number assocaed wh he ransacon o search for an Inel VT-d ranslaon able. In dong so, uses he /D/F number o raverse he daa srucure shown n he above fgure. If fnds a vald Inel VT-d able n hs daa srucure, uses ha able o ranslae he address provded on he PCI Express bus. If does no fnd a vald ranslaon able for a gven ranslaon, hs resuls n an Inel VT-d faul. If Inel VT-d ranslaon s requred, he Inel VT-d engne performs an N-level able walk. For more nformaon, refer o Inel Vrualzaon Technology for Dreced I/O Archecure Specfcaon hp://download.nel.com/echnology/compung/vpech/ Inel(r)_VT_for_Drec_IO.pdf Inel VT-d Feaures The processor suppors he followng Inel VT-d feaures: Daashee Volume 1 of 2 March Order No.:

43 Technologes Processor Memory conroller and processor graphcs comply wh he Inel VT-d 1.2 Specfcaon Two Inel VT-d DMA remap engnes GFX DMA remap engne Defaul DMA remap engne (covers all devces excep GFX) Suppor for roo enry, conex enry, and defaul conex 39-b gues physcal address and hos physcal address wdhs Suppor for 4 K page szes Suppor for regser-based faul recordng only (for sngle enry only) and suppor for MSI nerrups for fauls Suppor for boh leaf and non-leaf cachng Suppor for boo proecon of defaul page able Suppor for non-cachng of nvald page able enres Suppor for hardware-based flushng of ranslaed bu pendng wres and pendng reads, on IOTL nvaldaon Suppor for Global, Doman specfc, and Page specfc IOTL nvaldaon MSI cycles (MemWr o address FEEx_xxxxh) no ranslaed Translaon fauls resul n cycle forwardng o VIOS regon (bye enables masked for wres). Reurned daa may be bogus for nernal agens; PEG/DMI nerfaces reurn unsuppored reques saus Inerrup remappng s suppored Queued nvaldaon s suppored Inel VT-d ranslaon bypass address range s suppored (Pass Through) The processor suppors he followng added new Inel VT-d feaures: 4-level Inel VT-d Page walk: oh defaul Inel VT-d engne, as well as he IGD Inel VT-d engne, are upgraded o suppor 4-level Inel VT-d ables (adjused gues address wdh 48 bs) Inel VT-d superpage: suppor of Inel VT-d superpage (2 M, 1 G) for he defaul Inel VT-d engne (ha covers all devces excep IGD) IGD Inel VT-d engne does no suppor superpage and IOS should dsable superpage n defaul Inel VT-d engne when GFX s enabled. Noe: 3.2 Inel VT-d Technology may no be avalable on all SKUs. Inel Trused Execuon Technology (Inel TXT) Inel Trused Execuon Technology (Inel TXT) defnes plaform-level enhancemens ha provde he buldng blocks for creang rused plaforms. The Inel TXT plaform helps o provde he auhency of he conrollng envronmen such ha hose wshng o rely on he plaform can make an approprae rus decson. The Inel TXT plaform deermnes he deny of he conrollng envronmen by accuraely measurng and verfyng he conrollng sofware. March 2015 Daashee Volume 1 of 2 Order No.:

44 Processor Technologes Anoher aspec of he rus decson s he ably of he plaform o ress aemps o change he conrollng envronmen. The Inel TXT plaform wll ress aemps by sofware processes o change he conrollng envronmen or bypass he bounds se by he conrollng envronmen. Inel TXT s a se of exensons desgned o provde a measured and conrolled launch of sysem sofware ha wll hen esablsh a proeced envronmen for self and any addonal sofware ha may execue. These exensons enhance wo areas: The launchng of he Measured Launched Envronmen (MLE). The proecon of he MLE from poenal corrupon. The enhanced plaform provdes hese launch and conrol nerfaces usng Safer Mode Exensons (SMX). The SMX nerface ncludes he followng funcons: Measured/Verfed launch of he MLE. Mechansms o ensure he above measuremen s proeced and sored n a secure locaon. Proecon mechansms ha allow he MLE o conrol aemps o modfy self. The processor also offers addonal enhancemens o Sysem Managemen Mode (SMM) archecure for enhanced secury and performance. The processor provdes new MSRs o: Enable a second SMM range Enable SMM code execuon range checkng Selec wheher SMM Save Sae s o be wren o legacy SMRAM or o MSRs Deermne f a hread s gong o be delayed enerng SMM Deermne f a hread s blocked from enerng SMM Targeed SMI, enable/dsable hreads from respondng o SMIs boh VLWs and IPI For he above feaures, IOS mus es he assocaed capably b before aempng o access any of he above regsers. For more nformaon, refer o he Inel Trused Execuon Technology Measured Launched Envronmen Programmng Gude. 3.3 Inel Hyper-Threadng Technology (Inel HT Technology) The processor suppors Inel Hyper-Threadng Technology (Inel HT Technology) ha allows an execuon core o funcon as wo logcal processors. Whle some execuon resources, such as caches, execuon uns, and buses are shared, each logcal processor has s own archecural sae wh s own se of general-purpose regsers and conrol regsers. Ths feaure mus be enabled usng he IOS and requres operang sysem suppor. Daashee Volume 1 of 2 March Order No.:

45 Technologes Processor Inel recommends enablng Inel HT Technology wh Mcrosof Wndows* 8 and Mcrosof Wndows* 7 and dsablng Inel HT Technology usng he IOS for all prevous versons of Wndows* operang sysems. For more nformaon on Inel HT Technology, see hp:// 3.4 Inel Turbo oos Technology 2.0 The Inel Turbo oos Technology 2.0 allows he processor core o opporunscally and auomacally run faser han s raed operang frequency/render clock, f s operang below power, emperaure, and curren lms. The Inel Turbo oos Technology 2.0 feaure s desgned o ncrease performance of boh mul-hreaded and sngle-hreaded workloads. Maxmum frequency s dependan on he SKU and number of acve cores. No specal hardware suppor s necessary for Inel Turbo oos Technology 2.0. IOS and he operang sysem can enable or dsable Inel Turbo oos Technology 2.0. Compared wh prevous generaon producs, Inel Turbo oos Technology 2.0 wll ncrease he rao of applcaon power o TDP. Thus, hermal soluons and plaform coolng ha are desgned o less han hermal desgn gudance mgh experence hermal and performance ssues snce more applcaons wll end o run a he maxmum power lm for sgnfcan perods of me. Noe: Inel Turbo oos Technology 2.0 may no be avalable on all SKUs. Inel Turbo oos Technology 2.0 Frequency The processor raed frequency assumes ha all execuon cores are runnng an applcaon a he hermal desgn power (TDP). However, under ypcal operaon, no all cores are acve. Therefore, mos applcaons are consumng less han he TDP a he raed frequency. To ake advanage of he avalable hermal headroom, he acve cores can ncrease her operang frequency. To deermne he hghes performance frequency amongs acve cores, he processor akes he followng no consderaon: The number of cores operang n he C0 sae. The esmaed core curren consumpon. The esmaed package pror and presen power consumpon. The package emperaure. Any of hese facors can affec he maxmum frequency for a gven workload. If he power, curren, or hermal lm s reached, he processor wll auomacally reduce he frequency o say whn s TDP lm. Turbo processor frequences are only acve f he operang sysem s requesng he P0 sae. For more nformaon on P-saes and C-saes, see Power Managemen on page Inel Advanced Vecor Exensons 2.0 (Inel AVX2) Inel Advanced Vecor Exensons 2.0 (Inel AVX2) s he laes expanson of he Inel nsrucon se. Inel AVX2 exends he Inel Advanced Vecor Exensons (Inel AVX) wh 256-b neger nsrucons, floang-pon fused mulply add (FMA) nsrucons, and gaher operaons. The 256-b neger vecors benef mah, codec, mage, and March 2015 Daashee Volume 1 of 2 Order No.:

46 Processor Technologes dgal sgnal processng sofware. FMA mproves performance n face deecon, professonal magng, and hgh performance compung. Gaher operaons ncrease vecorzaon opporunes for many applcaons. In addon o he vecor exensons, hs generaon of Inel processors adds new b manpulaon nsrucons useful n compresson, encrypon, and general purpose sofware. For more nformaon on Inel AVX, see hp:// 3.6 Inel Advanced Encrypon Sandard New Insrucons (Inel AES-NI) The processor suppors Inel Advanced Encrypon Sandard New Insrucons (Inel AES-NI) ha are a se of Sngle Insrucon Mulple Daa (SIMD) nsrucons ha enable fas and secure daa encrypon and decrypon based on he Advanced Encrypon Sandard (AES). Inel AES-NI are valuable for a wde range of crypographc applcaons, such as applcaons ha perform bulk encrypon/ decrypon, auhencaon, random number generaon, and auhencaed encrypon. AES s broadly acceped as he sandard for boh governmen and ndusry applcaons, and s wdely deployed n varous proocols. Inel AES-NI consss of sx Inel SSE nsrucons. Four nsrucons, AESENC, AESENCLAST, AESDEC, and AESDELAST faclae hgh performance AES encrypon and decrypon. The oher wo, AESIMC and AESKEYGENASSIST, suppor he AES key expanson procedure. Togeher, hese nsrucons provde a full hardware for supporng AES; offerng secury, hgh performance, and a grea deal of flexbly. PCLMULQDQ Insrucon The processor suppors he carry-less mulplcaon nsrucon, PCLMULQDQ. PCLMULQDQ s a Sngle Insrucon Mulple Daa (SIMD) nsrucon ha compues he 128-b carry-less mulplcaon of wo, 64-b operands whou generang and propagang carres. Carry-less mulplcaon s an essenal processng componen of several crypographc sysems and sandards. Hence, accelerang carry-less mulplcaon can sgnfcanly conrbue o achevng hgh speed secure compung and communcaon. Inel Secure Key The processor suppors Inel Secure Key (formerly known as Dgal Random Number Generaor (DRNG)), a sofware vsble random number generaon mechansm suppored by a hgh qualy enropy source. Ths capably s avalable o programmers hrough he RDRAND nsrucon. The resulan random number generaon capably s desgned o comply wh exsng ndusry sandards n hs regard (ANSI X9.82 and NIST SP ). Some possble usages of he RDRAND nsrucon nclude crypographc key generaon as used n a varey of applcaons, ncludng communcaon, dgal sgnaures, secure sorage, and so on. 3.7 Inel Transaconal Synchronzaon Exensons - New Insrucons (Inel TSX-NI) Inel Transaconal Synchronzaon Exensons - New Insrucons (Inel TSX-NI). Inel TSX-NI provdes a se of nsrucon exensons ha allow programmers o specfy regons of code for ransaconal synchronzaon. Programmers can use hese Daashee Volume 1 of 2 March Order No.:

47 Technologes Processor exensons o acheve he performance of fne-gran lockng whle acually programmng usng coarse-gran locks. Deals on Inel TSX-NI are n he Inel Archecure Insrucon Se Exensons Programmng Reference. 3.8 Inel 64 Archecure x2apic The x2apic archecure exends he xapic archecure ha provdes key mechansms for nerrup delvery. Ths exenson s prmarly nended o ncrease processor addressably. Specfcally, x2apic: Reans all key elemens of compably o he xapic archecure: Delvery modes Inerrup and processor prores Inerrup sources Inerrup desnaon ypes Provdes exensons o scale processor addressably for boh he logcal and physcal desnaon modes Adds new feaures o enhance performance of nerrup delvery Reduces complexy of logcal desnaon mode nerrup delvery on lnk based archecures The key enhancemens provded by he x2apic archecure over xapic are he followng: Suppor for wo modes of operaon o provde backward compably and exensbly for fuure plaform nnovaons: In xapic compably mode, APIC regsers are accessed hrough memory mapped nerface o a 4K-ye page, dencal o he xapic archecure. In x2apic mode, APIC regsers are accessed hrough Model Specfc Regser (MSR) nerfaces. In hs mode, he x2apic archecure provdes sgnfcanly ncreased processor addressably and some enhancemens on nerrup delvery. Increased range of processor addressably n x2apic mode: Physcal xapic ID feld ncreases from 8 bs o 32 bs, allowng for nerrup processor addressably up o 4G 1 processors n physcal desnaon mode. A processor mplemenaon of x2apic archecure can suppor fewer han 32- bs n a sofware ransparen fashon. Logcal xapic ID feld ncreases from 8 bs o 32 bs. The 32-b logcal x2apic ID s paroned no wo sub-felds a 16-b cluser ID and a 16-b logcal ID whn he cluser. Consequenly, ((2^20) 16) processors can be addressed n logcal desnaon mode. Processor mplemenaons can suppor fewer han 16 bs n he cluser ID sub-feld and logcal ID sub-feld n a sofware agnosc fashon. More effcen MSR nerface o access APIC regsers: To enhance ner-processor and self-dreced nerrup delvery as well as he ably o vrualze he local APIC, he APIC regser se can be accessed only hrough MSR-based nerfaces n x2apic mode. The Memory Mapped IO (MMIO) nerface used by xapic s no suppored n x2apic mode. March 2015 Daashee Volume 1 of 2 Order No.:

48 Processor Technologes The semancs for accessng APIC regsers have been revsed o smplfy he programmng of frequenly-used APIC regsers by sysem sofware. Specfcally, he sofware semancs for usng he Inerrup Command Regser (ICR) and End Of Inerrup (EOI) regsers have been modfed o allow for more effcen delvery and dspachng of nerrups. The x2apic exensons are made avalable o sysem sofware by enablng he local x2apic un n he x2apic mode. To benef from x2apic capables, a new operang sysem and a new IOS are boh needed, wh specal suppor for x2apic mode. The x2apic archecure provdes backward compably o he xapic archecure and forward exendble for fuure Inel plaform nnovaons. Noe: Inel x2apic Technology may no be avalable on all SKUs. For more nformaon, see he Inel 64 Archecure x2apic Specfcaon a hp:// Power Aware Inerrup Roung (PAIR) The processor ncludes enhanced power-performance echnology ha roues nerrups o hreads or cores based on her sleep saes. As an example, for energy savngs, roues he nerrup o he acve cores whou wakng he deep dle cores. For performance, roues he nerrup o he dle (C1) cores whou nerrupng he already heavly loaded cores. Ths enhancemen s mosly benefcal for hgh-nerrup scenaros lke Ggab LAN, WLAN perpherals, and so on Execue Dsable The Execue Dsable allows memory o be marked as execuable when combned wh a supporng operang sysem. If code aemps o run n non-execuable memory, he processor rases an error o he operang sysem. Ths feaure can preven some classes of vruses or worms ha explo buffer overrun vulnerables and can hus help mprove he overall secury of he sysem. See he Inel 64 and IA-32 Archecures Sofware Developer's Manuals for more dealed nformaon Supervsor Mode Execuon Proecon (SMEP) Supervsor Mode Execuon Proecon provdes he nex level of sysem proecon by blockng malcous sofware aacks from user mode code when he sysem s runnng n he hghes prvlege level. Ths echnology helps o proec from vrus aacks and unwaned code from harmng he sysem. For more nformaon, refer o Inel 64 and IA-32 Archecures Sofware Developer's Manual, Volume 3A a: hp:// Daashee Volume 1 of 2 March Order No.:

49 Power Managemen Processor 4.0 Power Managemen Ths chaper provdes nformaon on he followng power managemen opcs: Advanced Confguraon and Power Inerface (ACPI) Saes Processor Core Inegraed Memory Conroller (IMC) PCI Express* Drec Meda Inerface (DMI) Processor Graphcs Conroller Fgure 11. Processor Power Saes G0 - Workng S0 Processor Fully powered on (full on mode / conneced sandby mode) C0 Acve mode P0 Pn C1 Auo Hal C1E Auo Hal, Low freq, low volage C3 L1/L2 caches flush, clocks off C6 Save core saes before shudown C7 Smlar o C6, L3 flush G1 Sleepng S3 Cold Sleep Suspend o Ram (STR) S4 Hbernae Suspend o Dsk (STD), Wakeup on PCH S5 Sof Off no power, Wakeup on PCH G3 Mechancal OFF Noe: Power saes avalably may vary beween he dfferen SKUs March 2015 Daashee Volume 1 of 2 Order No.:

50 Processor Power Managemen 4.1 Advanced Confguraon and Power Inerface (ACPI) Saes Suppored Ths secon descrbes he ACPI saes suppored by he processor. Table 11. Sysem Saes Sae Descrpon G0/S0 G1/S3-Cold G1/S4 G2/S5 G3 Full On Mode. Suspend-o-RAM (STR). Conex saved o memory (S3-Ho sae s no suppored by he processor). Suspend-o-Dsk (STD). All power los (excep wakeup on PCH). Sof off. All power los (excep wakeup on PCH). Toal reboo. Mechancal off. All power removed from sysem. Table 12. Processor Core / Package Sae Suppor Sae C0 C1 C1E C3 C6 C7 Acve mode, processor execung code. AuoHALT sae. Descrpon AuoHALT sae wh lowes frequency and volage operang pon. Execuon cores n C3 sae flush her L1 nsrucon cache, L1 daa cache, and L2 cache o he L3 shared cache. Clocks are shu off o each core. Execuon cores n hs sae save her archecural sae before removng core volage. Execuon cores n hs sae behave smlarly o he C6 sae. If all execuon cores reques C7 sae, L3 cache ways are flushed unl s cleared. If he enre L3 cache s flushed, volage wll be removed from he L3 cache. Power removal o SA, Cores and L3 wll reduce power consumpon. C7 may no be avalable on all SKUs. Table 13. Inegraed Memory Conroller Saes Sae Descrpon Power up Pre-charge Power-down Acve Powerdown Self-Refresh CKE assered. Acve mode. CKE de-assered (no self-refresh) wh all banks closed. CKE de-assered (no self-refresh) wh mnmum one bank acve. CKE de-assered usng devce self-refresh. Table 14. PCI Express* Lnk Saes Sae Descrpon L0 L0s L1 L3 Full on Acve ransfer sae. Frs Acve Power Managemen low-power sae Low ex laency. Lowes Acve Power Managemen Longer ex laency. Lowes power sae (power-off) Longes ex laency. Daashee Volume 1 of 2 March Order No.:

51 Power Managemen Processor Table 15. Drec Meda Inerface (DMI) Saes Sae Descrpon L0 L0s L1 L3 Full on Acve ransfer sae. Frs Acve Power Managemen low-power sae Low ex laency. Lowes Acve Power Managemen Longer ex laency. Lowes power sae (power-off) Longes ex laency. Table 16. G, S, and C Inerface Sae Combnaons Global (G) Sae Sleep (S) Sae Processor Package (C) Sae Processor Sae Sysem Clocks Descrpon G0 S0 C0 Full On On Full On G0 S0 C1/C1E Auo-Hal On Auo-Hal G0 S0 C3 Deep Sleep On Deep Sleep G0 S0 C6/C7 Deep Powerdown On Deep Power-down G1 S3 Power off Off, excep RTC Suspend o RAM G1 S4 Power off Off, excep RTC Suspend o Dsk G2 S5 Power off Off, excep RTC Sof Off G3 NA Power off Power off Hard off Table 17. D, S, and C Inerface Sae Combnaon Graphcs Adaper (D) Sae Sleep (S) Sae Package (C) Sae Descrpon D0 S0 C0 Full On, Dsplayng. D0 S0 C1/C1E Auo-Hal, Dsplayng. D0 S0 C3 Deep sleep, Dsplayng. D0 S0 C6/C7 Deep Power-down, Dsplayng. D3 S0 Any No dsplayng. D3 S3 N/A No dsplayng, Graphcs Core s powered off. D3 S4 N/A No dsplayng, suspend o dsk. 4.2 Processor Core Power Managemen Whle execung code, Enhanced Inel SpeedSep Technology opmzes he processor s frequency and core volage based on workload. Each frequency and volage operang pon s defned by ACPI as a P-sae. When he processor s no execung code, s dle. A low-power dle sae s defned by ACPI as a C-sae. In general, deeper power C-saes have longer enry and ex laences Enhanced Inel SpeedSep Technology Key Feaures The followng are he key feaures of Enhanced Inel SpeedSep Technology: March 2015 Daashee Volume 1 of 2 Order No.:

52 Processor Power Managemen Mulple frequency and volage pons for opmal performance and power effcency. These operang pons are known as P-saes. Frequency selecon s sofware conrolled by wrng o processor MSRs. The volage s opmzed based on he seleced frequency and he number of acve processor cores. Once he volage s esablshed, he PLL locks on o he arge frequency. All acve processor cores share he same frequency and volage. In a mulcore processor, he hghes frequency P-sae requesed among all acve cores s seleced. Sofware-requesed ransons are acceped a any me. If a prevous ranson s n progress, he new ranson s deferred unl he prevous ranson s compleed. The processor conrols volage ramp raes nernally o ensure glch-free ransons. ecause here s low ranson laency beween P-saes, a sgnfcan number of ransons per-second are possble Low-Power Idle Saes When he processor s dle, low-power dle saes (C-saes) are used o save power. More power savngs acons are aken for numercally hgher C-saes. However, hgher C-saes have longer ex and enry laences. Resoluon of C-saes occur a he hread, processor core, and processor package level. Thread-level C-saes are avalable f Inel Hyper-Threadng Technology s enabled. Cauon: Fgure 12. Long erm relably canno be assured unless all he Low-Power Idle Saes are enabled. Idle Power Managemen reakdown of he Processor Cores Thread 0 Thread 1 Thread 0 Thread 1 Core 0 Sae Core N Sae Processor Package Sae Enry and ex of he C-saes a he hread and core level are shown n he followng fgure. Daashee Volume 1 of 2 March Order No.:

53 Power Managemen Processor Fgure 13. Thread and Core C-Sae Enry and Ex MWAIT(C1), HLT MWAIT(C1), HLT (C1E Enabled) C0 MWAIT(C3), P_LVL2 I/O Read MWAIT(C7), P_LVL4 I/O Read MWAIT(C6), P_LVL3 I/O Read C1 C1E C3 C6 C7 Whle ndvdual hreads can reques low-power C-saes, power savng acons only ake place once he core C-sae s resolved. Core C-saes are auomacally resolved by he processor. For hread and core C-saes, a ranson o and from C0 s requred before enerng any oher C-sae. Table 18. Coordnaon of Thread Power Saes a he Core Level Processor Core C-Sae Thread 1 C0 C1 C3 C6 C7 C0 C0 C0 C0 C0 C0 C1 C0 C1 1 C1 1 C1 1 C1 1 Thread 0 C3 C0 C1 1 C3 C3 C3 C6 C0 C1 1 C3 C6 C6 C7 C0 C1 1 C3 C6 C7 Noe: 1. If enabled, he core C-sae wll be C1E f all cores have resolved a core C1 sae or hgher Requesng Low-Power Idle Saes The prmary sofware nerfaces for requesng low-power dle saes are hrough he MWAIT nsrucon wh sub-sae hns and he HLT nsrucon (for C1 and C1E). However, sofware may make C-sae requess usng he legacy mehod of I/O reads from he ACPI-defned processor clock conrol regsers, referred o as P_LVLx. Ths mehod of requesng C-saes provdes legacy suppor for operang sysems ha nae C-sae ransons usng I/O reads. For legacy operang sysems, P_LVLx I/O reads are convered whn he processor o he equvalen MWAIT C-sae reques. Therefore, P_LVLx reads do no drecly resul n I/O reads o he sysem. The feaure, known as I/O MWAIT redrecon, mus be enabled n he IOS. The IOS can wre o he C-sae range feld of he PMG_IO_CAPTURE MSR o resrc he range of I/O addresses ha are rapped and emulae MWAIT lke funconaly. Any P_LVLx reads ousde of hs range do no cause an I/O redrecon o MWAIT(Cx) lke reques. The reads fall hrough lke a normal I/O nsrucon. March 2015 Daashee Volume 1 of 2 Order No.:

54 Processor Power Managemen Noe: When P_LVLx I/O nsrucons are used, MWAIT sub-saes canno be defned. The MWAIT sub-sae s always zero f I/O MWAIT redrecon s used. y defaul, P_LVLx I/O redrecons enable he MWAIT 'break on EFLAGS.IF feaure ha rggers a wakeup on an nerrup, even f nerrups are masked by EFLAGS.IF. Core C-Sae Rules The followng are general rules for all core C-saes, unless specfed oherwse: A core C-sae s deermned by he lowes numercal hread sae (such as Thread 0 requess C1E sae whle Thread 1 requess C3 sae, resulng n a core C1E sae). See he G, S, and C Inerface Sae Combnaons able. A core ransons o C0 sae when: An nerrup occurs There s an access o he monored address f he sae was enered usng an MWAIT/Tmed MWAIT nsrucon The deadlne correspondng o he Tmed MWAIT nsrucon expres An nerrup dreced oward a sngle hread wakes only ha hread. If any hread n a core s n acve (n C0 sae), he core's C-sae wll resolve o C0 sae. Any nerrup comng no he processor package may wake any core. A sysem rese re-nalzes all processor cores. Core C0 Sae The normal operang sae of a core where code s beng execued. Core C1/C1E Sae C1/C1E s a low power sae enered when all hreads whn a core execue a HLT or MWAIT(C1/C1E) nsrucon. A Sysem Managemen Inerrup (SMI) handler reurns execuon o eher Normal sae or he C1/C1E sae. See he Inel 64 and IA-32 Archecures Sofware Developer s Manual for more nformaon. Whle a core s n C1/C1E sae, processes bus snoops and snoops from oher hreads. For more nformaon on C1E sae, see Package C-Saes on page 55. Core C3 Sae Indvdual hreads of a core can ener he C3 sae by nang a P_LVL2 I/O read o he P_LK or an MWAIT(C3) nsrucon. A core n C3 sae flushes he conens of s L1 nsrucon cache, L1 daa cache, and L2 cache o he shared L3 cache, whle mananng s archecural sae. All core clocks are sopped a hs pon. ecause he core s caches are flushed, he processor does no wake any core ha s n he C3 sae when eher a snoop s deeced or when anoher core accesses cacheable memory. Daashee Volume 1 of 2 March Order No.:

55 Power Managemen Processor Core C6 Sae Indvdual hreads of a core can ener he C6 sae by nang a P_LVL3 I/O read or an MWAIT(C6) nsrucon. efore enerng core C6 sae, he core wll save s archecural sae o a dedcaed SRAM. Once complee, a core wll have s volage reduced o zero vols. Durng ex, he core s powered on and s archecural sae s resored. Core C7 Sae Indvdual hreads of a core can ener he C7 sae by nang a P_LVL4 I/O read o he P_LK or by an MWAIT(C7) nsrucon. The core C7 sae exhbs he same behavor as he core C6 sae. Noe: C7 sae may no be avalable on all SKUs. C-Sae Auo-Demoon In general, deeper C-saes, such as C6 sae, have long laences and have hgher energy enry/ex coss. The resulng performance and energy penales become sgnfcan when he enry/ex frequency of a deeper C-sae s hgh. Therefore, ncorrec or neffcen usage of deeper C-saes have a negave mpac on dle power. To ncrease resdency and mprove dle power n deeper C-saes, he processor suppors C-sae auo-demoon. There are wo C-sae auo-demoon opons: C7/C6 o C3 sae C7/C6/C3 To C1 sae The decson o demoe a core from C6/C7 o C3 or C3/C6/C7 o C1 sae s based on each core s mmedae resdency hsory and nerrup rae. If he nerrup rae experenced on a core s hgh and he resdence n a deep C-sae beween such nerrups s low, he core can be demoed o a C3 or C1 sae. A hgher nerrup paern s requred o demoe a core o C1 sae as compared o C3 sae. Ths feaure s dsabled by defaul. IOS mus enable n he PMG_CST_CONFIG_CONTROL regser. The auo-demoon polcy s also confgured by hs regser Package C-Saes The processor suppors C0, C1/C1E, C3, C6, and C7 (on some SKUs) power saes. The followng s a summary of he general rules for package C-sae enry. These apply o all package C-saes, unless specfed oherwse: A package C-sae reques s deermned by he lowes numercal core C-sae amongs all cores. A package C-sae s auomacally resolved by he processor dependng on he core dle power saes and he saus of he plaform componens. Each core can be a a lower dle power sae han he package f he plaform does no gran he processor permsson o ener a requesed package C-sae. The plaform may allow addonal power savngs o be realzed n he processor. March 2015 Daashee Volume 1 of 2 Order No.:

56 Processor Power Managemen For package C-saes, he processor s no requred o ener C0 sae before enerng any oher C-sae. Enry no a package C-sae may be subjec o auo-demoon ha s, he processor may keep he package n a deeper package C-sae han requesed by he operang sysem f he processor deermnes, usng heurscs, ha he deeper C-sae resuls n beer power/performance. The processor exs a package C-sae when a break even s deeced. Dependng on he ype of break even, he processor does he followng: If a core break even s receved, he arge core s acvaed and he break even message s forwarded o he arge core. If he break even s no masked, he arge core eners he core C0 sae and he processor eners package C0 sae. If he break even s masked, he processor aemps o re-ener s prevous package sae. If he break even was due o a memory access or snoop reques, u he plaform dd no reques o keep he processor n a hgher package C- sae, he package reurns o s prevous C-sae. And he plaform requess a hgher power C-sae, he memory access or snoop reques s servced and he package remans n he hgher power C- sae. The followng able shows package C-sae resoluon for a dual-core processor. The followng fgure summarzes package C-sae ransons. Table 19. Coordnaon of Core Power Saes a he Package Level Package C-Sae Core 1 C0 C1 C3 C6 C7 C0 C0 C0 C0 C0 C0 C1 C0 C1 1 C1 1 C1 1 C1 1 Core 0 C3 C0 C1 1 C3 C3 C3 C6 C0 C1 1 C3 C6 C6 C7 C0 C1 1 C3 C6 C7 Noe: 1. If enabled, he package C-sae wll be C1E f all cores have resolved a core C1 sae or hgher. Daashee Volume 1 of 2 March Order No.:

57 Power Managemen Processor Fgure 14. Package C-Sae Enry and Ex C0 C3 C6 C1 C7 Package C0 Sae Ths s he normal operang sae for he processor. The processor remans n he normal sae when a leas one of s cores s n he C0 or C1 sae or when he plaform has no graned permsson o he processor o go no a low-power sae. Indvdual cores may be n lower power dle saes whle he package s n C0 sae. Package C1/C1E Sae No addonal power reducon acons are aken n he package C1 sae. However, f he C1E sub-sae s enabled, he processor auomacally ransons o he lowes suppored core clock frequency, followed by a reducon n volage. The package eners he C1 low-power sae when: A leas one core s n he C1 sae. The oher cores are n a C1 or deeper power sae. The package eners he C1E sae when: All cores have drecly requesed C1E usng MWAIT(C1) wh a C1E sub-sae hn. All cores are n a power sae deeper han C1/C1E sae; however, he package low-power sae s lmed o C1/C1E usng he PMG_CST_CONFIG_CONTROL MSR. All cores have requesed C1 sae usng HLT or MWAIT(C1) and C1E auopromoon s enabled n IA32_MISC_ENALES. No nofcaon o he sysem occurs upon enry o C1/C1E sae. March 2015 Daashee Volume 1 of 2 Order No.:

58 Processor Power Managemen Package C2 Sae Package C2 sae s an nernal processor sae ha canno be explcly requesed by sofware. A processor eners Package C2 sae when: All cores and graphcs have requesed a C3 or deeper power sae; however, consrans (LTR, programmed mer evens n he near fuure, and so on) preven enry o any sae deeper han C 2 sae. Or, All cores and graphcs are n he C3 or deeper power saes, and a memory access reques s receved. Upon compleon of all ousandng memory requess, he processor ransons back no a deeper package C-sae. Package C3 Sae A processor eners he package C3 low-power sae when: A leas one core s n he C3 sae. The oher cores are n a C3 sae or deeper power sae and he processor has been graned permsson by he plaform. The plaform has no graned a reques o a package C6 or deeper sae, however, has allowed a package C6 sae. In package C3 sae, he L3 shared cache s vald. Package C6 Sae A processor eners he package C6 low-power sae when: A leas one core s n he C6 sae. The oher cores are n a C6 or deeper power sae and he processor has been graned permsson by he plaform. If he cores are requesng C7 sae, bu he plaform s lmng o a package C6 sae, he las level cache n hs case can be flushed. In package C6 sae all cores have saved her archecural sae and have had her core volages reduced o zero vols. I s possble he L3 shared cache s flushed and urned off n package C6 sae. If a leas one core s requesng C6 sae, he L3 cache wll no be flushed. Package C7 Sae The processor eners he package C7 low-power sae when all cores are n he C7 sae. In package C7, he processor wll ake acon o remove power from porons of he sysem agen. Core break evens are handled he same way as n package C3 or C6 sae. Noe: C7 sae may no be avalable on all SKUs. Daashee Volume 1 of 2 March Order No.:

59 Power Managemen Processor Noe: Package C6 sae s he deepes C-sae suppored on dscree graphcs sysems wh PCI Express Graphcs (PEG). Package C7 sae s he deepes C-sae suppored on negraed graphcs sysems (or swchable graphcs sysems durng negraed graphcs mode). However, n mos confguraons, package C6 wll be more energy effcen han package C7 sae. As a resul, package C7 sae resdency s expeced o be very low or zero n mos scenaros where he dsplay s enabled. Logc nernal o he processor wll deermne wheher package C6 or package C7 sae s he mos effcen. There s no need o make changes n IOS or sysem sofware o prorze package C6 sae over package C7 sae Package C-Saes and Dsplay Resoluons The negraed graphcs engne has he frame buffer locaed n sysem memory. When he dsplay s updaed, he graphcs engne feches dsplay daa from sysem memory. Dfferen screen resoluons and refresh raes have dfferen memory laency requremens. These requremens may lm he deepes Package C-sae he processor can ener. Oher elemens ha may affec he deepes Package C-sae avalable are he followng: Dsplay s on or off Sngle or mulple dsplays Nave or non-nave resoluon Panel Self Refresh (PSR) echnology Noe: Dsplay resoluon s no he only facor nfluencng he deepes Package C-sae he processor can ge no. Devce laences, nerrup response laences, and core C- saes are among oher facors ha nfluence he fnal package C-sae he processor can ener. The followng able lss dsplay resoluons and deepes avalable package C-Sae. The dsplay resoluons are examples usng common values for blankng and pxel rae. Acual resuls wll vary. The able shows he deepes possble Package C-sae. Sysem workload, sysem dle, and AC or DC power also affec he deepes possble Package C-sae. Table 20. Deepes Package C-Sae Avalable Number of Dsplays 1 Nave Resoluon Deepes Avalable Package C- Sae Sngle 800x Hz PC6 Sngle 1024x Hz PC6 Sngle 1280x Hz PC6 Sngle 1920x Hz PC6 Sngle 1920x Hz PC6 Sngle 1920x Hz PC6 Sngle 2048x Hz PC6 Sngle 2560x Hz PC6 Sngle 2560x Hz PC3 connued... March 2015 Daashee Volume 1 of 2 Order No.:

60 Processor Power Managemen Number of Dsplays 1 Nave Resoluon Deepes Avalable Package C- Sae Sngle 2880x Hz PC3 Sngle 2880x Hz PC3 Sngle 3200x Hz PC3 Sngle 3200x Hz PC3 Sngle 3840x Hz PC3 Sngle 3840x Hz PC3 Sngle 4096x Hz PC3 Mulple 800x Hz PC6 Mulple 1024x Hz PC6 Mulple 1280x Hz PC6 Mulple 1920x Hz PC3 Mulple 1920x Hz PC3 Mulple 1920x Hz PC3 Mulple 2048x Hz PC3 Mulple 2560x Hz PC2 Mulple 2560x Hz PC2 Mulple 2880x Hz PC2 Mulple 2880x Hz PC2 Mulple 3200x Hz PC2 Mulple 3200x Hz PC2 Mulple 3840x Hz PC2 Mulple 3840x Hz PC2 Mulple 4096x Hz PC2 Noes: 1. For mulple dsplay cases, he resoluon lsed s he hghes nave resoluon of all enabled dsplays, and PSR s nernally dsabled; ha s, dual dsplay wh one 800x Hz dsplay and one 2560x Hz dsplay wll resul n a deepes avalable package C-sae of PC2. 2. Mcrocode Updae rev or newer mus be used. 4.3 Inegraed Memory Conroller (IMC) Power Managemen The man memory s power managed durng normal operaon and n low-power ACPI Cx saes Dsablng Unused Sysem Memory Oupus Any sysem memory (SM) nerface sgnal ha goes o a memory module connecor n whch s no conneced o any acual memory devces (such as SO-DIMM connecor s unpopulaed, or s sngle-sded) s r-saed. The benefs of dsablng unused SM sgnals are: Reduced power consumpon. Daashee Volume 1 of 2 March Order No.:

61 Power Managemen Processor Reduced possble overshoo/undershoo sgnal qualy ssues seen by he processor I/O buffer recevers caused by reflecons from poenally unermnaed ransmsson lnes. When a gven rank s no populaed, he correspondng chp selec and CKE sgnals are no drven. A rese, all rows mus be assumed o be populaed, unl can be deermned ha he rows are no populaed. Ths s due o he fac ha when CKE s r-saed wh an SO-DIMM presen, he SO-DIMM s no ensured o manan daa negry. CKE r-sae should be enabled by IOS where approprae, snce a rese all rows mus be assumed o be populaed DRAM Power Managemen and Inalzaon The processor mplemens exensve suppor for power managemen on he SDRAM nerface. There are four SDRAM operaons assocaed wh he Clock Enable (CKE) sgnals, whch he SDRAM conroller suppors. The processor drves four CKE pns o perform hese operaons. The CKE s one of he power save means. When CKE s off, he nernal DDR clock s dsabled and he DDR power s reduced. The power savng dffers accordng o he seleced mode and he DDR ype used. For more nformaon, refer o he IDD able n he DDR specfcaon. The processor suppors hree dfferen ypes of power-down modes n package C0. The dfferen power-down modes can be enabled hrough confgurng "PM_PDWN_confg_0_0_0_MCHAR". The ype of CKE power-down can be confgured hrough PDWN_mode (bs 15:12) and he dle mer can be confgured hrough PDWN_dle_couner (bs 11:0). The dfferen power-down modes suppored are: No power-down (CKE dsable) Acve power-down (APD): Ths mode s enered f here are open pages when de-asserng CKE. In hs mode he open pages are reaned. Power-savng n hs mode s he lowes. Power consumpon of DDR s defned by IDD3P. Exng hs mode s defned by XP small number of cycles. For hs mode, DRAM DLL mus be on. PPD/DLL-off: In hs mode he daa-n DLLs on DDR are off. Power-savng n hs mode s he bes among all power modes. Power consumpon s defned by IDD2P1. Exng hs mode s defned by XP, bu also XPDLL (10 20 accordng o DDR ype) cycles unl frs daa ransfer s allowed. For hs mode, DRAM DLL mus be off. The CKE s deermned per rank, whenever s nacve. Each rank has an dlecouner. The dle-couner sars counng as soon as he rank has no accesses, and f expres, he rank may ener power-down whle no new ransacons o he rank arrves o queues. The dle-couner begns counng a he las ncomng ransacon arrval. I s mporan o undersand ha snce he power-down decson s per rank, he IMC can fnd many opporunes o power down ranks, even whle runnng memory nensve applcaons; he savngs are sgnfcan (may be few Was, accordng o he DDR specfcaon). Ths s sgnfcan when each channel s populaed wh more ranks. March 2015 Daashee Volume 1 of 2 Order No.:

62 Processor Power Managemen Selecon of power modes should be accordng o power-performance or hermal rade-offs of a gven sysem: When ryng o acheve maxmum performance and power or hermal consderaon s no an ssue use no power-down In a sysem whch res o mnmze power-consumpon, ry usng he deepes power-down mode possble PPD/DLL-off wh a low dle mer value. In hgh-performance sysems wh dense packagng (ha s, rcky hermal desgn) he power-down mode should be consdered n order o reduce he heang and avod DDR hrolng caused by he heang. The defaul value ha IOS confgures n "PM_PDWN_confg_0_0_0_MCHAR" s 6080h; ha s, PPD/DLL-off mode wh dle mer of 80h, or 128 DCLKs. Ths s a balanced seng wh deep power-down mode and moderae dle mer value. The dle mer expraon coun defnes he number of DCKLs ha a rank s dle ha causes enry o he seleced power mode. As hs mer s se o a shorer me, he IMC wll have more opporunes o pu DDR n power-down. There s no IOS hook o se hs regser. Cusomers choosng o change he value of hs regser can do by changng n he IOS. For expermens, hs regser can be modfed n real me f IOS does no lock he IMC regsers Inalzaon Role of CKE Durng power-up, CKE s he only npu o he SDRAM ha has s level recognzed (oher han he DDR3/DDR3L rese pn) once power s appled. I mus be drven LOW by he DDR conroller o make sure he SDRAM componens floa DQ and DQS durng power-up. CKE sgnals reman LOW (whle any rese s acve) unl he IOS wres o a confguraon regser. Usng hs mehod, CKE s ensured o reman nacve for much longer han he specfed 200 mcro-seconds afer power and clocks o SDRAM devces are sable Condonal Self-Refresh Durng S0 dle sae, sysem memory may be condonally placed no self-refresh sae when he processor s n package C3 or deeper power sae. Refer o Inel Rapd Memory Power Managemen (Inel RMPM) for more deals on condonal selfrefresh wh Inel HD Graphcs enabled. When enerng he S3 Suspend-o-RAM (STR) sae or S0 condonal self-refresh, he processor core flushes pendng cycles and hen eners SDRAM ranks ha are no used by Inel graphcs memory no self-refresh. The CKE sgnals reman LOW so he SDRAM devces perform self-refresh. The arge behavor s o ener self-refresh for package C3 or deeper power saes as long as here are no memory requess o servce Dynamc Power-Down Dynamc power-down of memory s employed durng normal operaon. ased on dle condons, a gven memory rank may be powered down. The IMC mplemens aggressve CKE conrol o dynamcally pu he DRAM devces n a power-down sae. The processor core conroller can be confgured o pu he devces n acve powerdown (CKE de-asseron wh open pages) or pre-charge power-down (CKE de- Daashee Volume 1 of 2 March Order No.:

63 Power Managemen Processor asseron wh all pages closed). Pre-charge power-down provdes greaer power savngs, bu has a bgger performance mpac snce all pages wll frs be closed before pung he devces n power-down mode. If dynamc power-down s enabled, all ranks are powered up before dong a refresh cycle and all ranks are powered down a he end of refresh DRAM I/O Power Managemen Unused sgnals should be dsabled o save power and reduce elecromagnec nerference. Ths ncludes all sgnals assocaed wh an unused memory channel. Clocks, CKE, ODE, and CS sgnals are conrolled per DIMM rank and wll be powered down for unused ranks. The I/O buffer for an unused sgnal should be r-saed (oupu drver dsabled), he npu recever (dfferenal sense-amp) should be dsabled, and any DLL crcury relaed ONLY o unused sgnals should be dsabled. The npu pah mus be gaed o preven spurous resuls due o nose on he unused sgnals (ypcally handled auomacally when npu recever s dsabled) DRAM Runnng Average Power Lmaon (RAPL) RAPL s a power and me consan par. DRAM RAPL defnes an average power consran for he DRAM doman. Consran s conrolled by he PCU. Plaform enes (PECI or n-band power drver) can specfy a power lm for he DRAM doman. PCU connuously monors he exan of DRAM hrolng due o he power lm and rebudges he lm beween DIMMs DDR Elecrcal Power Gang (EPG) The DDR I/O of he processor suppors Elecrcal Power Gang (DDR-EPG) whle he processor s a C3 or deeper power sae. In C3 or deeper power sae, he processor nernally gaes V DDQ for he majory of he logc o reduce dle power whle keepng all crcal DDR pns such as SM_DRAMRST#, CKE and VREF n he approprae sae. In C7, he processor nernally gaes V CCIO_TERM for all non-crcal sae o reduce dle power. In S3 or C-sae ransons, he DDR does no go hrough ranng mode and wll resore he prevous ranng nformaon. 4.4 PCI Express* Power Managemen Acve power managemen s suppored usng L0s, and L1 saes. All npus and oupus dsabled n L2/L3 Ready sae. 4.5 Drec Meda Inerface (DMI) Power Managemen Acve power managemen s suppored usng L0s/L1 sae. March 2015 Daashee Volume 1 of 2 Order No.:

64 Processor Power Managemen Graphcs Power Managemen Inel Rapd Memory Power Managemen (Inel RMPM) Inel Rapd Memory Power Managemen (Inel RMPM) condonally places memory no self-refresh when he processor s n package C3 or deeper power sae o allow he sysem o reman n he lower power saes longer for memory no reserved for graphcs memory. Inel RMPM funconaly depends on graphcs/dsplay sae (relevan only when processor graphcs s beng used), as well as memory raffc paerns generaed by oher conneced I/O devces Graphcs Render C-Sae Render C-sae (RC6) s a echnque desgned o opmze he average power o he graphcs render engne durng mes of dleness. RC6 s enered when he graphcs render engne, bler engne, and he vdeo engne have no workload beng currenly worked on and no ousandng graphcs memory ransacons. When he dleness condon s me, he processor graphcs wll program he graphcs render engne nernal power ral no a low volage sae Inel Graphcs Dynamc Frequency Inel Graphcs Dynamc Frequency Technology s he ably of he processor and graphcs cores o opporunscally ncrease frequency and/or volage above he guaraneed processor and graphcs frequency for he gven par. Inel Graphcs Dynamc Frequency Technology s a performance feaure ha makes use of unused package power and hermals o ncrease applcaon performance. The ncrease n frequency s deermned by how much power and hermal budge s avalable n he package, and he applcaon demand for addonal processor or graphcs performance. The processor core conrol s mananed by an embedded conroller. The graphcs drver dynamcally adjuss beween P-Saes o manan opmal performance, power, and hermals. The graphcs drver wll always ry o place he graphcs engne n he mos energy effcen P-sae. Daashee Volume 1 of 2 March Order No.:

65 Thermal Managemen Processor 5.0 Thermal Managemen Ths chaper provdes boh componen-level and sysem-level hermal managemen. Topcs covered nclude processor hermal specfcaons, hermal profles, hermal merology, fan speed conrol, adapve hermal monor, THERMTRIP# sgnal, Dgal Thermal Sensor (DTS), Inel Turbo oos Technology, package power conrol, power plane conrol, and urbo me parameer. The processor requres a hermal soluon o manan emperaures whn s operang lms. Any aemp o operae he processor ousde hese operang lms may resul n permanen damage o he processor and poenally oher componens whn he sysem. Mananng he proper hermal envronmen s key o relable, long-erm sysem operaon. A complee soluon ncludes boh componen and sysem level hermal managemen feaures. Componen level hermal soluons can nclude acve or passve heasnks aached o he processor negraed hea spreader (IHS). To allow he opmal operaon and long-erm relably of Inel processor-based sysems, he processor mus reman whn he mnmum and maxmum case emperaure (T CASE ) specfcaons as defned by he applcable hermal profle. Thermal soluons no desgned o provde hs level of hermal capably may affec he long-erm relably of he processor and sysem. The processors mplemen a mehodology for managng processor emperaures ha s nended o suppor acousc nose reducon hrough fan speed conrol and o assure processor relably. Selecon of he approprae fan speed s based on he relave emperaure daa repored by he processor s Dgal Temperaure Sensor (DTS). The DTS can be read usng he Plaform Envronmen Conrol Inerface (PECI) as descrbed n Processor Temperaure on page 78. Alernavely, when PECI s monored by he PCH, he processor emperaure can be read from he PCH usng he SMus proocol defned n Embedded Conroller Suppor Provded by he PCH. The emperaure repored over PECI s always a negave value and represens a dela below he onse of hermal conrol crcu (TCC) acvaon, as ndcaed by PROCHOT# (see Processor Temperaure on page 78). Sysems ha mplemen fan speed conrol mus be desgned o use hs daa. Sysems ha do no aler he fan speed only need o ensure he case emperaure mees he hermal profle specfcaons. Analyss ndcaes ha real applcaons are unlkely o cause he processor o consume maxmum power dsspaon for susaned me perods. Inel recommends ha complee hermal soluon desgns arge he Thermal Desgn Power (TDP), nsead of he maxmum processor power consumpon. The Adapve Thermal Monor feaure s nended o help proec he processor n he even ha an applcaon exceeds he TDP recommendaon for a susaned me perod. For more deals on hs feaure, see Adapve Thermal Monor on page 78. To ensure maxmum flexbly for fuure processors, sysems should be desgned o he Thermal Soluon Capably gudelnes, even f a processor wh lower power dsspaon s currenly planned. March 2015 Daashee Volume 1 of 2 Order No.:

66 Processor Thermal Managemen Table 21. Deskop Processor Thermal Specfcaons Produc PCG 8 Max Power Packag e C1E (W) 1, 2, 5, 9 Max Power Packag e C3 (W) 1, 3, 5, 9 Mn Power Package C3 (W) 9 Max Power Packag e C6 (W) 1, 4, 5, 9 Max Power Package C7 (W) 1, 4, 5, 9 Mn Power Package C6/C7 (W) 9 TTV Thermal Desgn Power (W) 6, 7, 10 Mn T CASE ( C) Max TTV T CASE ( C) Quad Core Processor wh Graphcs 2013D and Processo r (PCG 2013D and PCG 2014) Thermal Profle on page 68 Quad Core Processor wh Graphcs Dual Core Processor wh Graphcs Quad Core Processor wh Graphcs 2013C C Processo r (PCG 2013C) Thermal Profle on page 69 Processo r (PCG 2013C) Thermal Profle on page 69 Processo r (PCG 2013) Thermal Profle on page 70 Quad Core Processor wh Graphcs 2013A Processo r (PCG 2013A) Thermal connued... Daashee Volume 1 of 2 March Order No.:

67 Thermal Managemen Processor Produc PCG 8 Max Power Packag e C1E (W) 1, 2, 5, 9 Max Power Packag e C3 (W) 1, 3, 5, 9 Mn Power Package C3 (W) 9 Max Power Packag e C6 (W) 1, 4, 5, 9 Max Power Package C7 (W) 1, 4, 5, 9 Mn Power Package C6/C7 (W) 9 TTV Thermal Desgn Power (W) 6, 7, 10 Mn T CASE ( C) Max TTV T CASE ( C) Dual Core Processor wh Graphcs Profle on page 72 Noes: 1. The package C-sae power s he wors case power n he sysem confgured as follows: a. Memory confgured for DDR and populaed wh wo DIMMs per channel. b. DMI and PCIe lnks are a L1. 2. Specfcaon a DTS = 50 C and mnmum volage loadlne. 3. Specfcaon a DTS = 50 C and mnmum volage loadlne. 4. Specfcaon a DTS = 35 C and mnmum volage loadlne. 5. These DTS values n Noes 2 4 are based on he TCC Acvaon MSR havng a value of 100, see Processor Temperaure on page These values are specfed a V CC_MAX and V NOM for all oher volage rals for all processor frequences. Sysems mus be desgned o ensure he processor s no o be subjeced o any sac V CC and I CC combnaon wheren V CCP exceeds V CCP_MAX a specfed I CCP. See he loadlne specfcaons. 7. Thermal Desgn Power (TDP) should be used for processor hermal soluon desgn arges. TDP s no he maxmum power ha he processor can dsspae. TDP s measured a DTS = -1. TDP s acheved wh he Memory confgured for DDR and 2 DIMMs per channel. 8. Plaform Compably Gude (PCG) (prevously known as FM) provdes a desgn arge for meeng all planned processor frequency requremens. 9. No 100% esed. Specfed by desgn characerzaon. 5.1 Deskop Processor Thermal Profles Ths secon provdes hermal profles for he Deskop processor famles. March 2015 Daashee Volume 1 of 2 Order No.:

68 TTV Case Temperaure ( C) Processor Thermal Managemen Fgure 15. Processor (PCG 2013D and PCG 2014) Thermal Profle Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013D and PCG 2014) T CASE = 0.33 * Power TTV Power (W) See he followng able for dscree pons ha consue he hermal profle. Table 22. Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013D and PCG 2014) Power (W) T CASE_MAX ( C) Power (W) T CASE_MAX ( C) Power (W) T CASE_MAX ( C) Y = 0.33 * Power connued connued connued... Daashee Volume 1 of 2 March Order No.:

69 Thermal Managemen Processor Power (W) T CASE_MAX ( C) Processor (PCG 2013C) Thermal Profle Fgure 16. Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013C) See he followng able for dscree pons ha consue he hermal profle. Table 23. Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013C) Power (W) T CASE_MAX ( C) Power (W) T CASE_MAX ( C) Y = 0.41 * Power connued... connued... March 2015 Daashee Volume 1 of 2 Order No.:

70 Processor Thermal Managemen Power (W) T CASE_MAX ( C) Processor (PCG 2013) Thermal Profle Fgure 17. Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013) See he followng able for dscree pons ha consue he hermal profle. Daashee Volume 1 of 2 March Order No.:

71 Thermal Managemen Processor Table 24. Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013) Power (W) T CASE_MAX ( C) Y = 0.51 * Power March 2015 Daashee Volume 1 of 2 Order No.:

72 Processor Thermal Managemen Processor (PCG 2013A) Thermal Profle Fgure 18. Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013A) See he followng able for dscree pons ha consue he hermal profle. Table 25. Thermal Tes Vehcle Thermal Profle for Processor (PCG 2013A) Power (W) T CASE_MAX ( C) Power (W) T CASE_MAX ( C) Y = 0.51 * Power connued... Daashee Volume 1 of 2 March Order No.:

73 Thermal Managemen Processor 5.2 Thermal Merology The maxmum Thermal Tes Vehcle (TTV) case emperaures (T CASE-MAX ) can be derved from he daa n he approprae TTV hermal profle earler n hs chaper. The TTV T CASE s measured a he geomerc op cener of he TTV negraed hea spreader (IHS). The followng fgure llusraes he locaon where T CASE emperaure measuremens should be made. Fgure 19. Thermal Tes Vehcle (TTV) Case Temperaure (T CASE ) Measuremen Locaon Measure T CASE a he geomerc cener of he package Noe: 5.3 THERM-X OF CALIFORNIA can machne he groove and aach a hermocouple o he IHS. The suppler s subjec o change whou noce. THERM-X OF CALIFORNIA, 1837 Whpple Road, Hayward, Ca Erneso Valenca Ex. 242 [email protected]. The vendor par number s XTMS1565. Fan Speed Conrol Scheme wh Dgal Thermal Sensor (DTS) 1.1 To correcly use DTS 1.1, he desgner mus frs selec a wors case scenaro T AMIENT, and ensure ha he Fan Speed Conrol (FSC) can provde a Ψ CA ha s equvalen or greaer han he Ψ CA specfcaon. The DTS 1.1 mplemenaon consss of wo pons: a Ψ CA a T CONTROL and a Ψ CA a DTS = -1. March 2015 Daashee Volume 1 of 2 Order No.:

74 Processor Thermal Managemen The Ψ CA pon a DTS = -1 defnes he mnmum Ψ CA requred a TDP consderng he wors case sysem desgn T AMIENT desgn pon: Ψ CA = (T CASE-MAX T AMIENT-TARGET ) / TDP For example, for a 95 W TDP par, he T case maxmum s 72.6 C and a a wors case desgn pon of 40 C local amben hs wll resul n: Ψ CA = ( ) / 95 = 0.34 C/W Smlarly for a sysem wh a desgn arge of 45 C amben, he Ψ CA a DTS = -1 needed wll be 0.29 C/W. The second pon defnes he hermal soluon performance (Ψ CA ) a T CONTROL. The followng able lss he requred Ψ CA for he varous TDP processors. These wo pons defne he operaonal lms for he processor for DTS 1.1 mplemenaon. A T CONTROL he fan speed mus be programmed such ha he resulng Ψ CA s beer han or equvalen o he requred Ψ CA lsed n he followng able. Smlarly, he fan speed should be se a DTS = -1 such ha he hermal soluon performance s beer han or equvalen o he Ψ CA requremens a T AMIENT- MAX. The fan speed conroller mus lnearly ramp he fan speed from processor DTS = T CONTROL o processor DTS = -1. Fgure 20. Dgal Thermal Sensor (DTS) 1.1 Defnon Pons Daashee Volume 1 of 2 March Order No.:

75 Thermal Managemen Processor Table 26. Dgal Thermal Sensor (DTS) 1.1 Thermal Soluon Performance Above T CONTROL Processor TDP Ψ CA a DTS = T CONTROL 1, 2 A Sysem T AMIENT- MAX = 30 C Ψ CA a DTS = -1 A Sysem T AMIENT-MAX = 40 C Ψ CA a DTS = -1 A Sysem T AMIENT-MAX = 45 C Ψ CA a DTS = -1 A Sysem T AMIENT- MAX = 50 C 88 W W W W W Noes: 1. Ψ CA a "DTS = T CONTROL " s applcable o sysems ha have an nernal T RISE (T ROOM emperaure o Processor coolng fan nle) of less han 10 C. In case he expeced T RISE s greaer han 10 C, a correcon facor should be used as explaned below. For each 1 C T RISE above 10 C, he correcon facor (CF) s defned as CF = 1.7 / (processor TDP) 2. Example: A chasss T RISE assumpon s 12 C for a 95 W TDP processor: CF = 1.7 / 95 W = /W For T RISE > 10 C Ψ CA a T CONTROL = (Value provde n Column 2) (T RISE 10) * CF Ψ CA = (12 10) * = C/W In hs case, he fan speed should be se slghly hgher, equvalen o Ψ CA = C/W 5.4 Fan Speed Conrol Scheme wh Dgal Thermal Sensor (DTS) 2.0 To smplfy processor hermal specfcaon complance, he processor calculaes he DTS Thermal Profle from T CONTROL Offse, TCC Acvaon Temperaure, TDP, and he Thermal Margn Slope provded n he followng able. Noe: TCC Acvaon Offse s 0 for he processors. Usng he DTS Thermal Profle, he processor can calculae and repor he Thermal Margn, where a value less han 0 ndcaes ha he processor needs addonal coolng, and a value greaer han 0 ndcaes ha he processor s suffcenly cooled. Refer o he processor Thermal Mechancal Desgn Gudelnes (TMDG) for addonal nformaon (see Relaed Documens). March 2015 Daashee Volume 1 of 2 Order No.:

76 Processor Thermal Managemen Fgure 21. Dgal Thermal Sensor (DTS) Thermal Profle Defnon Table 27. Thermal Margn Slope PCG De Confguraon (Nave) Core + GT TDP (W) TCC Acvaon Temperaure ( C) MSR 1A2h 23:16 Temperaure Conrol Offse MSR 1A2h 15:8 Thermal Margn Slope ( C / W) (4+2) D 4+2 (4+2) (4+2) (4+2) C 2+2 (2+2) (2+2) (4+2) (4+2) A 2+2 (4+2) (2+2) (2+2) Thermal Specfcaons Ths secon provdes hermal specfcaons (Thermal Profle) and desgn gudelnes for enabled hermal soluons o cool he processor. Daashee Volume 1 of 2 March Order No.:

77 Thermal Managemen Processor Performance Targes The followng able provdes boundary condons and performance arges as gudance for hermal soluon desgn. Thermal soluons mus be able o comply wh he Maxmum T CASE Thermal Profle. Table 28. oundary Condons, Performance Targes, and T CASE Specfcaons Processor PCG 2 Package TDP Plaform TDP Heasnk 3 T LA, Arflow, RPM, Ѱ CA 4 Maxmum T CASE Thermal Profle 5 T Plaform TDP 6 Deskop 4C/GT2 95W W 88W Acve Cu Core (DHA-A) 40 C, 3100 RPM, C/W y = 0.33 * Power C 4C/GT2 95W D 84W 84W Acve Cu Core (DHA-A) 40 C, 3100 RPM, C/W y = 0.33 * Power C 4C/GT2 65W 1 65W 65W Acve Al Core (DHA-) 40 C, 3100 RPM, C/W y = 0.41 * Power C 2C/GT2 65W C 54W 54W Acve Al Core (DHA-) 40 C, 3100 RPM, C/W y = 0.41 * Power C 2C/GT1 65W 1 53W 53W Acve Al Core (DHA-) 40 C, 3100 RPM, C/W y = 0.41 * Power C 4C/GT2 45W 1 45W 45W Acve Shor (DHA-D) 45 C, 3000 RPM, C/W y = 0.51 * Power C 4C/GT2 35W W 35W Acve Shor (DHA-D) 45 C, 3000 RPM, C/W y = 0.51 * Power C 2C/GT2 35W 1 35W 35W Acve Shor (DHA-D) 45 C, 3000 RPM, C/W y = 0.51 * Power C Noes: 1. TDP shown here, 95W for example, represens he maxmum expeced plaform TDP n he nex generaon plaform for hs ype of SKU. Ths placeholder value s provded as a gudelne for hardware desgn for he nex generaon plaform. 2. Plaform Compably Gude (PCG) provdes a desgn arge for meeng all planned processor frequency requremens. For more nformaon, refer o Volage and Curren Specfcaons on page N/A 4. These boundary condons and performance arges are used o generae processor hermal specfcaons and o provde gudance for heasnk desgn. Values are for he heasnk shown n he adjacen column are calculaed a sea level, and are expeced o mee he Thermal Profle a TDP. T LA s he local amben emperaure of he heasnk nle ar. Arflow s hrough he heasnk fns wh zero bypass for a passve heasnk. RPM s fan revoluons per mnue for an acve heasnk. Ѱ CA s he maxmum arge (mean + 3 sgma) for he hermal characerzaon parameer. For more nformaon on he hermal characerzaon parameer, refer o he processor Thermal Mechancal Desgn Gudelnes (see Relaed Documens secon). 5. Maxmum T CASE Thermal Profle s he specfcaon ha mus be compled o. Any Aemp o operae he processor ousde hese operang lms may resul n permanen damage o he processor and poenally oher sysem componens. 6. T CASE-MAX a Plaform TDP s calculaed usng he maxmum T CASE Thermal Profle and he plaform TDP. 7. ATCA Reference Heasnk suppors Socke and s no ooled for Socke H. March 2015 Daashee Volume 1 of 2 Order No.:

78 Processor Thermal Managemen 5.6 Processor Temperaure A sofware readable feld n he TEMPERATURE_TARGET regser conans he mnmum emperaure a whch he TCC wll be acvaed and PROCHOT# wll be assered. The TCC acvaon emperaure s calbraed on a par-by-par bass and normal facory varaon may resul n he acual TCC acvaon emperaure beng hgher han he value lsed n he regser. TCC acvaon emperaures may change based on processor seppng, frequency or manufacurng effcences. 5.7 Adapve Thermal Monor The Adapve Thermal Monor feaure provdes an enhanced mehod for conrollng he processor emperaure when he processor slcon exceeds he Thermal Conrol Crcu (TCC) acvaon emperaure. Adapve Thermal Monor uses TCC acvaon o reduce processor power usng a combnaon of mehods. The frs mehod (Frequency conrol, smlar o Thermal Monor 2 (TM2) n prevous generaon processors) nvolves he processor reducng s operang frequency (usng he core rao mulpler) and nernal core volage. Ths combnaon of lower frequency and core volage resuls n a reducon of he processor power consumpon. The second mehod (clock modulaon, known as Thermal Monor 1 or TM1 n prevous generaon processors) reduces power consumpon by modulang (sarng and soppng) he nernal processor core clocks. The processor nellgenly selecs he approprae TCC mehod o use on a dynamc bass. IOS s no requred o selec a specfc mehod (as wh prevous-generaon processors supporng TM1 or TM2). The emperaure a whch Adapve Thermal Monor acvaes he Thermal Conrol Crcu s facory calbraed and s no user confgurable. Snoopng and nerrup processng are performed n he normal manner whle he TCC s acve. When he TCC acvaon emperaure s reached, he processor wll nae TM2 n aemp o reduce s emperaure. If TM2 s unable o reduce he processor emperaure, TM1 wll be also be acvaed. TM1 and TM2 wll work ogeher (clocks wll be modulaed a he lowes frequency rao) o reduce power dsspaon and emperaure. Wh a properly desgned and characerzed hermal soluon, s ancpaed ha he TCC wll only be acvaed for very shor perods of me when runnng he mos power nensve applcaons. The processor performance mpac due o hese bref perods of TCC acvaon s expeced o be so mnor ha would be mmeasurable. An underdesgned hermal soluon ha s no able o preven excessve acvaon of he TCC n he ancpaed amben envronmen may cause a noceable performance loss, and n some cases may resul n a T CASE ha exceeds he specfed maxmum emperaure and may affec he long-erm relably of he processor. In addon, a hermal soluon ha s sgnfcanly under desgned may no be capable of coolng he processor even when he TCC s acve connuously. See he approprae processor Thermal Mechancal Desgn Gudelnes for nformaon on desgnng a complan hermal soluon. The Thermal Monor does no requre any addonal hardware, sofware drvers, or nerrup handlng rounes. The followng secons provde more deals on he dfferen TCC mechansms used by he processor. Daashee Volume 1 of 2 March Order No.:

79 Thermal Managemen Processor Frequency Conrol When he Dgal Temperaure Sensor (DTS) reaches a value of 0 (DTS emperaures repored usng PECI may no equal zero when PROCHOT# s acvaed), he TCC wll be acvaed and he PROCHOT# sgnal wll be assered f confgured as b-dreconal. Ths ndcaes he processor emperaure has me or exceeded he facory calbraed rp emperaure and wll ake acon o reduce he emperaure. Upon acvaon of he TCC, he processor wll sop he core clocks, reduce he core rao mulpler by 1 rao and resar he clocks. All processor acvy sops durng hs frequency ranson ha occurs whn 2 us. Once he clocks have been resared a he new lower frequency, processor acvy resumes whle he core volage s reduced by he nernal volage regulaor. Runnng he processor a he lower frequency and volage wll reduce power consumpon and should allow he processor o cool off. If afer 1 ms he processor s sll oo ho (he emperaure has no dropped below he TCC acvaon pon, DTS sll = 0 and PROCHOT s sll acve), hen a second frequency and volage ranson wll ake place. Ths sequence of emperaure checkng and frequency and volage reducon wll connue unl eher he mnmum frequency has been reached or he processor emperaure has dropped below he TCC acvaon pon. If he processor emperaure remans above he TCC acvaon pon even afer he mnmum frequency has been reached, hen clock modulaon (descrbed below) a ha mnmum frequency wll be naed. There s no end user sofware or hardware mechansm o nae hs auomaed TCC acvaon behavor. A small amoun of hyseress has been ncluded o preven rapd acve/nacve ransons of he TCC when he processor emperaure s near he TCC acvaon emperaure. Once he emperaure has dropped below he rp emperaure and he hyseress mer has expred, he operang frequency and volage ranson back o he normal sysem operang pon usng he nermedae VID/frequency pons. Transon of he VID code wll occur frs, o nsure proper operaon as he frequency s ncreased. Clock Modulaon Clock modulaon s a second mehod of hermal conrol avalable o he processor. Clock modulaon s performed by rapdly urnng he clocks off and on a a duy cycle ha should reduce power dsspaon by abou 50% (ypcally a 30 50% duy cycle). Clocks ofen wll no be off for more han 32 mcroseconds when he TCC s acve. Cycle mes are ndependen of processor frequency. The duy cycle for he TCC, when acvaed by he Thermal Monor, s facory confgured and canno be modfed. I s possble for sofware o nae clock modulaon wh confgurable duy cycles. A small amoun of hyseress has been ncluded o preven rapd acve/nacve ransons of he TCC when he processor emperaure s near s maxmum operang emperaure. Once he emperaure has dropped below he maxmum operang emperaure and he hyseress mer has expred, he TCC goes nacve and clock modulaon ceases. March 2015 Daashee Volume 1 of 2 Order No.:

80 Processor Thermal Managemen Immedae Transon o Combned TM1 and TM2 When he TCC s acvaed, he processor wll sequenally sep down he rao mulplers and VIDs n an aemp o reduce he slcon emperaure. If he emperaure connues o ncrease and exceeds he TCC acvaon emperaure by approxmaely 5 C before he lowes rao/vid combnaon has been reached, he processor wll mmedaely ranson o he combned TM1/TM2 condon. The processor remans n hs sae unl he emperaure has dropped below he TCC acvaon pon. Once below he TCC acvaon emperaure, TM1 wll be dsconnued and TM2 wll be exed by seppng up o he approprae rao/vid sae. Crcal Temperaure Flag If TM2 s unable o reduce he processor emperaure, hen TM1 wll be also be acvaed. TM1 and TM2 wll hen work ogeher o reduce power dsspaon and emperaure. I s expeced ha only a caasrophc hermal soluon falure would creae a suaon where boh TM1 and TM2 are acve. If TM1 and TM2 have boh been acve for greaer han 20 ms and he processor emperaure has no dropped below he TCC acvaon pon, he Crcal Temperaure Flag n he IA32_THERM_STATUS MSR wll be se. Ths flag s an ndcaor of a caasrophc hermal soluon falure and ha he processor canno reduce s emperaure. Unless mmedae acon s aken o resolve he falure, he processor wll probably reach he Thermrp emperaure (see Tesably Sgnals on page 91) whn a shor me. To preven possble permanen slcon damage, Inel recommends removng power from he processor whn ½ second of he Crcal Temperaure Flag beng se. PROCHOT# Sgnal An exernal sgnal, PROCHOT# (processor ho), s assered when he processor core emperaure has exceeded s specfcaon. If Adapve Thermal Monor s enabled ( mus be enabled for he processor o be operang whn specfcaon), he TCC wll be acve when PROCHOT# s assered. The processor can be confgured o generae an nerrup upon he asseron or deasseron of PROCHOT#. y defaul, he PROCHOT# sgnal s se o b-dreconal. However, s recommended o confgure he sgnal as an npu only. When confgured as an npu or b-dreconal sgnal, PROCHOT# can be used for hermally proecng oher plaform componens should hey overhea as well. When PROCHOT# s drven by an exernal devce: The package wll mmedaely ranson o he mnmum operaon pons (volage and frequency) suppored by he processor and graphcs cores. Ths s conrary o he nernally-generaed Adapve Thermal Monor response. Clock modulaon s no acvaed. The TCC wll reman acve unl he sysem de-assers PROCHOT#. The processor can be confgured o generae an nerrup upon asseron and de-asseron of he PROCHOT# sgnal. Refer o he approprae Plaform Thermal Mechancal Desgn Gudelnes (see Relaed Doucmens secon) for deals on mplemenng he bdreconal PROCHOT# feaure. Noe: Togglng PROCHOT# more han once n 1.5 ms perod wll resul n consan Pn sae of he processor. Daashee Volume 1 of 2 March Order No.:

81 Thermal Managemen Processor Noe: A corner case exss for PROCHOT# confgured as a b-dreconal sgnal ha can cause several mllseconds of delay o a sysem asseron of PROCHOT# when he oupu funcon s assered. As an oupu, PROCHOT# (Processor Ho) wll go acve when he processor emperaure monorng sensor deecs ha one or more cores has reached s maxmum safe operang emperaure. Ths ndcaes ha he processor Thermal Conrol Crcu (TCC) has been acvaed, f enabled. As an npu, asseron of PROCHOT# by he sysem wll acvae he TCC for all cores. TCC acvaon when PROCHOT# s assered by he sysem wll resul n he processor mmedaely ransonng o he mnmum frequency and correspondng volage (usng Frequency conrol). Clock modulaon s no acvaed n hs case. The TCC wll reman acve unl he sysem de-assers PROCHOT#. Use of PROCHOT# n npu or b-dreconal mode can allow VR hermal desgns o arge maxmum susaned curren nsead of maxmum curren. Sysems should sll provde proper coolng for he Volage Regulaor (VR), and rely on PROCHOT# only as a backup n case of sysem coolng falure. The sysem hermal desgn should allow he power delvery crcury o operae whn s emperaure specfcaon even whle he processor s operang a s Thermal Desgn Power. 5.8 THERMTRIP# Sgnal Regardless of wheher or no Adapve Thermal Monor s enabled, n he even of a caasrophc coolng falure, he processor wll auomacally shu down when he slcon has reached an elevaed emperaure (refer o he THERMTRIP# defnon n Error and Thermal Proecon Sgnals on page 92). THERMTRIP# acvaon s ndependen of processor acvy. The emperaure a whch THERMTRIP# assers s no user confgurable and s no sofware vsble. 5.9 Dgal Thermal Sensor Each processor execuon core has an on-de Dgal Thermal Sensor (DTS) ha deecs he core's nsananeous emperaure. The DTS s he preferred mehod of monorng processor de emperaure because: I s locaed near he hoes porons of he de. I can accuraely rack he de emperaure and ensure ha he Adapve Thermal Monor s no excessvely acvaed. Temperaure values from he DTS can be rereved hrough: A sofware nerface usng processor Model Specfc Regser (MSR). A processor hardware nerface as descrbed n Plaform Envronmenal Conrol Inerface (PECI) on page 37. When emperaure s rereved by he processor MSR, s he nsananeous emperaure of he gven core. When emperaure s rereved usng PECI, s he average of he hghes DTS emperaure n he package over a 256 ms me wndow. Inel recommends usng he PECI repored emperaure for plaform hermal conrol ha benefs from averagng, such as fan speed conrol. The average DTS emperaure may no be a good ndcaor of package Adapve Thermal Monor acvaon or rapd ncreases n emperaure ha rggers he Ou of Specfcaon saus b whn he PACKAGE_THERM_STATUS MSR 11h and IA32_THERM_STATUS MSR 19Ch. March 2015 Daashee Volume 1 of 2 Order No.:

82 Processor Thermal Managemen Code execuon s haled n C1 or deeper C-saes. Package emperaure can sll be monored hrough PECI n lower C-saes. Unlke radonal hermal devces, he DTS oupus a emperaure relave o he maxmum suppored operang emperaure of he processor (Tj MAX ), regardless of TCC acvaon offse. I s he responsbly of sofware o conver he relave emperaure o an absolue emperaure. The absolue reference emperaure s readable n he TEMPERATURE_TARGET MSR 1A2h. The emperaure reurned by he DTS s an mpled negave neger ndcang he relave offse from Tj MAX. The DTS does no repor emperaures greaer han Tj MAX. The DTS-relave emperaure readou drecly mpacs he Adapve Thermal Monor rgger pon. When a package DTS ndcaes ha has reached he TCC acvaon (a readng of 0h, excep when he TCC acvaon offse s changed), he TCC wll acvae and ndcae an Adapve Thermal Monor even. A TCC acvaon wll lower boh IA core and graphcs core frequency, volage, or boh. Changes o he emperaure can be deeced usng wo programmable hresholds locaed n he processor hermal MSRs. These hresholds have he capably of generang nerrups usng he core's local APIC. Refer o he Inel 64 and IA-32 Archecures Sofware Developer s Manual for specfc regser and programmng deals Dgal Thermal Sensor Accuracy (Taccuracy) The error assocaed wh DTS measuremens wll no exceed ±5 C whn he enre operang range Inel Turbo oos Technology Thermal Consderaons Inel Turbo oos Technology allows processor cores and negraed graphcs cores o run faser han he baselne frequency. Durng a urbo even, he processor can exceed s TDP power for bref perods. Turbo s nvoked opporunscally and auomacally as long as he processor s conformng o s emperaure, power delvery, and curren specfcaon lms. Thus, hermal soluons and plaform coolng ha are desgned o less han hermal desgn gudance may experence hermal and performance ssues snce more applcaons wll end o run a or near he maxmum power lm for sgnfcan perods of me Inel Turbo oos Technology Power Conrol and Reporng Package processor core and nernal graphcs core powers are self monored and correspondngly repored ou. Wh he processor urbo dsabled, rollng average power over 5 seconds wll no exceed he TDP rang of he par for ypcal applcaons. Wh urbo enabled (see Fgure 22 on page 84) For he PL1: Package rollng average of he power se n POWER_LIMIT_1 (TURO_POWER_LIMIT MSR 0610h bs [14:0]) over me wndow se n POWER_LIMIT_1_TIME (TURO_POWER_LIMIT MSR 0610h bs [23:17]) mus be less han or equal o he TDP package power as read from he PACKAGE_POWER_SKU MSR 0614h for ypcal applcaons. Power conrol s vald only when he processor s operang n urbo. PL1 lower han he package TDP s no guaraneed. For he PL2: Package power wll be conrolled o a value se n POWER_LIMIT_2 (TURO_POWER_LIMIT MSR 0610h bs [46:32]). Occasonal bref power excursons may occur for perods of less han 10 ms over PL2. Daashee Volume 1 of 2 March Order No.:

83 Thermal Managemen Processor The processor monors s own power consumpon o conrol urbo behavor, assumng he followng: The power monor s no 100% esed across all processors. The Power Lm 2 (PL2) conrol s only vald for power levels se a or above TDP and under workloads wh smlar acvy raos as he produc TDP workload. Ths also assumes he processor s workng whn oher produc specfcaons. Seng power lms (PL1 or PL2) below TDP are no ensured o be followed, and are no characerzed for accuracy. Under unknown work loads and unforeseen applcaons he average processor power may exceed Power Lm 1 (PL1). Uncharacerzed workloads may exs ha could resul n hgher urbo frequences and power. If ha were o happen, he processor Thermal Conrol Crcury (TCC) would proec he processor. The TCC proecon mus be enabled by he plaform for he produc o be whn specfcaon. An llusraon of Inel Turbo oos Technology power conrol s shown n he followng secons and fgures. Mulple conrols operae smulaneously allowng for cusomzaon for mulple sysem hermal and power lmaons. These conrols provde urbo opmzaons whn sysem consrans Package Power Conrol The package power conrol allows for cusomzaon o mplemen opmal urbo whn plaform power delvery and package hermal soluon lmaons. March 2015 Daashee Volume 1 of 2 Order No.:

84 Processor Thermal Managemen Table 29. MSR: Address: Inel Turbo oos Technology 2.0 Package Power Conrol Sengs MSR_TURO_POWER_LIMIT 610h Conrol Defaul Descrpon POWER_LIMIT_1 (PL1) 14:0 SKU TDP Ths value ses he average power lm over a long me perod. Ths s normally algned o he TDP of he par and seady-sae coolng capably of he hermal soluon. The defaul value s he TDP for he SKU. PL1 lm may be se lower han TDP n real me for specfc needs, such as respondng o a hermal even. If s se lower han TDP, he processor may requre o use frequences below he guaraneed P1 frequency o conrol he low-power lms. The PL1 Clamp b [16] should be se o enable he processor o use frequences below P1 o conrol he sepower lm. PL1 lm may be se hgher han TDP. If se hgher han TDP, he processor could say a ha power level connuously and coolng soluon mprovemens may be requred. POWER_LIMIT_1_TIME (Turbo Tme Parameer) 23:17 1 sec Ths value s a me parameer ha adjuss he algorhm behavor o manan me averaged power a or below PL1. The hardware defaul value s 1 second; however, 28 seconds s recommended for mos moble applcaons. POWER_LIMIT_2 (PL2) 46: x TDP PL2 esablshes he upper power lm of urbo operaon above TDP, prmarly for plaform power supply consderaons. Power may exceed hs lm for up o 10 ms. The defaul for hs lm s 1.25 x TDP; however, he IOS may reprogram he defaul value o maxmze he performance whn plaform power supply consderaons. Seng hs lm o TDP wll lm he processor o only operae up o he TDP. I does no dsable urbo because urbo s opporunsc and power/emperaure dependen. Many workloads wll allow some urbo frequences for powers a or below TDP. Fgure 22. Package Power Conrol Turbo Tme Parameer Turbo Tme Parameer s a mahemacal parameer (uns n seconds) ha conrols he Inel Turbo oos Technology algorhm usng an average of energy usage. Durng a maxmum power urbo even of abou 1.25 x TDP, he processor could susan Power_Lm_2 for up o approxmaely 1.5 he Turbo Tme Parameer. See he approprae processor Thermal Mechancal Desgn Gudelnes for more nformaon (see Relaed Documens secon). If he power value and/or Turbo Tme Parameer s Daashee Volume 1 of 2 March Order No.:

85 Thermal Managemen Processor changed durng runme, may ake a perod of me (possbly up o approxmaely 3 o 5 mes he Turbo Tme Parameer, dependng on he magnude of he change and oher facors) for he algorhm o sele a he new conrol lms. March 2015 Daashee Volume 1 of 2 Order No.:

86 Processor Sgnal Descrpon 6.0 Sgnal Descrpon Ths chaper descrbes he processor sgnals. The sgnals are arranged n funconal groups accordng o he assocaed nerface or caegory. The followng noaons are used o descrbe he sgnal ype. Noaon Sgnal Type I O I/O Inpu pn Oupu pn -dreconal Inpu/Oupu pn The sgnal descrpon also ncludes he ype of buffer used for he parcular sgnal (see he followng able). Table 30. Sgnal Descrpon uffer Types Sgnal PCI Express* DMI CMOS DDR3/DDR3L A GTL Ref Asynchronous 1 Descrpon PCI Express* nerface sgnals. These sgnals are compable wh PCI Express 3.0 Sgnalng Envronmen AC Specfcaons and are AC coupled. The buffers are no 3.3 V- oleran. See he PCI Express ase Specfcaon 3.0. Drec Meda Inerface sgnals. These sgnals are compable wh PCI Express 2.0 Sgnalng Envronmen AC Specfcaons, bu are DC coupled. The buffers are no 3.3 V- oleran. CMOS buffers. 1.05V- oleran DDR3/DDR3L buffers: 1.5 V- oleran Analog reference or oupu. May be used as a hreshold volage or for buffer compensaon Gunnng Transcever Logc sgnalng echnology Volage reference sgnal Sgnal has no mng relaonshp wh any reference clock. 1. Qualfer for a buffer ype. 6.1 Table 31. Sysem Memory Inerface Sgnals Memory Channel A Sgnals Sgnal Name Descrpon Drecon / uffer Type SA_S[2:0] SA_WE# ank Selec: These sgnals defne whch banks are seleced whn each SDRAM rank. Wre Enable Conrol Sgnal: Ths sgnal s used wh SA_RAS# and SA_CAS# (along wh SA_CS#) o defne he SDRAM Commands. O DDR3/DDR3L O DDR3/DDR3L connued... Daashee Volume 1 of 2 March Order No.:

87 Sgnal Descrpon Processor Sgnal Name Descrpon Drecon / uffer Type SA_RAS# SA_CAS# SA_DQS[8:0] SA_DQSN[8:0] SA_DQ[63:0] SA_MA[15:0] SA_CK[3:0] SA_CKE[3:0] SA_CS#[3:0] SA_ODT[3:0] RAS Conrol Sgnal: Ths sgnal s used wh SA_CAS# and SA_WE# (along wh SA_CS#) o defne he SRAM Commands. CAS Conrol Sgnal: Ths sgnal s used wh SA_RAS# and SA_WE# (along wh SA_CS#) o defne he SRAM Commands. Daa Srobes: SA_DQS[8:0] and s complemen sgnal group make up a dfferenal srobe par. The daa s capured a he crossng pon of SA_DQS[8:0] and SA_DQS#[8:0] durng read and wre ransacons. Daa us: Channel A daa sgnal nerface o he SDRAM daa bus. Memory Address: These sgnals are used o provde he mulplexed row and column address o he SDRAM. SDRAM Dfferenal Clock: These sgnals are Channel A SDRAM Dfferenal clock sgnal pars. The crossng of he posve edge of SA_CK and he negave edge of s complemen SA_CK# are used o sample he command and conrol sgnals on he SDRAM. Clock Enable: (1 per rank). These sgnals are used o: Inalze he SDRAMs durng power-up Power-down SDRAM ranks Place all SDRAM ranks no and ou of self-refresh durng STR Chp Selec: (1 per rank). These sgnals are used o selec parcular SDRAM componens durng he acve sae. There s one Chp Selec for each SDRAM rank. On De Termnaon: Acve Termnaon Conrol. O DDR3/DDR3L O DDR3/DDR3L I/O DDR3/DDR3L I/O DDR3/DDR3L O DDR3/DDR3L O DDR3/DDR3L O DDR3/DDR3L O DDR3/DDR3L O DDR3/DDR3L Table 32. Memory Channel Sgnals Sgnal Name Descrpon Drecon / uffer Type S_S[2:0] S_WE# S_RAS# S_CAS# S_DQS[8:0] S_DQSN[8:0] S_DQ[63:0] S_MA[15:0] ank Selec: These sgnals defne whch banks are seleced whn each SDRAM rank. Wre Enable Conrol Sgnal: Ths sgnal s used wh S_RAS# and S_CAS# (along wh S_CS#) o defne he SDRAM Commands. RAS Conrol Sgnal: Ths sgnal s used wh S_CAS# and S_WE# (along wh S_CS#) o defne he SRAM Commands. CAS Conrol Sgnal: Ths sgnal s used wh S_RAS# and S_WE# (along wh S_CS#) o defne he SRAM Commands. Daa Srobes: S_DQS[8:0] and s complemen sgnal group make up a dfferenal srobe par. The daa s capured a he crossng pon of S_DQS[8:0] and s S_DQS#[8:0] durng read and wre ransacons. Daa us: Channel daa sgnal nerface o he SDRAM daa bus. Memory Address: These sgnals are used o provde he mulplexed row and column address o he SDRAM. O DDR3/DDR3L O DDR3/DDR3L O DDR3/DDR3L O DDR3/DDR3L I/O DDR3/DDR3L I/O DDR3/DDR3L O DDR3/DDR3L connued... March 2015 Daashee Volume 1 of 2 Order No.:

88 Processor Sgnal Descrpon Sgnal Name Descrpon Drecon / uffer Type S_CK[3:0] S_CKE[3:0] S_CS#[3:0] S_ODT[3:0] SDRAM Dfferenal Clock: Channel SDRAM Dfferenal clock sgnal par. The crossng of he posve edge of S_CK and he negave edge of s complemen S_CK# are used o sample he command and conrol sgnals on he SDRAM. Clock Enable: (1 per rank). These sgnals are used o: Inalze he SDRAMs durng power-up. Power-down SDRAM ranks. Place all SDRAM ranks no and ou of self-refresh durng STR. Chp Selec: (1 per rank). These sgnals are used o selec parcular SDRAM componens durng he acve sae. There s one Chp Selec for each SDRAM rank. On De Termnaon: Acve Termnaon Conrol. O DDR3/DDR3L O DDR3/DDR3L O DDR3/DDR3L O DDR3/DDR3L 6.2 Table 33. Memory Reference Compensaon Sgnals Memory Reference and Compensaon Sgnals Sgnal Name Descrpon Drecon / uffer Type SM_RCOMP[2:0] SM_VREF SA_DIMM_VREFDQ S_DIMM_VREFDQ Sysem Memory Impedance Compensaon: DDR3/DDR3L Reference Volage: Ths sgnal s used as a reference volage o he DDR3/DDR3L conroller and s defned as V DDQ /2 Memory Channel A/ DIMM DQ Volage Reference: The oupu pns are conneced o he DIMMs, and holds V DDQ /2 as reference volage. I A O DDR3/DDR3L O DDR3/DDR3L Daashee Volume 1 of 2 March Order No.:

89 Sgnal Descrpon Processor 6.3 Table 34. Rese and Mscellaneous Sgnals Rese and Mscellaneous Sgnals Sgnal Name Descrpon Drecon / uffer Type CFG[19:0] CFG_RCOMP FC_x PM_SYNC PWR_DEUG# IST_TRIGGER IVR_ERROR RESET# RSVD RSVD_TP RSVD_NCTF SM_DRAMRST# TESTLO_x Confguraon Sgnals: The CFG sgnals have a defaul value of '1' f no ermnaed on he board. CFG[1:0]: Reserved confguraon lane. A es pon may be placed on he board for hese lanes. CFG[2]: PCI Express* Sac x16 Lane Numberng Reversal. 1 = Normal operaon 0 = Lane numbers reversed. CFG[3]: MSR Prvacy Feaure 1 = Debug capably s deermned by IA32_Debug_Inerface_MSR (C80h) b[0] seng 0 = IA32_Debug_Inerface_MSR (C80h) b[0] defaul seng overrdden CFG[4]: Reserved confguraon lane. A es pon may be placed on he board for hs lane. CFG[6:5]: PCI Express* furcaon: 1 00 = 1 x8, 2 x4 PCI Express* 01 = reserved 10 = 2 x8 PCI Express* 11 = 1 x16 PCI Express* CFG[19:7]: Reserved confguraon lanes. A es pon may be placed on he board for hese lands. Confguraon ressance compensaon. Use a 49.9 Ω ±1% ressor o ground. FC (Fuure Compably) sgnals are sgnals ha are avalable for compably wh oher processors. A es pon may be placed on he board for hese lands. Power Managemen Sync: A sdeband sgnal o communcae power managemen saus from he plaform o he processor. Sgnal s for debug. Sgnal s for IFDIM esng only. Sgnal s for debug. If boh THERMTRIP# and hs sgnal are smulaneously assered, he processor has encounered an unrecoverable power delvery faul and has engaged auomac shudown as a resul. Plaform Rese pn drven by he PCH. RESERVED: All sgnals ha are RSVD and RSVD_NCTF mus be lef unconneced on he board. Inel recommends ha all RSVD_TP sgnals have va es pons. DRAM Rese: Rese sgnal from processor o DRAM devces. One sgnal common o all channels. TESTLO should be ndvdually conneced o V SS hrough a ressor. I/O GTL I CMOS I Asynchronous CMOS I CMOS O CMOS I CMOS No Connec Tes Pon Non-Crcal o Funcon O CMOS Noe: 1. PCIe bfurcaon suppor vares wh he processor and PCH SKUs used. March 2015 Daashee Volume 1 of 2 Order No.:

90 Processor Sgnal Descrpon 6.4 Table 35. PCI Express* Inerface Sgnals PCI Express* Graphcs Inerface Sgnals Sgnal Name Descrpon Drecon / uffer Type PEG_RCOMP PEG_RXP[15:0] PEG_RXN[15:0] PEG_TXP[15:0] PEG_TXN[15:0] PCI Express Ressance Compensaon PCI Express Receve Dfferenal Par PCI Express Transm Dfferenal Par I A I PCI Express O PCI Express 6.5 Table 36. Dsplay Inerface Sgnals Dsplay Inerface Sgnals Sgnal Name Descrpon Drecon / uffer Type FDI_TXP[1:0] FDI_TXN[1:0] DDI_TXP[3:0] DDI_TXN[3:0] DDIC_TXP[3:0] DDIC_TXN[3:0] DDID_TXP[3:0] DDID_TXN[3:0] FDI_CSYNC DISP_INT Inel Flexble Dsplay Inerface Transm Dfferenal Par Dgal Dsplay Inerface Transm Dfferenal Par Dgal Dsplay Inerface Transm Dfferenal Par Dgal Dsplay Inerface Transm Dfferenal Par Inel Flexble Dsplay Inerface Sync Inel Flexble Dsplay Inerface Ho-Plug Inerrup O FDI O FDI O FDI O FDI I CMOS I Asynchronous CMOS 6.6 Table 37. Drec Meda Inerface (DMI) Drec Meda Inerface (DMI) Processor o PCH Seral Inerface Sgnal Name Descrpon Drecon / uffer Type DMI_RXP[3:0] DMI_RXN[3:0] DMI_TXP[3:0] DMI_TXN[3:0] DMI Inpu from PCH: Drec Meda Inerface receve dfferenal par. DMI Oupu o PCH: Drec Meda Inerface ransm dfferenal par. I DMI O DMI Daashee Volume 1 of 2 March Order No.:

91 Sgnal Descrpon Processor 6.7 Table 38. Phase Locked Loop (PLL) Sgnals Phase Locked Loop (PLL) Sgnals Sgnal Name Descrpon Drecon / uffer Type CLKP CLKN DPLL_REF_CLKP DPLL_REF_CLKN SSC_DPLL_REF_CLKP SSC_ DPLL_REF_CLKN Dfferenal bus clock npu o he processor Embedded Dsplay Por PLL Dfferenal Clock In: 135 MHz Spread Specrum Embedded DsplayPor PLL Dfferenal Clock In: 135 MHz I Dff Clk I Dff Clk I Dff Clk 6.8 Table 39. Tesably Sgnals Tesably Sgnals Sgnal Name Descrpon Drecon / uffer Type PM#[7:0] DR# PRDY# PREQ# TCK TDI TDO TMS TRST# reakpon and Performance Monor Sgnals: Oupus from he processor ha ndcae he saus of breakpons and programmable couners used for monorng processor performance. Debug Rese: Ths sgnal s used only n sysems where no debug por s mplemened on he sysem board. DR# s used by a debug por nerposer so ha an narge probe can drve sysem rese. Processor Ready: Ths sgnal s a processor oupu used by debug ools o deermne processor debug readness. Processor Reques: Ths sgnal s used by debug ools o reques debug operaon of he processor. Tes Clock: Ths sgnal provdes he clock npu for he processor Tes us (also known as he Tes Access Por). Ths sgnal mus be drven low or allowed o floa durng power on Rese. Tes Daa In: Ths sgnal ransfers seral es daa no he processor. Ths sgnal provdes he seral npu needed for JTAG specfcaon suppor. Tes Daa Ou: Ths sgnal ransfers seral es daa ou of he processor. Ths sgnal provdes he seral oupu needed for JTAG specfcaon suppor. Tes Mode Selec: Ths s a JTAG specfcaon suppored sgnal used by debug ools. Tes Rese: Ths sgnal reses he Tes Access Por (TAP) logc. Ths sgnal mus be drven low durng power on Rese. I/O GTL O O GTL I GTL I GTL I GTL O Open Dran I GTL I GTL March 2015 Daashee Volume 1 of 2 Order No.:

92 Processor Sgnal Descrpon 6.9 Table 40. Error and Thermal Proecon Sgnals Error and Thermal Proecon Sgnals Sgnal Name Descrpon Drecon / uffer Type CATERR# PECI PROCHOT# THERMTRIP# Caasrophc Error: Ths sgnal ndcaes ha he sysem has experenced a caasrophc error and canno connue o operae. The processor wll se hs for non-recoverable machne check errors or oher unrecoverable nernal errors. CATERR# s used for sgnalng he followng ypes of errors: Legacy MCERRs, CATERR# s assered for 16 CLKs. Legacy IERRs, CATERR# remans assered unl warm or cold rese. Plaform Envronmen Conrol Inerface: A seral sdeband nerface o he processor, s used prmarly for hermal, power, and error managemen. Processor Ho: PROCHOT# goes acve when he processor emperaure monorng sensor(s) deecs ha he processor has reached s maxmum safe operang emperaure. Ths ndcaes ha he processor Thermal Conrol Crcu (TCC) has been acvaed, f enabled. Ths sgnal can also be drven o he processor o acvae he TCC. Thermal Trp: The processor proecs self from caasrophc overheang by use of an nernal hermal sensor. Ths sensor s se well above he normal operang emperaure o ensure ha here are no false rps. The processor wll sop all execuon when he juncon emperaure exceeds approxmaely 130 C. Ths s sgnaled o he sysem by he THERMTRIP# pn. O GTL I/O Asynchronous GTL Inpu Open-Dran Oupu O Asynchronous OD Asynchronous CMOS 6.10 Table 41. Power Sequencng Sgnals Power Sequencng Sgnals Sgnal Name Descrpon Drecon / uffer Type SM_DRAMPWROK PWRGOOD SKTOCC# SM_DRAMPWROK Processor Inpu: Ths sgnal connecs o he PCH DRAMPWROK. The processor requres hs npu sgnal o be a clean ndcaon ha he V CC and V DDQ power supples are sable and whn specfcaons. Ths requremen apples regardless of he S-sae of he processor. 'Clean' mples ha he sgnal wll reman low (capable of snkng leakage curren), whou glches, from he me ha he power supples are urned on unl he supples come whn specfcaon. The sgnal mus hen ranson monooncally o a hgh sae. SKTOCC# (Socke Occuped) / PROC_DETECT#: Processor Deec: Ths sgnal s pulled down drecly (0 Ohms) on he processor package o ground. There s no connecon o he processor slcon for hs sgnal. Sysem board desgners may use hs sgnal o deermne f he processor s presen. I Asynchronous CMOS I Asynchronous CMOS Daashee Volume 1 of 2 March Order No.:

93 Sgnal Descrpon Processor 6.11 Table 42. Processor Power Sgnals Processor Power Sgnals Sgnal Name Descrpon Drecon / uffer Type Processor core power ral. Ref IO_OUT Processor power reference for I/O. Ref VDDQ Processor I/O supply volage for DDR3. Ref VCOMP_OUT Processor power reference for PEG/Dsplay RCOMP. Ref VIDSOUT VIDSCLK VIDALERT# VIDALERT#, VIDSCLK, and VIDSCLK comprse a hree sgnal seral synchronous nerface used o ransfer power managemen nformaon beween he processor and he volage regulaor conrollers. Inpu GTL/ Oupu Open Dran Oupu Open Dran Inpu CMOS 6.12 Table 43. Sense Sgnals Sense Sgnals Sgnal Name Descrpon Drecon / uffer Type _SENSE _SENSE _SENSE and _SENSE provde an solaed, lowmpedance connecon o he processor npu V CC volage and ground. The sgnals can be used o sense or measure volage near he slcon. O A 6.13 Table 44. Ground and Non-Crcal o Funcon (NCTF) Sgnals Ground and Non-Crcal o Funcon (NCTF) Sgnals Sgnal Name Descrpon Drecon / uffer Type Processor ground node GND _NCTF Non-Crcal o Funcon: These pns are for package mechancal relably Table 45. Processor Inernal Pull-Up / Pull-Down Termnaons Processor Inernal Pull-Up / Pull-Down Termnaons Sgnal Name Pull Up / Pull Down Ral Value PM[7:0] Pull Up IO_TERM Ω PREQ# Pull Up IO_TERM Ω TDI Pull Up IO_TERM Ω TMS Pull Up IO_TERM Ω CFG[17:0] Pull Up IO_OUT 5 8 kω CATERR# Pull Up IO_TERM Ω March 2015 Daashee Volume 1 of 2 Order No.:

94 Processor Elecrcal Specfcaons 7.0 Elecrcal Specfcaons Ths chaper provdes he processor elecrcal specfcaons ncludng negraed volage regulaor (VR), V CC Volage Idenfcaon (VID), reserved and unused sgnals, sgnal groups, Tes Access Pons (TAP), and DC specfcaons. 7.1 Inegraed Volage Regulaor A new feaure o he processor s he negraon of plaform volage regulaors no he processor. Due o hs negraon, he processor has one man volage ral (V CC ) and a volage ral for he memory nerface (V DDQ ), compared o sx volage rals on prevous processors. The V CC volage ral wll supply he negraed volage regulaors whch n urn wll regulae o he approprae volages for he cores, cache, sysem agen, and graphcs. Ths negraon allows he processor o beer conrol on-de volages o opmze beween performance and power savngs. The processor V CC ral wll reman a VID-based volage wh a loadlne smlar o he core volage ral (also called V CC ) n prevous processors. 7.2 Power and Ground Lands The processor has, VDDQ, and (ground) lands for on-chp power dsrbuon. All power lands mus be conneced o her respecve processor power planes; all lands mus be conneced o he sysem ground plane. Use of mulple power and ground planes s recommended o reduce I*R drop. The lands mus be suppled wh he volage deermned by he processor Seral Volage IDenfcaon (SVID) nerface. Table 46 on page 95 specfes he volage level for he varous VIDs. 7.3 V CC Volage Idenfcaon (VID) The processor uses hree sgnals for he seral volage denfcaon nerface o suppor auomac selecon of volages. The followng able specfes he volage level correspondng o he 8-b VID value ransmed over seral VID. A 1 n hs able refers o a hgh volage level and a 0 refers o a low volage level. If he volage regulaon crcu canno supply he volage ha s requesed, he volage regulaor mus dsable self. VID sgnals are CMOS push/pull drvers. See he Volage and Curren Specfcaons secon for he DC specfcaons for hese sgnals. The VID codes wll change due o emperaure and/or curren load changes o mnmze he power of he par. A volage range s provded n he Volage and Curren Specfcaons secon. The specfcaons are se so ha one volage regulaor can operae wh all suppored frequences. Indvdual processor VID values may be se durng manufacurng so ha wo devces a he same core frequency may have dfferen defaul VID sengs. Ths s shown n he VID range values n he Volage and Curren Specfcaons secon. The processor provdes he ably o operae whle ransonng o an adjacen VID and s assocaed volage. Ths wll represen a DC shf n he loadlne. Daashee Volume 1 of 2 March Order No.:

95 Elecrcal Specfcaons Processor Table 46. Volage Regulaor (VR) 12.5 Volage Idenfcaon Hex V CC Hex V CC h h h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh h connued h h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh h h connued... March 2015 Daashee Volume 1 of 2 Order No.:

96 Processor Elecrcal Specfcaons Hex V CC Hex V CC h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh h h h h connued h h h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h connued... Daashee Volume 1 of 2 March Order No.:

97 Elecrcal Specfcaons Processor Hex V CC Hex V CC h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh A0h A1h A2h A3h A4h A5h A6h A7h connued A8h A9h AAh Ah ACh ADh AEh AFh h h h h h h h h h h Ah h Ch Dh Eh Fh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h connued... March 2015 Daashee Volume 1 of 2 Order No.:

98 Processor Elecrcal Specfcaons Hex V CC Hex V CC CAh Ch CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh Dh DCh DDh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh Fh FCh FDh FEh FFh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh Eh connued... Daashee Volume 1 of 2 March Order No.:

99 Elecrcal Specfcaons Processor 7.4 Reserved or Unused Sgnals The followng are he general ypes of reserved (RSVD) sgnals and connecon gudelnes: RSVD hese sgnals should no be conneced RSVD_TP hese sgnals should be roued o a es pon RSVD_NCTF hese sgnals are non-crcal o funcon and may be lef unconneced Arbrary connecon of hese sgnals o, VDDQ,, or o any oher sgnal (ncludng each oher) may resul n componen malfuncon or ncompably wh fuure processors. See Sgnal Descrpon on page 86 for a pn lsng of he processor and he locaon of all reserved sgnals. For relable operaon, always connec unused npus or b-dreconal sgnals o an approprae sgnal level. Unused acve hgh npus should be conneced hrough a ressor o ground (). Unused oupus maybe lef unconneced; however, hs may nerfere wh some Tes Access Por (TAP) funcons, complcae debug probng, and preven boundary scan esng. A ressor mus be used when yng b-dreconal sgnals o power or ground. When yng any sgnal o power or ground, a ressor wll also allow for sysem esably. 7.5 Sgnal Groups Sgnals are grouped by buffer ype and smlar characerscs as lsed n he followng able. The buffer ype ndcaes whch sgnalng echnology and specfcaons apply o he sgnals. All he dfferenal sgnals and seleced DDR3/DDR3L and Conrol Sdeband sgnals have On-De Termnaon (ODT) ressors. Some sgnals do no have ODT and need o be ermnaed on he board. Noe: Table 47. All Conrol Sdeband Asynchronous sgnals are requred o be assered/de-assered for a leas 10 CLKs wh maxmum Trse/Tfall of 6 ns for he processor o recognze he proper sgnal sae. See he DC Specfcaons secon and AC Specfcaons secon. Sgnal Groups Sgnal Group Type Sgnals Sysem Reference Clock Dfferenal CMOS Inpu CLKP, CLKN, DPLL_REF_CLKP, DPLL_REF_CLKN, SSC_DPLL_REF_CLKP, SSC_DPLL_REF_CLKN DDR3 / DDR3L Reference Clocks 2 Dfferenal DDR3/DDR3L Oupu SA_CKP[3:0], SA_CKN[3:0], S_CKP[3:0], S_CKN[3:0] DDR3 / DDR3L Command Sgnals 2 Sngle ended DDR3/DDR3L Oupu SA_S[2:0], S_S[2:0], SA_WE#, S_WE#, SA_RAS#, S_RAS#, SA_CAS#, S_CAS#, SA_MA[15:0], S_MA[15:0] DDR3 / DDR3L Conrol Sgnals 2 Sngle ended DDR3/DDR3L Oupu SA_CKE[3:0], S_CKE[3:0], SA_CS#[3:0], S_CS#[3:0], SA_ODT[3:0], S_ODT[3:0] Sngle ended CMOS Oupu SM_DRAMRST# connued... March 2015 Daashee Volume 1 of 2 Order No.:

100 Processor Elecrcal Specfcaons Sgnal Group Type Sgnals DDR3 / DDR3L Daa Sgnals 2 Sngle ended Dfferenal DDR3/DDR3L dreconal DDR3/DDR3L dreconal SA_DQ[63:0], S_DQ[63:0] SA_DQSP[7:0], SA_DQSN[7:0], S_DQSP[7:0], S_DQSN[7:0] DDR3 / DDR3L Compensaon Analog Inpu SM_RCOMP[2:0] DDR3 / DDR3L Reference Volage Sgnals DDR3/DDR3L Oupu SM_VREF, SA_DIMM_VREFDQ, S_DIMM_VREFDQ Tesably (ITP/XDP) Sngle ended CMOS Inpu TCK, TDI, TMS, TRST# Sngle ended GTL TDO Sngle ended Oupu DR# Sngle ended GTL PM#[7:0] Sngle ended GTL PREQ# Sngle ended GTL PRDY# Conrol Sdeband Sngle ended Sngle ended GTL Inpu/Open Dran Oupu Asynchronous CMOS Oupu PROCHOT# THERMTRIP#, IVR_ERROR Sngle ended GTL CATERR# Sngle ended Sngle ended Asynchronous CMOS Inpu Asynchronous dreconal PM_SYNC,RESET#, PWRGOOD, PWR_DEUG# PECI Sngle ended GTL -dreconal CFG[19:0] Sngle ended Analog Inpu SM_RCOMP[2:0] Volage Regulaor Sngle ended CMOS Inpu VR_READY Sngle ended CMOS Inpu VIDALERT# Sngle ended Open Dran Oupu VIDSCLK Sngle ended GTL Inpu/Open Dran Oupu VIDSOUT Dfferenal Analog Oupu _SENSE, _SENSE Power / Ground / Oher Sngle ended Power, VDDQ Ground, _NCTF 3 No Connec RSVD, RSVD_NCTF connued... Daashee Volume 1 of 2 March Order No.:

101 Elecrcal Specfcaons Processor Sgnal Group Type Sgnals Tes Pon Oher RSVD_TP SKTOCC#, PCI Express* Graphcs Dfferenal PCI Express Inpu PEG_RXP[15:0], PEG_RXN[15:0] Dfferenal PCI Express Oupu PEG_TXP[15:0], PEG_TXN[15:0] Sngle ended Analog Inpu PEG_RCOMP Dgal Meda Inerface (DMI) Dfferenal DMI Inpu DMI_RXP[3:0], DMI_RXN[3:0] Dfferenal DMI Oupu DMI_TXP[3:0], DMI_TXN[3:0] Dgal Dsplay Inerface Dfferenal DDI Oupu DDI_TXP[3:0], DDI_TXN[3:0], DDIC_TXP[3:0], DDIC_TXN[3:0], DDID_TXP[3:0], DDID_TXN[3:0] Inel FDI Sngle ended CMOS Inpu FDI_CSYNC Sngle ended Asynchronous CMOS Inpu DISP_INT Dfferenal FDI Oupu FDI_TXP[1:0], FDI_TXN[1:0] Noes: 1. See Sgnal Descrpon on page 86 for sgnal descrpon deals. 2. SA and S refer o DDR3/DDR3L Channel A and DDR3/DDR3L Channel. 7.6 Tes Access Por (TAP) Connecon Due o he volage levels suppored by oher componens n he Tes Access Por (TAP) logc, Inel recommends he processor be frs n he TAP chan, followed by any oher componens whn he sysem. A ranslaon buffer should be used o connec o he res of he chan unless one of he oher componens s capable of accepng an npu of he approprae volage. Two copes of each sgnal may be requred wh each drvng a dfferen volage level. The processor suppors oundary Scan (JTAG) IEEE and IEEE sandards. A few of he I/O pns may suppor only one of hose sandards. 7.7 DC Specfcaons The processor DC specfcaons n hs secon are defned a he processor pns, unless noed oherwse. See Sgnal Descrpon on page 86 for he processor pn lsngs and sgnal defnons. The DC specfcaons for he DDR3 / DDR3L sgnals are lsed n he Volage and Curren Specfcaons secon. The Volage and Curren Specfcaons secon lss he DC specfcaons for he processor and are vald only whle meeng specfcaons for juncon emperaure, clock frequency, and npu volages. Read all noes assocaed wh each parameer. March 2015 Daashee Volume 1 of 2 Order No.:

102 Processor Elecrcal Specfcaons AC olerances for all DC rals nclude dynamc load currens a swchng frequences up o 1 MHz. 7.8 Table 48. Volage and Curren Specfcaons Processor Core Acve and Idle Mode DC Volage and Curren Specfcaons Symbol Parameer Mn Typ Max Un Noe D: 1.75 Operaonal VID VID Range C: : A: V 2 Idle VID (package C6/C7) VID Range V 2 R_DC_LL Loadlne slope whn he VR regulaon loop capably 2014: PCG: D PCG: C PCG: PCG: A PCG: -1.5 mω 3, 5, 6, 8 R_AC_LL Loadlne slope n response o dynamc load ncrease evens 2014: PCG: D PCG: C PCG: PCG: A PCG: -2.4 mω R_AC_LL_OS Loadlne slope n response o dynamc load release evens 2014: PCG: D PCG: C PCG: PCG: A PCG: -3.0 mω T_OVS Overshoo me 500 us V_OVS Overshoo 50 mv V CC TO V CC Tolerance and ± 20 (PS0, PS1, PS2, PS3) mv 3, 5, 6, 7, 8 Rpple ± 10 (PS0) V CC Rpple ± 15 (PS1) +50/-15 (PS2) +60/-15 (PS3) mv 3, 5, 6, 7, 8 V CC,OOT Defaul V CC volage for nal power up 1.70 V I CC I CC I CC 2013D PCG I CC 95 A 4, C PCG I CC 75 A 4, PCG I CC 58 A 4, 8 connued... Daashee Volume 1 of 2 March Order No.:

103 Elecrcal Specfcaons Processor Symbol Parameer Mn Typ Max Un Noe 1 I CC P MAX P MAX P MAX P MAX 2013A PCG I CC 48 A 4, D PCG P MAX 153 W C PCG P MAX 121 W PCG P MAX 99 W A PCG P MAX 83 W 9 Noes: 1. Unless oherwse noed, all specfcaons n hs able are based on esmaes and smulaons or emprcal daa. 2. Each processor s programmed wh a maxmum vald volage denfcaon value (VID) ha s se a manufacurng and canno be alered. Indvdual maxmum VID values are calbraed durng manufacurng such ha wo processors a he same frequency may have dfferen sengs whn he VID range. Ths dffers from he VID employed by he processor durng a power managemen even (Adapve Thermal Monor, Enhanced Inel SpeedSep Technology, or Low-Power Saes). 3. The volage specfcaon requremens are measured across _SENSE and _SENSE lands a he socke wh a 20-MHz bandwdh osclloscope, 1.5 pf maxmum probe capacance, and 1- MΩ mnmum mpedance. The maxmum lengh of ground wre on he probe should be less han 5 mm. Ensure exernal nose from he sysem s no coupled no he osclloscope probe. 4. I CC_MAX specfcaon s based on he V CC loadlne a wors case (hghes) olerance and rpple. 5. The V CC specfcaons represen sac and ransen lms. 6. The loadlnes specfy volage lms a he de measured a he _SENSE and _SENSE lands. Volage regulaon feedback for volage regulaor crcus mus also be aken from processor _SENSE and _SENSE lands. 7. PSx refers o he volage regulaor power sae as se by he SVID proocol. 8. PCG s Plaform Compably Gude (prevously known as FM). These gudelnes are for esmaon purposes only. 9. P MAX s he maxmum power he processor wll dsspae as measured a _SENSE and _SENSE lands. The processor may draw hs power for up o 10 ms before regulaes o PL2. Table 49. Memory Conroller (V DDQ ) Supply DC Volage and Curren Specfcaons Symbol Parameer Mn Typ Max Un Noe V DDQ (DC+AC) DDR3/DDR3L V DDQ (DC+AC) DDR3/DDR3L Icc MAX_VDDQ (DDR3/ DDR3L) Processor I/O supply volage for DDR3/DDR3L (DC + AC specfcaon) Processor I/O supply volage for DDR3L (DC + AC specfcaon) Max Curren for V DDQ Ral Typ-5% 1.5 Typ+5% V 2, 3, 5 Typ-5% 1.35 Typ+5% V 2, A 1 I CCAVG_VDDQ (Sandby) Average Curren for V DDQ Ral durng Sandby ma 4 Noes: 1. The curren suppled o he SO-DIMM modules s no ncluded n hs specfcaon. 2. Includes AC and DC error, where he AC nose s bandwdh lmed o under 20 MHz. 3. No requremen on he breakdown of AC versus DC nose. 4. Measured a 50 C 5. Ths specfcaon apples o deskop processors March 2015 Daashee Volume 1 of 2 Order No.:

104 Processor Elecrcal Specfcaons Table 50. IO_OUT, VCOMP_OUT, and IO_TERM Symbol Parameer Typ Max Uns Noes IO_OUT ICCIO_OUT VCOMP_OUT IO_TERM Termnaon Volage Maxmum Exernal Load Termnaon Volage Termnaon Volage 1.0 V 300 ma 1.0 V V 2 Noes: 1. VCOMP_OUT may only be used o connec o PEG_RCOMP and DP_RCOMP. 2. Inernal processor power for sgnal ermnaon. Table 51. DDR3 / DDR3L Sgnal Group DC Specfcaons Symbol Parameer Mn Typ Max Uns Noes 1 V IL Inpu Low Volage V DDQ /2 0.43*V DDQ V 2, 4, 11 V IH Inpu Hgh Volage 0.57*V DDQ V DDQ /2 V 3, 11 V IL V IH R ON_UP(DQ) Inpu Low Volage (SM_DRAMPWROK) Inpu Hgh Volage (SM_DRAMPWROK) DDR3/DDR3L Daa uffer pull-up Ressance 0.15*V DDQ V 0.45*V DDQ 1.0 V 10, Ω 5, 11 R ON_DN(DQ) DDR3/DDR3L Daa uffer pull-down Ressance Ω 5, 11 R ODT(DQ) DDR3/DDR3L On-de ermnaon equvalen ressance for daa sgnals Ω 11 V ODT(DC) DDR3/DDR3L On-de ermnaon DC workng pon (drver se o receve mode) 0.45*V DDQ 0.5*V DDQ 0.55*V DDQ V 11 R ON_UP(CK) DDR3/DDR3L Clock uffer pull-up Ressance Ω 5, 11, 13 R ON_DN(CK) DDR3/DDR3L Clock uffer pull-down Ressance Ω 5, 11, 13 R ON_UP(CMD) DDR3/DDR3L Command uffer pull-up Ressance Ω 5, 11, 13 R ON_DN(CMD) DDR3/DDR3L Command uffer pull-down Ressance Ω 5, 11, 13 R ON_UP(CTL) DDR3/DDR3L Conrol uffer pull-up Ressance Ω 5, 11, 13 connued... Daashee Volume 1 of 2 March Order No.:

105 Elecrcal Specfcaons Processor Symbol Parameer Mn Typ Max Uns Noes 1 R ON_DN(CTL) DDR3/DDR3L Conrol uffer pull-down Ressance Ω 5, 11, 13 R ON_UP(RST) R ON_DN(RST) I LI I LI SM_RCOMP0 DDR3/DDR3L Rese uffer pull-up Ressance DDR3/DDR3L Rese uffer pull-up Ressance Inpu Leakage Curren (DQ, CK) 0V 0.2*V DDQ 0.8*V DDQ Inpu Leakage Curren (CMD, CTL) 0V 0.2*V DDQ 0.8*V DDQ Command COMP Ressance Ω Ω 0.7 ma 1.0 ma Ω 8 SM_RCOMP1 Daa COMP Ressance Ω 8 SM_RCOMP2 ODT COMP Ressance Ω 8 Noes: 1. Unless oherwse noed, all specfcaons n hs able apply o all processor frequences. 2. V IL s defned as he maxmum volage level a a recevng agen ha wll be nerpreed as a logcal low value. 3. V IH s defned as he mnmum volage level a a recevng agen ha wll be nerpreed as a logcal hgh value. 4. V IH and V OH may experence excursons above V DDQ. However, npu sgnal drvers mus comply wh he sgnal qualy specfcaons. 5. Ths s he pull up/down drver ressance. 6. R TERM s he ermnaon on he DIMM and n no conrolled by he processor. 7. The mnmum and maxmum values for hese sgnals are programmable by IOS o one of he wo ses. 8. SM_RCOMPx ressance mus be provded on he sysem board wh 1% ressors. SM_RCOMPx ressors are o V SS. 9. SM_DRAMPWROK rse and fall me mus be < 50 ns measured beween V DDQ *0.15 and V DDQ * SM_VREF s defned as V DDQ /2. 11.Maxmum-mnmum range s correc; however, cener pon s subjec o change durng MRC boo ranng. 12.Processor may be damaged f V IH exceeds he maxmum volage for exended perods. 13.The MRC durng boo ranng mgh opmze R ON ousde he range specfed. Table 52. Dgal Dsplay Inerface Group DC Specfcaons Symbol Parameer Mn Typ Max Uns V IL HPD Inpu Low Volage 0.8 V V IH HPD Inpu Hgh Volage V Vaux(Tx) Vaux(Rx) Aux peak-o-peak volage a ransmng devce Aux peak-o-peak volage a recevng devce V V March 2015 Daashee Volume 1 of 2 Order No.:

106 Processor Elecrcal Specfcaons Table 53. embedded DsplayPor* (edp*) Group DC Specfcaons Symbol Parameer Mn Typ Max Uns V IL HPD Inpu Low Volage V V IH HPD Inpu Hgh Volage V V OL edp_disp_util Oupu Low Volage 0.1*V CC V V OH edp_disp_util Oupu Hgh Volage 0.9*V CC V R UP edp_disp_util Inernal pull-up 100 Ω R DOWN edp_disp_util Inernal pull-down 100 Ω Vaux(Tx) Vaux(Rx) Aux peak-o-peak volage a ransmng devce Aux peak-o-peak volage a recevng devce V V edp_rcomp DP_RCOMP COMP Ressance Ω Noe: 1. COMP ressance s o VCOMP_OUT. Table 54. CMOS Sgnal Group DC Specfcaons Symbol Parameer Mn Max Uns Noes 1 V IL Inpu Low Volage V CCIO_OUT * 0.3 V 2 V IH Inpu Hgh Volage V CCIO_OUT * 0.7 V 2, 4 V OL Oupu Low Volage V CCIO_OUT * 0.1 V 2 V OH Oupu Hgh Volage V CCIO_OUT * 0.9 V 2, 4 R ON uffer on Ressance Ω I LI Inpu Leakage Curren ±150 μa 3 Noes: 1. Unless oherwse noed, all specfcaons n hs able apply o all processor frequences. 2. The V CCIO_OUT referred o n hese specfcaons refers o nsananeous IO_OUT. 3. For VIN beween 0 V and V CCIO_OUT. Measured when he drver s r-saed. 4. V IH and V OH may experence excursons above V CCIO_OUT. However, npu sgnal drvers mus comply wh he sgnal qualy specfcaons. Table 55. GTL Sgnal Group and Open Dran Sgnal Group DC Specfcaons Symbol Parameer Mn Max Uns Noes 1 V IL V IH Inpu Low Volage (TAP, excep TCK) Inpu Hgh Volage (TAP, excep TCK) V CCIO_TERM * 0.6 V 2 V CCIO_TERM * 0.72 V 2, 4 V IL Inpu Low Volage (TCK) V CCIO_TERM * 0.4 V 2 V IH Inpu Hgh Volage (TCK) V CCIO_TERM * 0.8 V 2, 4 V HYSTERESIS Hyseress Volage V CCIO_TERM * 0.2 V R ON uffer on Ressance (TDO) Ω V IL Inpu Low Volage (oher GTL) V CCIO_TERM * 0.6 V 2 connued... Daashee Volume 1 of 2 March Order No.:

107 Elecrcal Specfcaons Processor Symbol Parameer Mn Max Uns Noes 1 V IH Inpu Hgh Volage (oher GTL) V CCIO_TERM * 0.72 V 2, 4 R ON uffer on Ressance (CFG/PM) Ω R ON uffer on Ressance (oher GTL) Ω I LI Inpu Leakage Curren ±150 μa 3 Noes: 1. Unless oherwse noed, all specfcaons n hs able apply o all processor frequences. 2. The V CCIO_OUT referred o n hese specfcaons refers o nsananeous IO_OUT. 3. For VIN beween 0 V and V CCIO_TERM. Measured when he drver s r-saed. 4. V IH and V OH may experence excursons above V CCIO_TERM. However, npu sgnal drvers mus comply wh he sgnal qualy specfcaons. Table 56. PCI Express* DC Specfcaons Symbol Parameer Mn Typ Max Uns Noes 1 Z TX-DIFF-DC DC Dfferenal Tx Impedance (Gen 1 Only) Ω 1, 6 Z TX-DIFF-DC DC Dfferenal Tx Impedance (Gen 2 and Gen 3) 120 Ω 1, 6 Z RX-DC DC Common Mode Rx Impedance Ω 1, 4, 5 Z RX-DIFF-DC DC Dfferenal Rx Impedance (Gen1 Only) Ω 1 PEG_RCOMP Comp Ressance Ω 2, 3 Noes: 1. See he PCI Express ase Specfcaon for more deals. 2. PEG_RCOMP should be conneced o V COMP_OUT hrough a 25 Ω ±1% ressor. 3. Inel allows usng 24.9 Ω ±1% ressors. 4. DC mpedance lms are needed o ensure Recever deec. 5. The Rx DC Common Mode Impedance mus be presen when he Recever ermnaons are frs enabled o ensure ha he Recever Deec occurs properly. Compensaon of hs mpedance can sar mmedaely and he 15 Rx Common Mode Impedance (consraned by RLRX-CM o 50 Ω ±20%) mus be whn he specfed range by he me Deec s enered. 6. Low mpedance defned durng sgnalng. Parameer s capured for 5.0 GHz by RLTX-DIFF Plaform Envronmen Conrol Inerface (PECI) DC Characerscs The PECI nerface operaes a a nomnal volage se by V CCIO_TERM. The se of DC elecrcal specfcaons shown n he followng able s used wh devces normally operang from a V CCIO_TERM nerface supply. V CCIO_TERM nomnal levels wll vary beween processor famles. All PECI devces wll operae a he V CCIO_TERM level deermned by he processor nsalled n he sysem. Table 57. Plaform Envronmen Conrol Inerface (PECI) DC Elecrcal Lms Symbol Defnon and Condons Mn Max Uns Noes 1 R up Inernal pull up ressance Ω 3 V n Inpu Volage Range V CCIO_TERM V V hyseress Hyseress 0.1 * V CCIO_TERM N/A V connued... March 2015 Daashee Volume 1 of 2 Order No.:

108 Processor Elecrcal Specfcaons Symbol Defnon and Condons Mn Max Uns Noes 1 V n V p Negave-Edge Threshold Volage Posve-Edge Threshold Volage * V V CCIO_TERM * V CCIO_TERM * * V V CCIO_TERM V CCIO_TERM C bus us Capacance per Node N/A 10 pf C pad Pad Capacance pf Ileak000 leakage curren a 0 V 0.6 ma Ileak025 Ileak050 Ileak075 Ileak100 leakage curren a 0.25* V CCIO_TERM 0.4 ma leakage curren a 0.50* V CCIO_TERM 0.2 ma leakage curren a 0.75* V CCIO_TERM 0.13 ma leakage curren a V CCIO_TERM 0.10 ma Noes: 1. V CCIO_TERM supples he PECI nerface. PECI behavor does no affec V CCIO_TERM mnmum / maxmum specfcaons. 2. The leakage specfcaon apples o powered devces on he PECI bus. 3. The PECI buffer nernal pull-up ressance measured a 0.75* V CCIO_TERM Inpu Devce Hyseress The npu buffers n boh clen and hos models mus use a Schm-rggered npu desgn for mproved nose mmuny. Use he followng fgure as a gude for npu buffer desgn. Fgure 23. Inpu Devce Hyseress V TTD Maxmum V P PECI Hgh Range Mnmum V P Maxmum V N Mnmum Hyseress Vald Inpu Sgnal Range Mnmum V N PECI Low Range PECI Ground Daashee Volume 1 of 2 March Order No.:

109 Package Mechancal Specfcaons Processor 8.0 Package Mechancal Specfcaons The processor s packaged n a Flp-Chp Land Grd Array package ha nerfaces wh he moherboard usng he LGA1150 socke. The package consss of a processor mouned on a subsrae land-carrer. An negraed hea spreader (IHS) s aached o he package subsrae and core and serves as he mang surface for processor hermal soluons, such as a heasnk. The followng fgure shows a skech of he processor package componens and how hey are assembled ogeher. The package componens shown n he followng fgure nclude he followng: 1. Inegraed Hea Spreader (IHS) 2. Thermal Inerface Maeral (TIM) 3. Processor core (de) 4. Package subsrae 5. Capacors Fgure 24. Processor Package Assembly Skech 8.1 Processor Componen Keep-Ou Zone The processor may conan componens on he subsrae ha defne componen keepou zone requremens. A hermal and mechancal soluon desgn mus no nrude no he requred keep-ou zones. Decouplng capacors are ypcally mouned o he land-sde of he package subsrae. Refer o he LGA1150 Socke Applcaon Gude for keep-ou zones. The locaon and quany of package capacors may change due o manufacurng effcences bu wll reman whn he componen keep-n. Ths keep-n zone ncludes solder pase and s a pos reflow maxmum hegh for he componens. 8.2 Package Loadng Specfcaons The followng able provdes dynamc and sac load specfcaons for he processor package. These mechancal maxmum load lms should no be exceeded durng heasnk assembly, shppng condons, or sandard use condon. Also, any March 2015 Daashee Volume 1 of 2 Order No.:

110 Processor Package Mechancal Specfcaons mechancal sysem or componen esng should no exceed he maxmum lms. The processor package subsrae should no be used as a mechancal reference or loadbearng surface for hermal and mechancal soluon. Table 58. Processor Loadng Specfcaons Parameer Mnmum Maxmum Noes Sac Compressve Load 600 N [135 lbf] 1, 2, 3 Dynamc Compressve Load 712 N [160 lbf] 1, 3, 4 Noes: 1. These specfcaons apply o unform compressve loadng n a drecon normal o he processor, IHS. 2. Ths s he maxmum sac force ha can be appled by he heasnk and reenon soluon o manan he heasnk and processor nerface. 3. These specfcaons are based on lmed esng for desgn characerzaon. Loadng lms are for he package only and do no nclude he lms of he processor socke. 4. Dynamc loadng s defned as an 50g shock load, 2X Dynamc Acceleraon Facor wh a 500g maxmum hermal soluon. 8.3 Package Handlng Gudelnes The followng able ncludes a ls of gudelnes on package handlng n erms of recommended maxmum loadng on he processor IHS relave o a fxed subsrae. These package handlng loads may be experenced durng heasnk removal. Table 59. Package Handlng Gudelnes Parameer Maxmum Recommended Noes Shear 311 N [70 lbf] 1, 4 Tensle 111 N [25 lbf] 2, 4 Torque 3.95 N-m [35 lbf-n] 3, 4 Noes: 1. A shear load s defned as a load appled o he IHS n a drecon parallel o he IHS op surface. 2. A ensle load s defned as a pullng load appled o he IHS n a drecon normal o he IHS surface. 3. A orque load s defned as a wsng load appled o he IHS n an axs of roaon normal o he IHS op surface. 4. These gudelnes are based on lmed esng for desgn characerzaon. 8.4 Package Inseron Specfcaons The processor can be nsered no and removed from an LGA1150 socke 15 mes. The socke should mee he LGA1150 socke requremens dealed n he LGA1150 Socke Applcaon Gude. 8.5 Processor Mass Specfcaon The ypcal mass of he processor s 27.0 g (0.95 oz). Ths mass [wegh] ncludes all he componens ha are ncluded n he package. 8.6 Processor Maerals The followng able lss some of he package componens and assocaed maerals. Daashee Volume 1 of 2 March Order No.:

111 Package Mechancal Specfcaons Processor Table 60. Processor Maerals Componen Maeral Inegraed Hea Spreader (IHS) Subsrae Subsrae Lands Nckel Plaed Copper Fber Renforced Resn Gold Plaed Copper 8.7 Processor Markngs The followng fgure shows he op-sde markngs on he processor. Ths dagram ads n he denfcaon of he processor. Fgure 25. Processor Top-Sde Markngs 8.8 Processor Land Coordnaes The followng fgures show he boom vew of he processor package. March 2015 Daashee Volume 1 of 2 Order No.:

112 Processor Package Mechancal Specfcaons Fgure 26. Processor Package Land Coordnaes Daashee Volume 1 of 2 March Order No.:

113 Package Mechancal Specfcaons Processor Fgure Processor Package Land/Pn Sde Componens 8.9 Processor Sorage Specfcaons The followng able ncludes a ls of he specfcaons for devce sorage n erms of maxmum and mnmum emperaures and relave humdy. These condons should no be exceeded n sorage or ransporaon. Table 61. Processor Sorage Specfcaons Parameer Descrpon Mnmum Maxmum Noes T absolue sorage T susaned sorage The non-operang devce sorage emperaure. Damage (laen or oherwse) may occur when subjeced o for any lengh of me. The amben sorage emperaure lm (n shppng meda) for a susaned perod of me. -55 C 125 C 1, 2, 3-5 C 40 C 4, 5 connued... March 2015 Daashee Volume 1 of 2 Order No.:

114 Processor Package Mechancal Specfcaons Parameer Descrpon Mnmum Maxmum Noes RH susaned sorage TIME susaned sorage The maxmum devce sorage relave humdy for a susaned perod of me. A prolonged or exended perod of me; ypcally assocaed wh cusomer shelf lfe. 24 C 5, 6 0 Monhs 6 Monhs 6 Noes: 1. Refers o a componen devce ha s no assembled n a board or socke ha s no o be elecrcally conneced o a volage reference or I/O sgnals. 2. Specfed emperaures are based on daa colleced. Excepons for surface moun reflow are specfed n by applcable JEDEC sandard. Non-adherence may affec processor relably. 3. T ASOLUTE sorage apples o he unassembled componen only and does no apply o he shppng meda, mosure barrer bags, or desccan. 4. Inel branded board producs are cerfed o mee he followng emperaure and humdy lms ha are gven as an example only (Non-Operang Temperaure Lm: -40 C o 70 C, Humdy: 50% o 90%, non-condensng wh a maxmum we bulb of 28 C). Pos board aach sorage emperaure lms are no specfed for non-inel branded boards. 5. The JEDEC, J-JSTD-020 mosure level rang and assocaed handlng pracces apply o all mosure sensve devces removed from he mosure barrer bag. 6. Nomnal emperaure and humdy condons and duraons are gven and esed whn he consrans mposed by T susaned sorage and cusomer shelf lfe n applcable Inel box and bags. Daashee Volume 1 of 2 March Order No.:

115 Processor all and Sgnal Informaon Processor 9.0 Processor all and Sgnal Informaon Ths chaper provdes processor ball nformaon. The followng able provdes he ball ls by sgnal name. Noe: Table 62. References o SA_ECC_C[7:0] and S_ECC_C[7:0] are for processor SKUs ha suppor ECC. These sgnals are reserved on he Deskop 4h Generaon Inel Core processor famly. Processor all Ls by Sgnal Name Sgnal Name all # Sgnal Name all # Sgnal Name all # CLKN V4 CFG3 W38 DDID_TXDN1 16 CLKP V5 CFG4 V39 DDID_TXDN2 C17 PM#0 G39 CFG5 U39 DDID_TXDN3 18 PM#1 J39 CFG6 U40 DDID_TXDP0 15 PM#2 G38 CFG7 V38 DDID_TXDP1 A16 PM#3 H37 CFG8 T40 DDID_TXDP2 17 PM#4 H38 CFG9 Y35 DDID_TXDP3 A18 PM#5 J38 DR# G40 DISP_INT D18 PM#6 K39 DDI_TXN0 F17 DMI_RXN0 T3 PM#7 K37 DDI_TXN1 G18 DMI_RXN1 V1 CATERR# M36 DDI_TXN2 H19 DMI_RXN2 V2 CFG_RCOMP H40 DDI_TXN3 G20 DMI_RXN3 W3 CFG0 AA37 DDI_TXP0 E17 DMI_RXP0 U3 CFG1 Y38 DDI_TXP1 F18 DMI_RXP1 U1 CFG10 AA34 DDI_TXP2 G19 DMI_RXP2 W2 CFG11 V37 DDI_TXP3 F20 DMI_RXP3 Y3 CFG12 Y34 DDIC_TXCN0 E19 DMI_TXN0 AA5 CFG13 U38 DDIC_TXCN1 D20 DMI_TXN1 A4 CFG14 W34 DDIC_TXCN2 E21 DMI_TXN2 AC4 CFG15 V35 DDIC_TXCN3 D22 DMI_TXN3 AC2 CFG16 Y37 DDIC_TXCP0 D19 DMI_TXP0 AA4 CFG17 Y36 DDIC_TXCP1 C20 DMI_TXP1 A3 CFG18 W36 DDIC_TXCP2 D21 DMI_TXP2 AC5 CFG19 V36 DDIC_TXCP3 C22 DMI_TXP3 AC1 CFG2 AA36 DDID_TXDN0 C15 DP_RCOMP R4 connued... connued... connued... March 2015 Daashee Volume 1 of 2 Order No.:

116 Processor Processor all and Sgnal Informaon Sgnal Name all # Sgnal Name all # Sgnal Name all # DPLL_REF_CLKN W6 PEG_RXP14 K5 PEG_TXP4 C8 DPLL_REF_CLKP W5 PEG_RXP15 L4 PEG_TXP5 7 EDP_DISP_UTIL E16 PEG_RXP2 E13 PEG_TXP6 A6 FC_K9 K9 PEG_RXP3 D12 PEG_TXP7 5 FC_Y7 Y7 PEG_RXP4 E11 PEG_TXP8 E1 FDI_CSYNC D16 PEG_RXP5 F10 PEG_TXP9 F2 FDI0_TX0N0 14 PEG_RXP6 E9 PM_SYNC P36 FDI0_TX0N1 C13 PEG_RXP7 F8 PRDY# L39 FDI0_TX0P0 A14 PEG_RXP8 D3 PREQ# L37 FDI0_TX0P1 13 PEG_RXP9 E4 PROCHOT# K38 IST_TRIGGER C39 PEG_TXN0 12 PWR_DEUG N40 IVR_ERROR R36 PEG_TXN1 C11 PWRGOOD A35 PECI N37 PEG_TXN10 G2 RESET# M39 PEG_RCOMP P3 PEG_TXN11 H3 RSVD A33 PEG_RXN0 F15 PEG_TXN12 J2 RSVD A36 PEG_RXN1 E14 PEG_TXN13 K3 RSVD A8 PEG_RXN10 F6 PEG_TXN14 M3 RSVD AC8 PEG_RXN11 G5 PEG_TXN15 L2 RSVD AK20 PEG_RXN12 H6 PEG_TXN2 D10 RSVD AL20 PEG_RXN13 J5 PEG_TXN3 C9 RSVD AT40 PEG_RXN14 K6 PEG_TXN4 D8 RSVD AU1 PEG_RXN15 L5 PEG_TXN5 C7 RSVD AU27 PEG_RXN2 F13 PEG_TXN6 6 RSVD AU39 PEG_RXN3 E12 PEG_TXN7 C5 RSVD AV2 PEG_RXN4 F11 PEG_TXN8 E2 RSVD AV20 PEG_RXN5 G10 PEG_TXN9 F3 RSVD AV24 PEG_RXN6 F9 PEG_TXP0 A12 RSVD AV29 PEG_RXN7 G8 PEG_TXP1 11 RSVD AW12 PEG_RXN8 D4 PEG_TXP10 G1 RSVD AW23 PEG_RXN9 E5 PEG_TXP11 H2 RSVD AW24 PEG_RXP0 E15 PEG_TXP12 J1 RSVD AW27 PEG_RXP1 D14 PEG_TXP13 K2 RSVD AY18 PEG_RXP10 F5 PEG_TXP14 M2 RSVD H12 PEG_RXP11 G4 PEG_TXP15 L1 RSVD H14 PEG_RXP12 H5 PEG_TXP2 C10 RSVD H15 PEG_RXP13 J4 PEG_TXP3 9 RSVD J15 connued... connued... connued... Daashee Volume 1 of 2 March Order No.:

117 Processor all and Sgnal Informaon Processor Sgnal Name all # Sgnal Name all # Sgnal Name all # RSVD J17 RSVD_TP P37 SA_DQ20 AM37 RSVD J40 SA_S0 AV12 SA_DQ21 AM38 RSVD J9 SA_S1 AY11 SA_DQ22 AP37 RSVD L10 SA_S2 AT21 SA_DQ23 AP40 RSVD L12 SA_CAS# AU9 SA_DQ24 AV37 RSVD M10 SA_CK0 AY15 SA_DQ25 AW37 RSVD M11 SA_CK1 AW15 SA_DQ26 AU35 RSVD M38 SA_CK2 AV14 SA_DQ27 AV35 RSVD N35 SA_CK3 AW13 SA_DQ28 AT37 RSVD P33 SA_CKE0 AV22 SA_DQ29 AU37 RSVD R33 SA_CKE1 AT23 SA_DQ3 AF39 RSVD R34 SA_CKE2 AU22 SA_DQ30 AT35 RSVD T34 SA_CKE3 AU23 SA_DQ31 AW35 RSVD T35 SA_CKN0 AY16 SA_DQ32 AY6 RSVD T8 SA_CKN1 AV15 SA_DQ33 AU6 RSVD U8 SA_CKN2 AW14 SA_DQ34 AV4 RSVD W8 SA_CKN3 AY13 SA_DQ35 AU4 RSVD Y8 SA_CS#0 AU14 SA_DQ36 AW6 RSVD_TP A4 SA_CS#1 AV9 SA_DQ37 AV6 RSVD_TP AV1 SA_CS#2 AU10 SA_DQ38 AW4 RSVD_TP AW2 SA_CS#3 AW8 SA_DQ39 AY4 RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP 3 C2 D1 H16 J10 J12 J13 J16 J8 K11 K12 K13 K8 N36 N38 connued... SA_DIMM_VREF DQ SA_DQ0 SA_DQ1 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ2 A39 AD38 AD39 AK38 AK39 AH37 AH38 AK37 AK40 AM40 AM39 AP38 AP39 AF38 connued... SA_DQ4 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ5 SA_DQ50 SA_DQ51 SA_DQ52 AD37 AR1 AR4 AN3 AN4 AR2 AR3 AN2 AN1 AL1 AL4 AD40 AJ3 AJ4 AL2 connued... March 2015 Daashee Volume 1 of 2 Order No.:

118 Processor Processor all and Sgnal Informaon Sgnal Name all # Sgnal Name all # Sgnal Name all # SA_DQ53 AL3 SA_ECC_C3 AV31 S_CKE1 AY29 SA_DQ54 AJ2 SA_ECC_C4 AT33 S_CKE2 AU28 SA_DQ55 AJ1 SA_ECC_C5 AU33 S_CKE3 AU29 SA_DQ56 AG1 SA_ECC_C6 AT31 S_CKN0 AM21 SA_DQ57 AG4 SA_ECC_C7 AW31 S_CKN1 AP21 SA_DQ58 AE3 SA_MA0 AU13 S_CKN2 AN21 SA_DQ59 AE4 SA_MA1 AV16 S_CKN3 AP20 SA_DQ6 AF37 SA_MA10 AW11 S_CS#0 AP17 SA_DQ60 AG2 SA_MA11 AV19 S_CS#1 AN15 SA_DQ61 AG3 SA_MA12 AU19 S_CS#2 AN17 SA_DQ62 AE2 SA_MA13 AY10 S_CS#3 AL15 SA_DQ63 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSN8 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SA_DQSP8 SA_ECC_C0 SA_ECC_C1 SA_ECC_C2 AE1 AF40 AH40 AH39 AE38 AJ38 AN38 AU36 AW5 AP2 AK2 AF2 AU32 AE39 AJ39 AN39 AV36 AV5 AP3 AK3 AF3 AV32 AW33 AV33 AU31 connued... SA_MA14 SA_MA15 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3 SA_RAS# SA_WE# S_S0 S_S1 S_S2 S_CAS# S_CK0 S_CK1 S_CK2 S_CK3 S_CKE0 AT20 AU21 AU16 AW17 AU17 AW18 AV17 AT18 AU18 AT19 AW10 AY8 AW9 AU8 AU12 AU11 AK17 AL18 AW28 AP16 AM20 AP22 AN20 AP19 AW29 connued... S_DIMM_VREF DQ S_DQ0 S_DQ1 S_DQ10 S_DQ11 S_DQ12 S_DQ13 S_DQ14 S_DQ15 S_DQ16 S_DQ17 S_DQ18 S_DQ19 S_DQ2 S_DQ20 S_DQ21 S_DQ22 S_DQ23 S_DQ24 S_DQ25 S_DQ26 S_DQ27 S_DQ28 S_DQ29 A40 AE34 AE35 AK31 AL31 AK34 AK35 AK32 AL32 AN34 AP34 AN31 AP31 AG35 AN35 AP35 AN32 AP32 AM29 AM28 AR29 AR28 AL29 AL28 connued... Daashee Volume 1 of 2 March Order No.:

119 Processor all and Sgnal Informaon Processor Sgnal Name all # Sgnal Name all # Sgnal Name all # S_DQ3 AH35 S_DQ62 AF6 S_MA13 AR15 S_DQ30 AP29 S_DQ63 AF7 S_MA14 AV27 S_DQ31 AP28 S_DQ7 AH34 S_MA15 AY28 S_DQ32 AR12 S_DQ8 AL34 S_MA2 AM22 S_DQ33 AP12 S_DQ9 AL35 S_MA3 AM23 S_DQ34 AL13 S_DQS0 AF35 S_MA4 AP23 S_DQ35 AL12 S_DQS1 AL33 S_MA5 AL23 S_DQ36 AR13 S_DQS2 AP33 S_MA6 AY24 S_DQ37 AP13 S_DQS3 AN28 S_MA7 AV25 S_DQ38 AM13 S_DQS4 AN12 S_MA8 AU26 S_DQ39 AM12 S_DQS5 AP8 S_MA9 AW25 S_DQ4 AD34 S_DQS6 AL8 S_ODT0 AM17 S_DQ40 AR9 S_DQS7 AG7 S_ODT1 AL16 S_DQ41 AP9 S_DQS8 AN25 S_ODT2 AM16 S_DQ42 AR6 S_DQSN0 AF34 S_ODT3 AK15 S_DQ43 AP6 S_DQSN1 AK33 S_RAS# AM18 S_DQ44 AR10 S_DQSN2 AN33 S_WE# AK16 S_DQ45 AP10 S_DQSN3 AN29 SKTOCC# D38 S_DQ46 S_DQ47 S_DQ48 S_DQ49 S_DQ5 S_DQ50 S_DQ51 S_DQ52 AR7 AP7 AM9 AL9 AD35 AL6 AL7 AM10 S_DQSN4 S_DQSN5 S_DQSN6 S_DQSN7 S_DQSN8 S_ECC_C0 S_ECC_C1 S_ECC_C2 AN13 AR8 AM8 AG6 AN26 AM26 AM25 AP25 SM_DRAMPWRO K SM_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_VREF SSC_DPLL_REF_ CLKN AK21 AK22 R1 P1 R2 A38 U5 S_DQ53 S_DQ54 S_DQ55 S_DQ56 S_DQ57 S_DQ58 S_DQ59 S_DQ6 S_DQ60 S_DQ61 AL10 AM6 AM7 AH6 AH7 AE6 AE7 AG34 AJ6 AJ7 connued... S_ECC_C3 S_ECC_C4 S_ECC_C5 S_ECC_C6 S_ECC_C7 S_MA0 S_MA1 S_MA10 S_MA11 S_MA12 AP26 AL26 AL25 AR26 AR25 AL19 AK23 AP18 AY25 AV26 connued... SSC_DPLL_REF_ CLKP TCK TDI TDO TESTLO_N5 TESTLO_P6 THERMTRIP# TMS TRST# U6 D39 F38 F39 N5 P6 F37 E39 E37 connued... March 2015 Daashee Volume 1 of 2 Order No.:

120 Processor Processor all and Sgnal Informaon Sgnal Name all # Sgnal Name all # Sgnal Name all # A24 E29 J22 A25 E30 J23 A26 E31 J24 A27 E32 J25 A28 E33 J26 A29 E34 J27 A30 E35 J28 25 F23 J29 27 F25 J30 29 F27 J31 31 F29 J32 33 F31 J33 35 F33 J34 C24 F35 J35 C25 G22 K19 C26 G23 K21 C27 G24 K23 C28 G25 K25 C29 G26 K27 C30 G27 K29 C31 G28 K31 C32 G29 K33 C33 G30 K35 C34 G31 L15 C35 G32 L16 D25 G33 L17 D27 G34 L18 D29 G35 L19 D31 H23 L20 D33 H25 L21 D35 H27 L22 E24 H29 L23 E25 H31 L24 E26 H33 L25 E27 H35 L26 E28 J21 L27 connued... connued... connued... Daashee Volume 1 of 2 March Order No.:

121 Processor all and Sgnal Informaon Processor Sgnal Name all # Sgnal Name all # Sgnal Name all # L28 VDDQ AU20 AC34 L29 VDDQ AU24 AC35 L30 VDDQ AV10 AC36 L31 VDDQ AV11 AC37 L32 VDDQ AV13 AC38 L33 VDDQ AV18 AC39 L34 VDDQ AV23 AC40 M13 VDDQ AV8 AC6 M15 VDDQ AW16 AC7 M17 VDDQ AY12 AD1 M19 VDDQ AY14 AD2 M21 VDDQ AY9 AD3 M23 VIDALERT# 37 AD33 M25 VIDSCLK C38 AD36 M27 VIDSOUT C37 AD4 M29 A11 AD5 M33 A13 AD6 M8 A15 AD7 P8 A17 AD8 _SENSE E40 A23 AE33 IO_OUT L40 A5 AE36 VCOMP_OUT P4 A7 AE37 VDDQ AJ12 AA3 AE40 VDDQ AJ13 AA33 AE5 VDDQ AJ15 AA35 AE8 VDDQ AJ17 AA38 AF1 VDDQ AJ20 AA6 AF33 VDDQ AJ21 AA7 AF36 VDDQ AJ24 AA8 AF4 VDDQ AJ25 A34 AF5 VDDQ AJ28 A37 AF8 VDDQ AJ29 A5 AG33 VDDQ AJ9 A6 AG36 VDDQ AT17 A7 AG37 VDDQ AT22 AC3 AG38 VDDQ AU15 AC33 AG39 connued... connued... connued... March 2015 Daashee Volume 1 of 2 Order No.:

122 Processor Processor all and Sgnal Informaon Sgnal Name all # Sgnal Name all # Sgnal Name all # AG40 AK14 AM2 AG5 AK18 AM24 AG8 AK19 AM27 AH1 AK24 AM3 AH2 AK25 AM30 AH3 AK26 AM31 AH33 AK27 AM32 AH36 AK28 AM33 AH4 AK29 AM34 AH5 AK30 AM35 AH8 AK36 AM36 AJ11 AK4 AM4 AJ14 AK5 AM5 AJ16 AK6 AN10 AJ18 AK7 AN11 AJ19 AK8 AN14 AJ22 AK9 AN16 AJ23 AL11 AN18 AJ26 AL14 AN19 AJ27 AL17 AN22 AJ30 AL21 AN23 AJ31 AL22 AN24 AJ32 AL24 AN27 AJ33 AL27 AN30 AJ34 AL30 AN36 AJ35 AL36 AN37 AJ36 AL37 AN40 AJ37 AL38 AN5 AJ40 AL39 AN6 AJ5 AL40 AN7 AJ8 AL5 AN8 AK1 AM1 AN9 AK10 AM11 AP1 AK11 AM14 AP11 AK12 AM15 AP14 AK13 AM19 AP15 connued... connued... connued... Daashee Volume 1 of 2 March Order No.:

123 Processor all and Sgnal Informaon Processor Sgnal Name all # Sgnal Name all # Sgnal Name all # AP24 AT15 AV7 AP27 AT16 AW26 AP30 AT2 AW3 AP36 AT24 AW30 AP4 AT25 AW32 AP5 AT26 AW34 AR11 AT27 AW36 AR14 AT28 AW7 AR16 AT29 AY17 AR17 AT3 AY23 AR18 AT30 AY26 AR19 AT32 AY27 AR20 AT34 AY30 AR21 AT36 AY5 AR22 AT38 AY7 AR23 AT39 10 AR24 AT4 23 AR27 AT5 24 AR30 AT6 26 AR31 AT7 28 AR32 AT8 30 AR33 AT9 32 AR34 AU2 34 AR35 AU25 36 AR36 AU3 4 AR37 AU30 8 AR38 AU34 C12 AR39 AU38 C14 AR40 AU5 C16 AR5 AU7 C18 AT1 AV21 C19 AT10 AV28 C21 AT11 AV3 C23 AT12 AV30 C3 AT13 AV34 C36 AT14 AV38 C4 connued... connued... connued... March 2015 Daashee Volume 1 of 2 Order No.:

124 Processor Processor all and Sgnal Informaon Sgnal Name all # Sgnal Name all # Sgnal Name all # C6 F22 H30 D11 F24 H32 D13 F26 H34 D15 F28 H36 D17 F30 H39 D2 F32 H4 D23 F34 H7 D24 F36 H8 D26 F4 H9 D28 F7 J11 D30 G11 J14 D32 G12 J18 D34 G13 J19 D36 G14 J20 D37 G15 J3 D5 G16 J36 D6 G17 J37 D7 G21 J6 D9 G3 J7 E10 G36 K1 E18 G37 K10 E20 G6 K14 E22 G7 K15 E23 G9 K16 E3 H1 K17 E36 H10 K18 E38 H11 K20 E6 H13 K22 E7 H17 K24 E8 H18 K26 F1 H20 K28 F12 H21 K30 F14 H22 K32 F16 H24 K34 F19 H26 K36 F21 H28 K4 connued... connued... connued... Daashee Volume 1 of 2 March Order No.:

125 Processor all and Sgnal Informaon Processor Sgnal Name all # Sgnal Name all # Sgnal Name all # K40 N3 T7 K7 N33 U2 L11 N34 U33 L13 N39 U34 L14 N4 U35 L3 N6 U36 L35 N7 U37 L36 N8 U4 L38 P2 U7 L6 P34 V3 L7 P35 V33 L8 P38 V34 L9 P39 V40 M1 P40 V6 M12 P5 V7 M14 P7 V8 M16 R3 W1 M18 R35 W33 M20 R37 W35 M22 R38 W37 M24 R39 W4 M26 R40 W7 M28 R5 Y33 M30 R6 Y4 M32 R7 Y5 M34 R8 Y6 M35 T1 _NCTF AU40 M37 T2 _NCTF AV39 M4 T33 _NCTF AW38 M40 T36 _NCTF AY3 M5 T37 _NCTF 38 M6 T38 _NCTF 39 M7 T39 _NCTF C40 M9 T4 _NCTF D40 N1 T5 _SENSE F40 N2 T6 connued... connued... March 2015 Daashee Volume 1 of 2 Order No.: