Mobile 4th Generation Intel Core Processor Family, Mobile Intel Pentium Processor Family, and Mobile Intel Celeron Processor Family

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1 Moble 4h Generaon Inel Core, Moble Inel Penum, and Moble Inel Celeron Processor Famly Daashee Volume 1 of 2 Supporng 4h Generaon Inel Core processor based on Moble U-Processor and Y-Processor Lnes Supporng Moble Inel Penum and Moble Inel Celeron Processor Famles July 2014 Order No.:

2 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, Y ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED Y THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIAILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIAILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTAILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Msson Crcal Applcaon" s any applcaon n whch falure of he Inel Produc could resul, drecly or ndrecly, n personal njury or deah. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUSIDIARIES, SUCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONALE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIAILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Inel may make changes o specfcaons and produc descrpons a any me, whou noce. Desgners mus no rely on he absence or characerscs of any feaures or nsrucons marked "reserved" or "undefned". Inel reserves hese for fuure defnon and shall have no responsbly whasoever for conflcs or ncompables arsng from fuure changes o hem. The nformaon here s subjec o change whou noce. Do no fnalze a desgn wh hs nformaon. The producs descrbed n hs documen may conan desgn defecs or errors known as erraa whch may cause he produc o devae from publshed specfcaons. Curren characerzed erraa are avalable on reques. Conac your local Inel sales offce or your dsrbuor o oban he laes specfcaons and before placng your produc order. Ths documen conans nformaon on producs n he desgn phase of developmen. Code Names are only for use by Inel o denfy producs, plaforms, programs, servces, ec. ("producs") n developmen by Inel ha have no been made commercally avalable o he publc,.e., announced, launched or shpped. They are never o be used as "commercal" names for producs. Also, hey are no nended o funcon as rademarks. For Enhanced Inel SpeedSep Technology, see he Processor Spec Fnder a hp://ark.nel.com/ or conac your Inel represenave for more nformaon. Inel AES-NI requres a compuer sysem wh an AES-NI enabled processor, as well as non-inel sofware o execue he nsrucons n he correc sequence. AES-NI s avalable on selec Inel processors. For avalably, consul your reseller or sysem manufacurer. For more nformaon, see hp://sofware.nel.com/en-us/arcles/nel-advanced-encrypon-sandard-nsrucons-aes-n/. Inel Hyper-Threadng Technology (Inel HT Technology) s avalable on selec Inel Core processors. I requres an Inel HT Technology enabled sysem. Consul your PC manufacurer. Performance wll vary dependng on he specfc hardware and sofware used. No avalable on Inel Core For more nformaon ncludng deals on whch processors suppor Inel HT Technology, vs hp:// Inel 64 archecure requres a sysem wh a 64-b enabled processor, chpse, IOS and sofware. Performance wll vary dependng on he specfc hardware and sofware you use. Consul your PC manufacurer for more nformaon. For more nformaon, vs hp:// conen/www/us/en/archecure-and-echnology/mcroarchecure/nel-64-archecure-general.hml. No compuer sysem can provde absolue secury under all condons. Inel Trused Execuon Technology (Inel TXT) requres a compuer wh Inel Vrualzaon Technology, an Inel TXT-enabled processor, chpse, IOS, Auhencaed Code Modules and an Inel TXT-compable measured launched envronmen (MLE). Inel TXT also requres he sysem o conan a TPM v1.s. For more nformaon, vs hp:// secury. Inel Vrualzaon Technology (Inel VT) requres a compuer sysem wh an enabled Inel processor, IOS, and vrual machne monor (VMM). Funconaly, performance or oher benefs wll vary dependng on hardware and sofware confguraons. Sofware applcaons may no be compable wh all operang sysems. Consul your PC manufacurer. For more nformaon, vs hp:// Requres a sysem wh Inel Turbo oos Technology. Inel Turbo oos Technology and Inel Turbo oos Technology 2.0 are only avalable on selec Inel processors. Consul your PC manufacurer. Performance vares dependng on hardware, sofware, and sysem confguraon. For more nformaon, vs hp:// Requres acvaon and a sysem wh a corporae nework connecon, an Inel AMT-enabled chpse, nework hardware and sofware. For noebooks, Inel AMT may be unavalable or lmed over a hos OS-based VPN, when connecng wrelessly, on baery power, sleepng, hbernang or powered off. Resuls dependen upon hardware, seup and confguraon. Inel, Inel Core, Celeron, Penum, and he Inel logo are rademarks of Inel Corporaon n he U.S. and/or oher counres. *Oher names and brands may be clamed as he propery of ohers. Copyrgh , Inel Corporaon. All rghs reserved. Daashee Volume 1 of 2 July Order No.:

3 Conens Processors Conens Revson Hsory Inroducon Suppored Technologes Power Managemen Suppor Thermal Managemen Suppor Package Suppor Processor Tesably Termnology Relaed Documens Inerfaces Sysem Memory Inerface Sysem Memory Technology Suppored Sysem Memory Tmng Suppor Sysem Memory Organzaon Modes Sysem Memory Frequency Inel Fas Memory Access (Inel FMA) Technology Enhancemens Daa Scramblng DRAM Clock Generaon DRAM Reference Volage Generaon Processor Graphcs Processor Graphcs Conroller (GT) D and Vdeo Engnes for Graphcs Processng Dgal Dsplay Inerface (DDI) Plaform Envronmenal Conrol Inerface (PECI) PECI us Archecure Technologes Inel Vrualzaon Technology (Inel VT) Inel Trused Execuon Technology (Inel TXT) Inel Hyper-Threadng Technology (Inel HT Technology) Inel Turbo oos Technology Inel Advanced Vecor Exensons 2.0 (Inel AVX2) Inel Advanced Encrypon Sandard New Insrucons (Inel AES-NI) Inel 64 Archecure x2apic Power Aware Inerrup Roung (PAIR) Execue Dsable Inel oo Guard Supervsor Mode Execuon Proecon (SMEP) Inel Transaconal Synchronzaon Exensons - New Insrucons (Inel TSX-NI) Power Managemen Advanced Confguraon and Power Inerface (ACPI) Saes Suppored Processor Core Power Managemen Enhanced Inel SpeedSep Technology Key Feaures Low-Power Idle Saes Requesng Low-Power Idle Saes Core C-Sae Rules...46 July 2014 Daashee Volume 1 of 2 Order No.:

4 Processors Conens Package C-Saes Package C-Saes and Dsplay Resoluons Inegraed Memory Conroller (IMC) Power Managemen Dsablng Unused Sysem Memory Oupus DRAM Power Managemen and Inalzaon DDR Elecrcal Power Gang (EPG) Graphcs Power Managemen Inel Rapd Memory Power Managemen (Inel RMPM) Graphcs Render C-Sae Inel Smar 2D Dsplay Technology (Inel S2DDT) Inel Graphcs Dynamc Frequency Inel Dsplay Power Savng Technology (Inel DPST) Inel Auomac Dsplay rghness Inel Seamless Dsplay Refresh Rae Technology (Inel SDRRS Technology) Thermal Managemen Thermal Consderaons Inel Turbo oos Technology 2.0 Power Monorng Inel Turbo oos Technology 2.0 Power Conrol Package Power Conrol Turbo Tme Parameer Confgurable TDP (ctdp) and Low-Power Mode Confgurable TDP Low-Power Mode Thermal and Power Specfcaons Thermal Managemen Feaures Adapve Thermal Monor Dgal Thermal Sensor PROCHOT# Sgnal On-Demand Mode Inel Memory Thermal Managemen Scenaro Desgn Power (SDP) Sgnal Descrpon Sysem Memory Inerface Sgnals Memory Compensaon and Mscellaneous Sgnals Rese and Mscellaneous Sgnals embedded DsplayPor* (edp*) Sgnals Dsplay Inerface Sgnals Tesably Sgnals Error and Thermal Proecon Sgnals Power Sequencng Sgnals Processor Power Sgnals Sense Sgnals Ground and Non-Crcal o Funcon (NCTF) Sgnals Processor Inernal Pull-Up / Pull-Down Termnaons Elecrcal Specfcaons Inegraed Volage Regulaor Power and Ground Pns V CC Volage Idenfcaon (VID) Daashee Volume 1 of 2 July Order No.:

5 Conens Processors 7.4 Reserved or Unused Sgnals Sgnal Groups Tes Access Por (TAP) Connecon DC Specfcaons Volage and Curren Specfcaons Plaform Envronmen Conrol Inerface (PECI) DC Characerscs Inpu Devce Hyseress Package Specfcaons Package Mechancal Arbues Package Loadng Specfcaons Package Sorage Specfcaons Processor all and Sgnal Informaon July 2014 Daashee Volume 1 of 2 Order No.:

6 Processors Fgures Fgures 1 Plaform lock Dagram Inel Flex Memory Technology Operaons Processor Dsplay Archecure for U- and Y- Processor Lnes DsplayPor* Overvew HDMI* Overvew PECI Hos-Clens Connecon Example Devce o Doman Mappng Srucures Processor Power Saes Processor Package and Core C-Saes Idle Power Managemen reakdown of he Processor Cores Package C-Sae Enry and Ex Package Power Conrol Inpu Devce Hyseress...97 Daashee Volume 1 of 2 July Order No.:

7 Tables Processors Tables 1 Termnology Relaed Documens Processor DIMM Suppor Summary by Produc Suppored DDR3L / DDR3L-RS SO-DIMM Module Confguraons Suppored LPDDR3 Memory Down Confguraons Suppored DDR3L / DDR3L-RS Memory Down Confguraons DRAM Sysem Memory Tmng Suppor Processor Suppored Audo Formas over HDMI*and DsplayPor* Mulple Dsplay Confguraon for U-Processor Lne Mulple Dsplay Confguraon for Y-Processor Lne DsplayPor and embedded DsplayPor* Resoluons per Lnk Daa Rae for U- Processor Lne DsplayPor and embedded DsplayPor* Resoluons per Lnk Daa Rae for Y- Processor Lne Sysem Saes Processor Core / Package Sae Suppor Inegraed Memory Conroller Saes G, S, and C Inerface Sae Combnaons Coordnaon of Core Power Saes a he Package Level Deepes Package C-Sae Avalable U-Processor Lne and Y-Processor Lne Targeed Memory Sae Condons Inel Turbo oos Technology 2.0 Package Power Conrol Sengs Confgurable TDP Modes Thermal Desgn Power (TDP) Specfcaons Juncon Temperaure Specfcaon Maxmum Idle Power Specfcaon Sgnal Descrpon uffer Types DDR3L / DDR3L-RS Memory Channel A Inerface (Memory-Down / SO-DIMM) Sgnals DDR3L / DDR3L-RS Memory Channel Inerface (Memory-Down / SO-DIMM) Sgnals LPDDR3 Memory Channel A Inerface (Memory-Down) Sgnals LPDDR3 Memory Channel Inerface (Memory-Down) Sgnals LPDDR3 / DDR3L / DDR3L-RS Reference and Compensaon Sgnals Rese and Mscellaneous Sgnals embedded Dsplay Por* Sgnals Dsplay Inerface Sgnals Tesably Sgnals Error and Thermal Proecon Sgnals Power Sequencng Sgnals Processor Power Sgnals Sense Sgnals Ground and Non-Crcal o Funcon (NCTF) Sgnals Processor Inernal Pull-Up / Pull-Down Termnaons Volage Regulaor (VR) 12.5 Volage Idenfcaon Sgnal Groups Processor Core Acve and Idle Mode DC Volage and Curren Specfcaons Memory Conroller (V DDQ ) Supply DC Volage and Curren Specfcaons Vcc Susan (Vcc ST ) Supply DC Volage and Curren Specfcaons DDR3L / DDR3L-RS Sgnal Group DC Specfcaons LPDDR3 Sgnal Group DC Specfcaons Dgal Dsplay Inerface Group DC Specfcaons embedded DsplayPor* (edp*) Group DC Specfcaons CMOS Sgnal Group DC Specfcaons GTL Sgnal Group and Open Dran Sgnal Group DC Specfcaons VR Enable CMOS Sgnal Group DC Specfcaon July 2014 Daashee Volume 1 of 2 Order No.:

8 Processors Tables 53 VCOMP_OUT and IO_TERM Plaform Envronmen Conrol Inerface (PECI) DC Elecrcal Lms Package Mechancal Arbues Package Loadng Specfcaons Package Sorage Specfcaons all Ls by Sgnal Name for DDR3L Confguraon all Ls by Sgnal Name for LPDDR3 Confguraon Daashee Volume 1 of 2 July Order No.:

9 Revson Hsory Processors Revson Hsory Revson Descrpon Dae 001 Inal Release June Updaed Secon 1.1, Suppored Technologes Updaed Table 3, Processor DIMM Suppor Summary by Produc Updaed Table 4, Suppored DDR3L / DDR3L-RS SO-DIMM Module Confguraons Updaed Secon 2.4, Dgal Dsplay Inerface (DDI) Updaed Fgure 3, Processor Dsplay Archecure Updaed Table 9, Mulple Dsplay Confguraon for U-Processor Lne Added Table 10, Mulple Dsplay Confguraon for Y-Processor Lne Updaed Table 11, DsplayPor and Embedded DsplayPor* Resoluons per Lnk Daa Rae for U-Processor Lne Added Table 12, DsplayPor and Embedded DsplayPor* Resoluons per Lnk Daa Rae for Y-Processor Lne Updaed Table 16, Inel Turbo oos Technology 2.0 Package Power Conrol Sengs Updaed Table 21, Thermal Desgn power (TDP) Specfcaons Updaed Table 23, Package Turbo Parameers Added Moble 4h Generaon Inel Core Y, Y, Y, U, U, Y, Y, Y, Y, U processors Added Moble Inel Penum 3560Y and 3556U processors Added Moble Inel Celeron 2980U and 2995U processors Added Secon 4.2.6, "Package C-Saes and Dsplay Resoluons". June 2013 Sepember Mnor eds hroughou for clary November Added Moble Inel Penum 3558U and 3561Y processors Added Moble Inel Celeron 2981U and 2957U processors Added Moble 4h Generaon Inel Core U, U, U, U, U, U, Y, Y processors Updaed Secon 6.6, Tesably Secons. Updaed he "Drecon/uffer Type" column n Table 34. Added Moble 4h Generaon Inel Core U, U, U processors December 2013 Aprl 2014 July 2014 July 2014 Daashee Volume 1 of 2 Order No.:

10 Processors Inroducon 1.0 Inroducon The 4h Generaon Inel Core processor based on Moble U-Processor and Y- Processor Lnes, Moble Inel Penum processor famly, and Moble Inel Celeron processor famly are 64-b, mul-core processors bul on 22-nanomeer process echnology. The processors are desgned for a one-chp plaform conssng of a Mul-Chp Package (MCP) processor ha ncludes a low-power Plaform Conroller Hub (PCH) de on he same package as he processor de. See he followng fgure. Throughou hs documen, he 4h Generaon Inel Core processor based on Moble U-Processor and Y-Processor Lnes, Moble Inel Penum processor famly, and Moble Inel Celeron processor famly may be referred o smply as "processor". Throughou hs documen, he 4h Generaon Inel Core processor based on Moble U-Processor and Y-Processor Lnes refers o he Moble 4h Generaon Inel Core U, Y, U, U, U, U, U, U, U, U, Y, Y, U, U, U, U, U, U, Y, U, Y, U, Y, U, U, Y, U, U, Y, Y, U, U, U, and Y processors. Throughou hs documen, he Moble Moble Inel Penum processor famly refers o he Inel Penum 3561Y, 3560Y, 3558U, and 3556U processors. Throughou hs documen, he Moble Inel Celeron processor famly refers o he Inel Celeron 2981U, 2980U, 2957U, and 2955U processors. Noe: Some processor feaures are no avalable on all plaforms. Refer o he processor Specfcaon Updae documen for deals. Daashee Volume 1 of 2 July Order No.:

11 Inroducon Processors Fgure 1. Plaform lock Dagram Dgal Dsplay Inerface x 2 DDIx2 DDR Ch.A DDR Ch. DDR3L/LPDDR3 Embedded DsplayPor* edp Cameras US 2.0 SATA SSD Drve IOS/FW Flash SPI US 2.0/3.0 US 2.0/3.0 Pors TPM SPI HDA/I 2 S HD Audo Codec Touch Screen I 2 C* PECI SMus EC Fngerprn Sensor Gyro US 2.0 I 2 C, UART or US PCI Express* 2.0 x8 US 2.0 T/3G/4G SMus 2.0 SDIO WF / WMax GPS GPIO Ggab Nework Connecon NFC Magneomeer Touch Pad Sensors Hub SD Slo Accelomeer Amben Lgh Sensor 1.1 Suppored Technologes Inel Vrualzaon Technology (Inel VT) Inel Acve Managemen Technology 9.5 (Inel AMT 9.5 ) Inel Trused Execuon Technology (Inel TXT) Inel Sreamng SIMD Exensons 4.2 (Inel SSE4.2) Inel Hyper-Threadng Technology (Inel HT Technology) Inel 64 Archecure Execue Dsable Inel Turbo oos Technology 2.0 Inel Advanced Vecor Exensons 2.0 (Inel AVX2) Inel Advanced Encrypon Sandard New Insrucons (Inel AES-NI) PCLMULQDQ Insrucon Inel Secure Key July 2014 Daashee Volume 1 of 2 Order No.:

12 Processors Inroducon Inel Transaconal Synchronzaon Exensons - New Insrucons (Inel TSX- NI) PAIR Power Aware Inerrup Roung SMEP Supervsor Mode Execuon Proecon oo Guard Noe: 1.2 The avalably of he feaures may vary beween processor SKUs. Power Managemen Suppor Processor Core Full suppor of ACPI C-saes as mplemened by he followng processor C-saes: C0, C1, C1E, C3, C6, C7, C8, C9, C10 Enhanced Inel SpeedSep Technology Sysem S0, S3, S4, S5 Memory Conroller Condonal self-refresh Dynamc power-down Processor Graphcs Conroller Inel Rapd Memory Power Managemen (Inel RMPM) Inel Smar 2D Dsplay Technology (Inel S2DDT) Graphcs Render C-sae (RC6) Inel Seamless Dsplay Refresh Rae Swchng wh edp por Inel Dsplay Power Savng Technology (Inel DPST) 1.3 Thermal Managemen Suppor Dgal Thermal Sensor Adapve Thermal Monor THERMTRIP# and PROCHOT# suppor On-Demand Mode Memory Open and Closed Loop Throlng Memory Thermal Throlng Exernal Thermal Sensor (TS-on-DIMM and TS-on-oard) Render Thermal Throlng Fan speed conrol wh DTS Daashee Volume 1 of 2 July Order No.:

13 Inroducon Processors 1.4 Package Suppor The processor s avalable n he followng package: A 40 mm x 24 mm x 1.5 mm GA package (GA1168) 1.5 Processor Tesably The processor ncludes boundary-scan for board and sysem level esably. 1.6 Table 1. Termnology Termnology Term Descrpon APD /D/F GA LC LT PP CKE CLTM DDI DDR3 DDR3L DDR3L-RS DLL DMA DP DTS EC ECC edp* EPG EU FMA FSC HDCP HDMI* HFM Acve Power-down us/devce/funcon all Grd Array acklgh Compensaon lock Level Transfer s per pxel Clock Enable Closed Loop Thermal Managemen Dgal Dsplay Inerface Thrd-generaon Double Daa Rae SDRAM memory echnology DDR3 Low Volage DDR3 Low Volage Reduced Sandby Power Delay-Locked Loop Drec Memory Access DsplayPor* Dgal Thermal Sensor Embedded Conroller Error Correcon Code embedded DsplayPor* Elecrcal Power Gang Execuon Un Floang-pon fused Mulply Add nsrucons Fan Speed Conrol Hgh-bandwdh Dgal Conen Proecon Hgh Defnon Mulmeda Inerface Hgh Frequency Mode July 2014 Daashee Volume 1 of 2 Order No.:

14 Processors Inroducon Term Descrpon DCT IHS GFX GUI IMC Inel 64 Technology Inel DPST Inel TSX-NI Inel TXT Inel VT Inel VT-d IOV ISI ITPM LFM LFP LPDDR3 MCP MFM MLE MLC MSI MSL MSR NCTF ODT OLTM PCG PCH Inverse Dscree Inegraed Hea Spreader Graphcs Graphcal User Inerface Inegraed Memory Conroller 64-b memory exensons o he IA-32 archecure Inel Dsplay Power Savng Technology Inel Transaconal Synchronzaon Exensons - New Insrucons Inel Trused Execuon Technology Inel Vrualzaon Technology. Processor vrualzaon, when used n conjuncon wh Vrual Machne Monor sofware, enables mulple, robus ndependen sofware envronmens nsde a sngle plaform. Inel Vrualzaon Technology (Inel VT) for Dreced I/O. Inel VT-d s a hardware asss, under sysem sofware (Vrual Machne Manager or OS) conrol, for enablng I/O devce vrualzaon. Inel VT-d also brngs robus secury by provdng proecon from erran DMAs by usng DMA remappng, a key feaure of Inel VT-d. I/O Vrualzaon Iner-Symbol Inerference Inegraed Trused Plaform Module Low Frequency Mode. LFM s Pn n he P-sae able. I can be read a MSR CEh [47:40]. Local Fla Panel Low-Power Thrd-generaon Double Daa Rae SDRAM memory echnology Mul-Chp Package Mnmum Frequency Mode. MFM s he mnmum rao suppored by he processor and can be read from MSR CEh [55:48]. Measured Launched Envronmen Md-Level Cache Message Sgnaled Inerrup Mosure Sensve Labelng Model Specfc Regsers Non-Crcal o Funcon. NCTF locaons are ypcally redundan ground or non-crcal reserved, so he loss of he solder jon connuy a end of lfe condons wll no affec he overall produc funconaly. On-De Termnaon Open Loop Thermal Managemen Plaform Compably Gude (PCG) (prevously known as FM) provdes a desgn arge for meeng all planned processor frequency requremens. Plaform Conroller Hub. The chpse wh cenralzed plaform capables ncludng he man I/O nerfaces along wh dsplay connecvy, audo feaures, power managemen, manageably, secury, and sorage feaures. Daashee Volume 1 of 2 July Order No.:

15 Inroducon Processors Term Descrpon PECI The Plaform Envronmen Conrol Inerface (PECI) s a one-wre nerface ha provdes a communcaon channel beween Inel processor and chpse componens o exernal monorng devces. PL1, PL2 Power Lm 1 and Power Lm 2 PPD Processor Processor Core Processor Graphcs Rank SCI SDP SF SMM SMX Sorage Condons SVID TAC TAP T CASE TCC T CONTROL TDP TL TTV TM V CC V DDQ VF Pre-charge Power-down The 64-b mul-core componen (package) The erm processor core refers o S de self, whch can conan mulple execuon cores. Each execuon core has an nsrucon cache, daa cache, and 256-K L2 cache. All execuon cores share he L3 cache. Inel Processor Graphcs A un of DRAM correspondng o four o egh devces n parallel, gnorng ECC. These devces are usually, bu no always, mouned on a sngle sde of a SO-DIMM. Sysem Conrol Inerrup. SCI s used n he ACPI proocol. Scenaro Desgn Power Srps and Fans Sysem Managemen Mode Safer Mode Exensons A non-operaonal sae. The processor may be nsalled n a plaform, n a ray, or loose. Processors may be sealed n packagng or exposed o free ar. Under hese condons, processor landngs should no be conneced o any supply volages, have any I/Os based, or receve any clocks. Upon exposure o free ar (ha s, unsealed packagng or a devce removed from packagng maeral), he processor mus be handled n accordance wh mosure sensvy labelng (MSL) as ndcaed on he packagng maeral. Seral Volage Idenfcaon Thermal Averagng Consan Tes Access Pon The case emperaure of he processor, measured a he geomerc cener of he opsde of he TTV IHS. Thermal Conrol Crcu T CONTROL s a sac value ha s below he TCC acvaon emperaure and used as a rgger pon for fan speed conrol. When DTS > T CONTROL, he processor mus comply o he TTV hermal profle. Thermal Desgn Power: Thermal soluon should be desgned o dsspae hs arge power level. TDP s no he maxmum power ha he processor can dsspae. Translaon Look-asde uffer Thermal Tes Vehcle. A mechancally equvalen package ha conans a ressve heaer n he de o evaluae hermal soluons. Thermal Monor. A power reducon feaure desgned o decrease emperaure afer he processor has reached s maxmum operang emperaure. Processor core power supply DDR3L and LPDDR3 power supply. Verex Fech VID Volage Idenfcaon July 2014 Daashee Volume 1 of 2 Order No.:

16 Processors Inroducon Term Descrpon VS VLD VMM VR V SS Verex Shader Varable Lengh Decodng Vrual Machne Monor Volage Regulaor Processor ground 1.7 Table 2. Relaed Documens Relaed Documens Documen Documen Number / Locaon Moble 4h Generaon Inel Core, Moble Inel Penum, and Moble Inel Celeron Daashee, Volume 2 of 2 Supporng 4h Generaon Inel Core processor based on Moble U-Processor and Y-Processor Lnes Moble 4h Generaon Inel Core, Moble Inel Penum, and Moble Inel Celeron Specfcaon Updae Moble 4h Generaon Inel Core Processor I/O Famly Daashee Moble 4h Generaon Inel Core Processor I/O Famly Specfcaon Updae Advanced Confguraon and Power Inerface 3.0 PCI Local us Specfcaon 3.0 PCI Express ase Specfcaon, Revson 2.0 DDR3 SDRAM Specfcaon DsplayPor* Specfcaon Inel 64 and IA-32 Archecures Sofware Developer's Manuals hp:// hp:// specfcaons hp:// hp:// hp:// hp:// producs/processor/ manuals/ndex.hm Daashee Volume 1 of 2 July Order No.:

17 Inerfaces Processors 2.0 Inerfaces 2.1 Sysem Memory Inerface Two channels of DDR3L/DDR3L-RS and LPDDR3 memory wh Unbuffered Small Oulne Dual In-Lne Memory Modules (SO-DIMM) wh a maxmum of one DIMM per channel and memory down. Sngle-channel and dual-channel memory organzaon modes Daa burs lengh of egh for all memory organzaon modes DDR3L/DDR3L-RS I/O Volage of 1.35V 64-b wde channels Non-ECC, Unbuffered DDR3L/DDR3L-RS SO-DIMMs and memory down Theorecal maxmum memory bandwdh of: 21.3 G/s n dual-channel mode assumng DDR3L/DDR3L-RS/LPDDR MT/s 25.6 G/s n dual-channel mode assumng DDR3L/DDR3L-RS/LPDDR MT/s Sysem Memory Technology Suppored The Inegraed Memory Conroller (IMC) suppors DDR3L/DDR3L-RS and LPDDR3 proocols wh wo ndependen, 64-b wde channels. I suppors one unbuffered non- ECC DDR3L/DDR3L-RS DIMM per channel; hus, allowng up o wo devce ranks per channel. Table 3. Processor DIMM Suppor Summary by Produc Processors TDP Graphcs Confguraon DIMM Per Channel DDR3L / DDR3L-RS (MT/s) LPDDR3 (MT/s) 28W GT3 1 DPC 1333/1600 N/A U-Processor (Dual-Core) Y-Processor (Dual-Core) 15W 11.5W (6W SDP / 4.5W SDP) GT3 1 DPC 1333/ /1600 GT2 1 DPC 1333/ /1600 GT1 1 DPC 1333/ /1600 GT1, GT2 1 DPC 1333/ /1600 Noes: 1. LPDDR3 suppor may vary beween he processor SKUs. 2. DDR3L-RS s suppored as a memory confguraon. Acual valdaon checkou depends on pars and vendor avalably. July 2014 Daashee Volume 1 of 2 Order No.:

18 Processors Inerfaces Daa Transfer Raes: DDR3L-RS s suppored as a memory confguraon. Acual valdaon checkou depends on pars and vendor avalably MT/s (PC ) 1600 MT/s (PC ) SO-DIMM Modules: Sandard 2Gb and 4Gb echnologes and addressng are suppored for x8 and x16 devces. There s no suppor for memory modules wh dfferen echnologes or capaces on oppose sdes of he same memory module. If one sde of a memory module s populaed, he oher sde s eher dencal or empy. LPDDR3 Memory Down: Quad Ranked x16 Sngle and Dual Ranked x32 Table 4. Suppored DDR3L / DDR3L-RS SO-DIMM Module Confguraons Raw Card Verson DIMM Capacy DRAM Organzaon # of DRAM Devces # of Row/Col Address s # of anks Insde DRAM Page Sze A 4 G 256 M x /10 8 8K 4 G 512 M x /10 8 8K C 2 G 256 M x /10 8 8K F 4 G 256 M x /10 8 8K F 8 G 512 M x /10 8 8K Table 5. Suppored LPDDR3 Memory Down Confguraons DIMM Capacy PKG Type (Des bs x PKG bs) De Densy PKG Densy Des Per Channel PKGs per Channel Physcal Devce Rank anks Insde DRAM Page Sze 2 G SDP 32 x32 4 Gb 4 Gb K 4 G DDP 32 x32 4 Gb 8 Gb K 8 G QDP 16 x32 4 Gb 16 Gb K Noe: SDP = Sngle De Package, DDP = Dual De Package, QDP = Quad De Package Table 6. Suppored DDR3L / DDR3L-RS Memory Down Confguraons Sysem Capacy DRAM Organzaon Des Per Package PKG Densy De Densy Des Per Channel PKGs Per Channel Physcal Devce Rank anks Insde DRAM Page Sze 2 G 128 M x 16 SDP 2 Gb 2 Gb K 4 G 256 M x 16 SDP 4 Gb 4 Gb K 8 G 256 M x 16 DDP 8 Gb 4 Gb K Noe: SDP = Sngle De Package, DDP = Dual De Package Daashee Volume 1 of 2 July Order No.:

19 Inerfaces Processors Sysem Memory Tmng Suppor The IMC suppors he followng DDR3L/DDR3L-RS Speed n, CAS Wre Laency (CWL), and command sgnal mode mngs on he man memory nerface: CL = CAS Laency RCD = Acvae Command o READ or WRITE Command delay RP = PRECHARGE Command Perod CWL = CAS Wre Laency Command Sgnal modes = 1N ndcaes a new command may be ssued every clock and 2N ndcaes a new command may be ssued every 2 clocks. Command launch mode programmng depends on he ransfer rae and memory confguraon. Table 7. DRAM Sysem Memory Tmng Suppor Segmen DRAM Devce Transfer Rae (MT/s) CL (CK) RCD (CK) RP (CK) CWL (CK) DPC (SO- DIMM Only) CMD Mode DDR3L/ DDR3L-RS /9 8/9 8/ N/2N U-Processor / Y-Processor (Dual Core) LPDDR N DDR3L/ DDR3L-RS /11 10/11 10/ N/2N LPDDR N Sysem Memory Organzaon Modes The Inegraed Memory Conroller (IMC) suppors wo memory organzaon modes sngle-channel and dual-channel. Dependng upon how he DIMM Modules are populaed n each memory channel, a number of dfferen confguraons can exs. Sngle-Channel Mode In hs mode, all memory cycles are dreced o a sngle-channel. Sngle-channel mode s used when eher Channel A or Channel DIMM connecors are populaed n any order, bu no boh. Dual-Channel Mode Inel Flex Memory Technology Mode The IMC suppors Inel Flex Memory Technology Mode. Memory s dvded no symmerc and asymmerc zones. The symmerc zone sars a he lowes address n each channel and s conguous unl he asymmerc zone begns or unl he op address of he channel wh he smaller capacy s reached. In hs mode, he sysem runs wh one zone of dual-channel mode and one zone of sngle-channel mode, smulaneously, across he whole memory array. Noe: Channels A and can be mapped for physcal channel 0 and 1 respecvely or vce versa; however, channel A sze mus be greaer or equal o channel sze. July 2014 Daashee Volume 1 of 2 Order No.:

20 Processors Inerfaces Fgure 2. Inel Flex Memory Technology Operaons TOM C Non nerleaved access C Dual channel nerleaved access CH A CH CH A and CH can be confgured o be physcal channels 0 or 1 The larges physcal memory amoun of he smaller sze memory module C The remanng physcal memory amoun of he larger sze memory module Dual-Channel Symmerc Mode Dual-Channel Symmerc mode, also known as nerleaved mode, provdes maxmum performance on real world applcaons. Addresses are png-ponged beween he channels afer each cache lne (64-bye boundary). If here are wo requess, and he second reques s o an address on he oppose channel from he frs, ha reques can be sen before daa from he frs reques has reurned. If wo consecuve cache lnes are requesed, boh may be rereved smulaneously, snce hey are ensured o be on oppose channels. Use Dual-Channel Symmerc mode when boh Channel A and Channel DIMM connecors are populaed n any order, wh he oal amoun of memory n each channel beng he same. When boh channels are populaed wh he same memory capacy and he boundary beween he dual channel zone and he sngle channel zone s he op of memory, he IMC operaes compleely n Dual-Channel Symmerc mode. Noe: The DRAM devce echnology and wdh may vary from one channel o he oher. Sysem Memory Frequency In all modes, he frequency of sysem memory s he lowes frequency of all memory modules placed n he sysem, as deermned hrough he SPD regsers on he memory modules. The sysem memory conroller suppors up o wo DIMM connecors per channel. If DIMMs wh dfferen laency are populaed across he channels, he IOS wll use he slower of he wo laences for boh channels. For dual-channel mode boh channels mus have a DIMM connecor populaed. For sngle-channel mode, only a sngle channel can have a DIMM connecor populaed Inel Fas Memory Access (Inel FMA) Technology Enhancemens The followng secons descrbe he Jus-n-Tme Schedulng, Command Overlap, and Ou-of-Order Schedulng Inel FMA echnology enhancemens. Daashee Volume 1 of 2 July Order No.:

21 Inerfaces Processors Jus-n-Tme Command Schedulng The memory conroller has an advanced command scheduler where all pendng requess are examned smulaneously o deermne he mos effcen reques o be ssued nex. The mos effcen reques s pcked from all pendng requess and ssued o sysem memory Jus-n-Tme o make opmal use of Command Overlappng. Thus, nsead of havng all memory access requess go ndvdually hrough an arbraon mechansm forcng requess o be execued one a a me, he requess can be sared whou nerferng wh he curren reques allowng for concurren ssung of requess. Ths allows for opmzed bandwdh and reduced laency whle mananng approprae command spacng o mee sysem memory proocol. Command Overlap Command Overlap allows he nseron of he DRAM commands beween he Acvae, Pre-charge, and Read/Wre commands normally used, as long as he nsered commands do no affec he currenly execung command. Mulple commands can be ssued n an overlappng manner, ncreasng he effcency of sysem memory proocol. Ou-of-Order Schedulng Whle leveragng he Jus-n-Tme Schedulng and Command Overlap enhancemens, he IMC connuously monors pendng requess o sysem memory for he bes use of bandwdh and reducon of laency. If here are mulple requess o he same open page, hese requess would be launched n a back-o-back manner o make opmum use of he open memory page. Ths ably o reorder requess on he fly allows he IMC o furher reduce laency and ncrease bandwdh effcency Daa Scramblng The sysem memory conroller ncorporaes a Daa Scramblng feaure o mnmze he mpac of excessve d/d on he plaform sysem memory VRs due o successve 1s and 0s on he daa bus. Pas experence has demonsraed ha raffc on he daa bus s no random and can have energy concenraed a specfc specral harmoncs creang hgh d/d, whch s generally lmed by daa paerns ha exce resonance beween he package nducance and on de capacances. As a resul, he sysem memory conroller uses a daa scramblng feaure o creae pseudo-random paerns on he sysem memory daa bus o reduce he mpac of any excessve d/d DRAM Clock Generaon Every suppored DIMM has wo dfferenal clock pars. There are a oal of four clock pars drven drecly by he processor o wo DIMMs DRAM Reference Volage Generaon The memory conroller has he capably of generang he DDR3L/DDR3L-RS Reference Volage (VREF) nernally for boh read (RDVREF) and wre (VREFDQ) operaons. The generaed VREF can be changed n small seps, and an opmum VREF value s deermned for boh durng a cold boo hrough advanced DDR3L/DDR3L-RS ranng procedures o provde he bes volage and sgnal margns. July 2014 Daashee Volume 1 of 2 Order No.:

22 Processors Inerfaces 2.2 Processor Graphcs The processor graphcs conans a generaon 7.5 graphcs core archecure. Ths enables subsanal gans n performance and lower power consumpon over prevous generaons. Up o 40 Execuon Uns are suppored dependng on he processor SKU. Nex Generaon Inel Clear Vdeo Technology HD Suppor s a collecon of vdeo playback and enhancemen feaures ha mprove he end user s vewng experence Encode / ranscode HD conen Playback of hgh defnon conen ncludng lu-ray Dsc* Superor mage qualy wh sharper, more colorful mages Playback of lu-ray* dsc S3D conen usng HDMI (1.4a specfcaon complan wh 3D) DrecX* Vdeo Acceleraon (DXVA) suppor for accelerang vdeo processng Full AVC/VC1/MPEG2 HW Decode Advanced Scheduler 2.0, 1.0, XPDM suppor Wndows* 8, Wndows* 7, OSX, Lnux* operang sysem suppor DrecX* 11.1, DrecX* 11, DrecX* 10.1, DrecX* 10, DrecX* 9 suppor. OpenGL* 4.0, suppor 2.3 Processor Graphcs Conroller (GT) The Graphcs Engne Archecure ncludes 3D compue elemens, Mul-forma HW asssed decode/encode ppelne, and Md-Level Cache (MLC) for superor hgh defnon playback, vdeo qualy, and mproved 3D performance and meda. The Dsplay Engne handles delverng he pxels o he screen. GSA (Graphcs n Sysem Agen) s he prmary channel nerface for dsplay memory accesses and PCI-lke raffc n and ou D and Vdeo Engnes for Graphcs Processng The Gen 7.5 3D engne provdes he followng performance and power-managemen enhancemens. 3D Ppelne The 3D graphcs ppelne archecure smulaneously operaes on dfferen prmves or on dfferen porons of he same prmve. All he cores are fully programmable, ncreasng he versaly of he 3D Engne. 3D Engne Execuon Uns Suppors up o 40 EUs.. The EUs perform 128-b wde execuon per clock. Suppor SIMD8 nsrucons for verex processng and SIMD16 nsrucons for pxel processng. Daashee Volume 1 of 2 July Order No.:

23 Inerfaces Processors Verex Fech (VF) Sage The VF sage execues 3DPRIMITIVE commands. Some enhancemens have been ncluded o beer suppor legacy D3D APIs as well as SGI OpenGL*. Verex Shader (VS) Sage The VS sage performs shadng of verces oupu by he VF funcon. The VS un produces an oupu verex reference for every npu verex reference receved from he VF un, n he order receved. Geomery Shader (GS) Sage The GS sage receves npus from he VS sage. Compled applcaon-provded GS programs, specfyng an algorhm o conver he verces of an npu objec no some oupu prmves. For example, a GS shader may conver lnes of a lne srp no polygons represenng a correspondng segmen of a blade of grass cenered on he lne. Or could use adjacency nformaon o deec slhouee edges of rangles and oupu polygons exrudng ou from he edges. Clp Sage The Clp sage performs general processng on ncomng 3D objecs. However, also ncludes specalzed logc o perform a Clp Tes funcon on ncomng objecs. The Clp Tes opmzes generalzed 3D Clppng. The Clp un examnes he poson of ncomng verces, and acceps/rejecs 3D objecs based on s Clp algorhm. Srps and Fans (SF) Sage The SF sage performs seup operaons requred o raserze 3D objecs. The oupus from he SF sage o he Wndower sage conan mplemenaon-specfc nformaon requred for he raserzaon of objecs and also suppors clppng of prmves o some exen. Wndower / IZ (WIZ) Sage The WIZ un performs an early deph es, whch removes falng pxels and elmnaes unnecessary processng overhead. The Wndower uses he parameers provded by he SF un n he objec-specfc raserzaon algorhms. The WIZ un raserzes objecs no he correspondng se of pxels. The Wndower s also capable of performng dherng, whereby he lluson of a hgher resoluon when usng low-bpp channels n color buffers s possble. Color dherng dffuses he sharp color bands seen on smooh-shaded objecs. Vdeo Engne The Vdeo Engne handles he non-3d (meda/vdeo) applcaons. I ncludes suppor for VLD and MPEG2 decode n hardware. 2D Engne The 2D Engne conans LT (lock Level Transfer) funconaly and an exensve se of 2D nsrucons. To ake advanage of he 3D durng engne s funconaly, some LT funcons make use of he 3D renderer. July 2014 Daashee Volume 1 of 2 Order No.:

24 Processors Inerfaces Logcal 128- Fxed LT and 256 Fll Engne Ths LT engne acceleraes he GUI of Mcrosof Wndows* operang sysems. The 128-b LT engne provdes hardware acceleraon of block ransfers of pxel daa for many common Wndows operaons. The LT engne can be used for he followng: Move recangular blocks of daa beween memory locaons Daa algnmen To perform logcal operaons (raser ops) The recangular block of daa does no change, as s ransferred beween memory locaons. The allowable memory ransfers are beween: cacheable sysem memory and frame buffer memory, frame buffer memory and frame buffer memory, and whn sysem memory. Daa o be ransferred can conss of regons of memory, paerns, or sold color flls. A paern s always 8 x 8 pxels wde and may be 8, 16, or 32 bs per pxel. The LT engne expands monochrome daa no a color deph of 8, 16, or 32 bs. LTs can be eher opaque or ransparen. Opaque ransfers move he daa specfed o he desnaon. Transparen ransfers compare desnaon color o source color and wre accordng o he mode of ransparency seleced. Daa s horzonally and vercally algned a he desnaon. If he desnaon for he LT overlaps wh he source memory locaon, he LT engne specfes whch area n memory o begn he LT ransfer. Hardware s ncluded for all 256 raser operaons (source, paern, and desnaon) defned by Mcrosof*, ncludng ransparen LT. The LT engne has nsrucons o nvoke LT and srech LT operaons, permng sofware o se up nsrucon buffers and use bach processng. The LT engne can perform hardware clppng durng LTs. 2.4 Dgal Dsplay Inerface (DDI) The processor suppors: Two Dgal Dsplay (x4 DDI) nerfaces ha can be confgured as DsplayPor*, HDMI*. The DsplayPor* can be confgured o use 1, 2, or 4 lanes dependng on he bandwdh requremens and lnk daa rae of RR (1.62 GT/s), HR (2.97 GT/s), and HR2 (5.4 GT/s). When confgured as HDMI*, he DDIx4 por can suppor 2.97 GT/s. One dedcaed x4 embedded DsplayPor* (edp*). ul-n dsplays are only suppored on edp. The HDMI* nerface suppors HDMI wh 3D, 4K, Deep Color, and x.v.color. The DsplayPor* nerface suppors he VESA DsplayPor* Sandard Verson 1, Revson 2. The processor suppors Hgh-bandwdh Dgal Conen Proecon (HDCP) for hgh-defnon conen playback over dgal nerfaces. The processor also negraes dedcaed a Mn HD audo conroller o drve audo on negraed dgal dsplay nerfaces, such as HDMI* and DsplayPor*. The HD audo conroller on he PCH would connue o suppor down CODECs, and so on. The processor Mn HD audo conroller suppors wo Hgh-Defnon Audo sreams smulaneously on any of he hree dgal pors. Daashee Volume 1 of 2 July Order No.:

25 Memory \ Confg Inerface Panel Fng Por Mux DDI Pors and C PCH Dsplay Conrol Sgnals Inerfaces Processors The processor suppors sreamng any 3 ndependen and smulaneous dsplay combnaon of DsplayPor*/HDMI*/eDP*/ monors. In he case of 3 smulaneous dsplays, wo Hgh Defnon Audo sreams over he dgal dsplay nerfaces are suppored. Each dgal por s capable of drvng resoluons up o 3200x2000 a 60 Hz hrough DsplayPor* and 4096x2304 a 24 Hz usng HDMI*. DsplayPor* Aux CH, DDC channel, Panel power sequencng, and HPD are suppored hrough he PCH. Fgure 3. Processor Dsplay Archecure for U- and Y- Processor Lnes edp* Mux Transcoder edp* DP encoder Tmng, VDIP DPT, SRID DP Aux edp X4 edp Dsplay Ppe A Transcoder A DP / HDMI Tmng, VDIP Dsplay Ppe Transcoder DP / HDMI Tmng, VDIP X4 DP / HDMI X4 DP / HDMI Dsplay Ppe C Transcoder C DP / HDMI Tmng, VDIP HD Audo Conroller Audo Codec Dsplay s he presenaon sage of graphcs. Ths nvolves: Pullng rendered daa from memory Converng raw daa no pxels lendng surfaces no a frame Organzng pxels no frames Oponally scalng he mage o he desred sze Re-mng daa for he nended arge Formang daa accordng o he por oupu sandard DsplayPor* DsplayPor* s a dgal communcaon nerface ha uses dfferenal sgnalng o acheve a hgh-bandwdh bus nerface desgned o suppor connecons beween PCs and monors, projecors, and TV dsplays. July 2014 Daashee Volume 1 of 2 Order No.:

26 Processors Inerfaces A DsplayPor* consss of a Man Lnk, Auxlary channel, and a Ho-Plug Deec sgnal. The Man Lnk s a undreconal, hgh-bandwdh, and low laency channel used for ranspor of sochronous daa sreams such as uncompressed vdeo and audo. The Auxlary Channel (AUX CH) s a half-duplex bdreconal channel used for lnk managemen and devce conrol. The Ho-Plug Deec (HPD) sgnal serves as an nerrup reques for he snk devce. The processor s desgned n accordance wh he VESA DsplayPor* Sandard Verson 1.2a. The processor suppors VESA DsplayPor* PHY Complance Tes Specfcaon 1.2a and VESA DsplayPor* Lnk Layer Complance Tes Specfcaon 1.2a. Fgure 4. DsplayPor* Overvew Source Devce DsplayPor Tx Man Lnk (Isochronous Sreams) Snk Devce DsplayPor Rx AUX CH (Lnk/Devce Manageme) Ho-Plug Deec (Inerrup Reques) Hgh-Defnon Mulmeda Inerface (HDMI*) The Hgh-Defnon Mulmeda Inerface* (HDMI*) s provded for ransmng uncompressed dgal audo and vdeo sgnals from DVD players, se-op boxes, and oher audovsual sources o elevson ses, projecors, and oher vdeo dsplays. I can carry hgh qualy mul-channel audo daa and all sandard and hgh-defnon consumer elecroncs vdeo formas. The HDMI dsplay nerface connecng he processor and dsplay devces uses ranson mnmzed dfferenal sgnalng (TMDS) o carry audovsual nformaon hrough he same HDMI cable. HDMI ncludes hree separae communcaons channels TMDS, DDC, and he oponal CEC (consumer elecroncs conrol). CEC s no suppored on he processor. As shown n he followng fgure, he HDMI cable carres four dfferenal pars ha make up he TMDS daa and clock channels. These channels are used o carry vdeo, audo, and auxlary daa. In addon, HDMI carres a VESA DDC. The DDC s used by an HDMI Source o deermne he capables and characerscs of he Snk. Audo, vdeo, and auxlary (conrol/saus) daa s ransmed across he hree TMDS daa channels. The vdeo pxel clock s ransmed on he TMDS clock channel and s used by he recever for daa recovery on he hree daa channels. The dgal dsplay daa sgnals drven navely hrough he PCH are AC coupled and needs level shfng o conver he AC coupled sgnals o he HDMI complan dgal sgnals. The processor HDMI nerface s desgned n accordance wh he Hgh-Defnon Mulmeda Inerface wh 3D, 4K, Deep Color, and x.v.color. Daashee Volume 1 of 2 July Order No.:

27 Inerfaces Processors Fgure 5. HDMI* Overvew HDMI Source HDMI Tx TMDS Daa Channel 0 HDMI Snk HDMI Rx TMDS Daa Channel 1 TMDS Daa Channel 2 TMDS Clock Channel Ho-Plug Deec Dsplay Daa Channel (DDC) CEC Lne (oponal) embedded DsplayPor* The embedded DsplayPor* (edp*) s an embedded verson of he DsplayPor sandard orened owards applcaons such as noebook and All-In-One PCs. Lke DsplayPor, embedded DsplayPor also consss of a Man Lnk, Auxlary channel, and an oponal Ho-Plug Deec sgnal. Inegraed Audo HDMI and dsplay por nerfaces carry audo along wh vdeo. Processor suppors wo DMA conrollers o oupu wo Hgh Defnon audo sreams on wo dgal pors smulaneously. Suppors only he nernal HDMI and DP CODECs. Table 8. Processor Suppored Audo Formas over HDMI*and DsplayPor* Audo Formas HDMI* DsplayPor* AC-3 Dolby* Dgal Yes Yes Dolby Dgal Plus Yes Yes DTS-HD* Yes Yes LPCM, 192 khz/24 b, 8 Channel Yes Yes Dolby TrueHD, DTS-HD Maser Audo* (Lossless lu-ray Dsc* Audo Forma) Yes Yes July 2014 Daashee Volume 1 of 2 Order No.:

28 Processors Inerfaces The processor wll connue o suppor Slen sream. Slen sream s an negraed audo feaure ha enables shor audo sreams, such as sysem evens o be heard over he HDMI and DsplayPor monors. The processor suppors slen sreams over he HDMI and DsplayPor nerfaces a 44.1 khz, 48 khz, 88.2 khz, 96 khz, khz, and 192 khz samplng raes. Mulple Dsplay Confguraons The followng mulple dsplay confguraon modes are suppored (wh approprae drver sofware): Sngle Dsplay s a mode wh one dsplay por acvaed o dsplay he oupu o one dsplay devce. Inel Dsplay Clone s a mode wh up o hree dsplay pors acvaed o drve he dsplay conen of same color deph seng bu poenally dfferen refresh rae and resoluon sengs o all he acve dsplay devces conneced. Exended Deskop s a mode wh up o hree dsplay pors acvaed o drve he conen wh poenally dfferen color deph, refresh rae, and resoluon sengs on each of he acve dsplay devces conneced. The dgal pors on he processor can be confgured o suppor DsplayPor*/HDMI. The followng able shows examples of vald hree dsplay confguraons hrough he processor. Table 9. Mulple Dsplay Confguraon for U-Processor Lne Dsplay 1 Dsplay 2 Dsplay 3 Maxmum Resoluon Dsplay 1 Maxmum Resoluon Dsplay 2 Maxmum Resoluon Dsplay 3 HDMI HDMI edp 24 Hz DP DP edp 60 Hz 60 Hz 60 Hz HDMI DP edp 24Hz 60 Hz 60 Hz Noe: DP and edp resoluons n hs able are suppored for 4 lanes wh lnk daa rae HR2 a 24 bs per pxel (bpp) and sngle sream mode of operaon. Table 10. Mulple Dsplay Confguraon for Y-Processor Lne Dsplay 1 Dsplay 2 Dsplay 3 Maxmum Resoluon Dsplay 1 Maxmum Resoluon Dsplay 2 Maxmum Resoluon Dsplay 3 HDMI HDMI edp 24 Hz DP DP edp 60 Hz 60 Hz 60 Hz HDMI DP edp 24 Hz 60 Hz 60 Hz Noe: 1. DP and edp resoluons n hs able are suppored for 4 lanes wh lnk daa rae HR2 a 24 bs per pxel (bpp) and sngle sream mode of operaon. Daashee Volume 1 of 2 July Order No.:

29 Inerfaces Processors Table 11. DsplayPor and embedded DsplayPor* Resoluons per Lnk Daa Rae for U-Processor Lne Lnk Daa Rae Lane Coun RR 1064x x x1400 HR 1280x x x1800 HR2 1920x x x2000 Noe: The above resoluons are vald a 60 Hz refresh rae and 24 bs per pxel (bpp). Table 12. DsplayPor and embedded DsplayPor* Resoluons per Lnk Daa Rae for Y- Processor Lne Lnk Daa Rae Lane Coun RR 1064x x x1400 HR 1280x x Hz Noe: The above resoluons are vald a 60 Hz refresh rae and 24 bs per pxel (bpp). Hgh-bandwdh Dgal Conen Proecon (HDCP) HDCP s he echnology for proecng hgh-defnon conen agans unauhorzed copy or unrecepve beween a source (compuer, dgal se op boxes, and so on) and he snk (panels, monor, and TVs). The processor suppors HDCP 1.4 for conen proecon over wred dsplays (HDMI* and DsplayPor*). The HDCP 1.4 keys are negraed no he processor and cusomers are no requred o physcally confgure or handle he keys. 2.5 Plaform Envronmenal Conrol Inerface (PECI) PECI s an Inel propreary nerface ha provdes a communcaon channel beween Inel processors and exernal componens, lke Super I/O (SIO) and Embedded Conrollers (EC), o provde processor emperaure, Turbo, Confgurable TDP, and memory hrolng conrol mechansms and many oher servces. PECI s used for plaform hermal managemen and real me conrol and confguraon of processor feaures and performance PECI us Archecure The PECI archecure s based on a wred-or bus ha he clens (as processor PECI) can pull up hgh (wh srong drve). The dle sae on he bus s near zero. The followng fgure demonsraes PECI desgn and connecvy. Whle he hos/ orgnaor can be a hrd pary PECI hos, one of he PECI clens s a processor PECI devce. July 2014 Daashee Volume 1 of 2 Order No.:

30 Processors Inerfaces Fgure 6. PECI Hos-Clens Connecon Example V TT V TT Q1 nx PECI Q3 nx Q2 1X C PECI <10pF/Node Hos / Orgnaor PECI Clen Addonal PECI Clens Daashee Volume 1 of 2 July Order No.:

31 Technologes Processors 3.0 Technologes Ths chaper provdes a hgh-level descrpon of Inel echnologes mplemened n he processor. The mplemenaon of he feaures may vary beween he processor SKUs. Deals on he dfferen echnologes of Inel processors and oher relevan exernal noes are locaed a he Inel echnology web se: hp:// 3.1 Inel Vrualzaon Technology (Inel VT) Inel Vrualzaon Technology (Inel VT) makes a sngle sysem appear as mulple ndependen sysems o sofware. Ths allows mulple, ndependen operang sysems o run smulaneously on a sngle sysem. Inel VT comprses echnology componens o suppor vrualzaon of plaforms based on Inel archecure mcroprocessors and chpses. Inel Vrualzaon Technology (Inel VT) for IA-32, Inel 64 and Inel Archecure (Inel VT-x) added hardware suppor n he processor o mprove he vrualzaon performance and robusness. Inel Vrualzaon Technology for Dreced I/O (Inel VT-d) exends Inel VT-x by addng hardware asssed suppor o mprove I/O devce vrualzaon performance. Inel VT-x specfcaons and funconal descrpons are ncluded n he Inel 64 and IA-32 Archecures Sofware Developer s Manual, Volume 3 and s avalable a: hp:// The Inel VT-d specfcaon and oher Inel VT documens can be referenced a: hp:// hps://sharedspaces.nel.com/ses/pcdc/sepages/ingredens/ngreden.aspx? ng=vt Inel VT-x Objecves Inel VT-x provdes hardware acceleraon for vrualzaon of IA plaforms. Vrual Machne Monor (VMM) can use Inel VT-x feaures o provde an mproved relable vrualzed plaform. y usng Inel VT-x, a VMM s: Robus: VMMs no longer need o use paravrualzaon or bnary ranslaon. Ths means ha off-he-shelf operang sysems and applcaons can be run whou any specal seps. Enhanced: Inel VT enables VMMs o run 64-b gues operang sysems on IA x86 processors. July 2014 Daashee Volume 1 of 2 Order No.:

32 Processors Technologes More relable: Due o he hardware suppor, VMMs can now be smaller, less complex, and more effcen. Ths mproves relably and avalably and reduces he poenal for sofware conflcs. More secure: The use of hardware ransons n he VMM srenghens he solaon of VMs and furher prevens corrupon of one VM from affecng ohers on he same sysem. Inel VT-x Feaures The processor suppors he followng Inel VT-x feaures: Exended Page Table (EPT) Accessed and Dry s EPT A/D bs enabled VMMs o effcenly mplemen memory managemen and page classfcaon algorhms o opmze VM memory operaons, such as defragmenaon, pagng, lve mgraon, and check-ponng. Whou hardware suppor for EPT A/D bs, VMMs may need o emulae A/D bs by markng EPT pagng-srucures as no-presen or read-only, and ncur he overhead of EPT page-faul VM exs and assocaed sofware processng. Exended Page Table Poner (EPTP) swchng EPTP swchng s a specfc VM funcon. EPTP swchng allows gues sofware (n VMX non-roo operaon, suppored by EPT) o reques a dfferen EPT pagng-srucure herarchy. Ths s a feaure by whch sofware n VMX nonroo operaon can reques a change of EPTP whou a VM ex. Sofware can choose among a se of poenal EPTP values deermned n advance by sofware n VMX roo operaon. Pause loop exng Suppor VMM schedulers seekng o deermne when a vrual processor of a mulprocessor vrual machne s no performng useful work. Ths suaon may occur when no all vrual processors of he vrual machne are currenly scheduled and when he vrual processor n queson s n a loop nvolvng he PAUSE nsrucon. The new feaure allows deecon of such loops and s hus called PAUSE-loop exng. The processor core suppors he followng Inel VT-x feaures: Exended Page Tables (EPT) EPT s hardware asssed page able vrualzaon. I elmnaes VM exs from he gues operang sysem o he VMM for shadow page-able manenance. Vrual Processor IDs (VPID) Ably o assgn a VM ID o ag processor core hardware srucures (such as TLs). Ths avods flushes on VM ransons o gve a lower-cos VM ranson me and an overall reducon n vrualzaon overhead. Gues Preempon Tmer Mechansm for a VMM o preemp he execuon of a gues operang sysem afer an amoun of me specfed by he VMM. The VMM ses a mer value before enerng a gues. The feaure ads VMM developers n flexbly and Qualy of Servce (QoS) guaranees. Daashee Volume 1 of 2 July Order No.:

33 Technologes Processors Descrpor-Table Exng Descrpor-able exng allows a VMM o proec a gues operang sysem from an nernal (malcous sofware based) aack by prevenng relocaon of key sysem daa srucures lke IDT (nerrup descrpor able), GDT (global descrpor able), LDT (local descrpor able), and TSS (ask segmen selecor). A VMM usng hs feaure can nercep (by a VM ex) aemps o relocae hese daa srucures and preven hem from beng ampered by malcous sofware. Inel VT-d Objecves The key Inel VT-d objecves are doman-based solaon and hardware-based vrualzaon. A doman can be absracly defned as an solaed envronmen n a plaform o whch a subse of hos physcal memory s allocaed. Inel VT-d provdes acceleraed I/O performance for a vrualzed plaform and provdes sofware wh he followng capables: I/O devce assgnmen and secury: for flexbly assgnng I/O devces o VMs and exendng he proecon and solaon properes of VMs for I/O operaons. DMA remappng: for supporng ndependen address ranslaons for Drec Memory Accesses (DMA) from devces. Inerrup remappng: for supporng solaon and roung of nerrups from devces and exernal nerrup conrollers o approprae VMs. Relably: for recordng and reporng o sysem sofware DMA and nerrup errors ha may oherwse corrup memory or mpac VM solaon. Inel VT-d accomplshes address ranslaon by assocang a ransacon from a gven I/O devce o a ranslaon able assocaed wh he Gues o whch he devce s assgned. I does hs by means of he daa srucure n he followng llusraon. Ths able creaes an assocaon beween he devce's PCI Express* us/devce/funcon (/D/F) number and he base address of a ranslaon able. Ths daa srucure s populaed by a VMM o map devces o ranslaon ables n accordance wh he devce assgnmen resrcons above, and o nclude a mul-level ranslaon able (VT-d Table) ha conans Gues specfc address ranslaons. July 2014 Daashee Volume 1 of 2 Order No.:

34 Processors Technologes Fgure 7. Devce o Doman Mappng Srucures (Dev 31, Func 7) Conex enry 255 (Dev 0, Func 1) (Dev 0, Func 0) Conex enry 0 (us 255) Roo enry 255 Conex enry Table For bus N Address Translaon Srucures for Doman A (us N) Roo enry N (us 0) Roo enry 0 Roo enry able Conex enry 255 Conex enry 0 Conex enry Table For bus 0 Address Translaon Srucures for Doman Inel VT-d funconaly, ofen referred o as an Inel VT-d Engne, has ypcally been mplemened a or near a PCI Express hos brdge componen of a compuer sysem. Ths mgh be n a chpse componen or n he PCI Express funconaly of a processor wh negraed I/O. When one such Inel VT-d engne receves a PCI Express ransacon from a PCI Express bus, uses he /D/F number assocaed wh he ransacon o search for an Inel VT-d ranslaon able. In dong so, uses he /D/F number o raverse he daa srucure shown n he above fgure. If fnds a vald Inel VT-d able n hs daa srucure, uses ha able o ranslae he address provded on he PCI Express bus. If does no fnd a vald ranslaon able for a gven ranslaon, hs resuls n an Inel VT-d faul. If Inel VT-d ranslaon s requred, he Inel VT-d engne performs an N-level able walk. For more nformaon, refer o Inel Vrualzaon Technology for Dreced I/O Archecure Specfcaon hp://download.nel.com/echnology/compung/vpech/ Inel(r)_VT_for_Drec_IO.pdf Inel VT-d Feaures The processor suppors he followng Inel VT-d feaures: Daashee Volume 1 of 2 July Order No.:

35 Technologes Processors Memory conroller and processor graphcs comply wh he Inel VT-d 1.2 Specfcaon Two Inel VT-d DMA remap engnes GFX DMA remap engne Defaul DMA remap engne (covers all devces excep GFX) Suppor for roo enry, conex enry, and defaul conex 39-b gues physcal address and hos physcal address wdhs Suppor for 4 K page szes Suppor for regser-based faul recordng only (for sngle enry only) and suppor for MSI nerrups for fauls Suppor for boh leaf and non-leaf cachng Suppor for boo proecon of defaul page able Suppor for non-cachng of nvald page able enres Suppor for hardware-based flushng of ranslaed bu pendng wres and pendng reads, on IOTL nvaldaon Suppor for Global, Doman specfc, and Page specfc IOTL nvaldaon MSI cycles (MemWr o address FEEx_xxxxh) no ranslaed Translaon fauls resul n cycle forwardng o VIOS regon (bye enables masked for wres). Reurned daa may be bogus for nernal agens; PEG/DMI nerfaces reurn unsuppored reques saus Inerrup remappng s suppored Queued nvaldaon s suppored Inel VT-d ranslaon bypass address range s suppored (Pass Through) The processor suppors he followng added new Inel VT-d feaures: 4-level Inel VT-d Page walk: oh defaul Inel VT-d engne, as well as he IGD Inel VT-d engne, are upgraded o suppor 4-level Inel VT-d ables (adjused gues address wdh 48 bs) Inel VT-d superpage: suppor of Inel VT-d superpage (2 M, 1 G) for he defaul Inel VT-d engne (ha covers all devces excep IGD) IGD Inel VT-d engne does no suppor superpage and IOS should dsable superpage n defaul Inel VT-d engne when GFX s enabled. Noe: 3.2 Inel VT-d Technology may no be avalable on all SKUs. Inel Trused Execuon Technology (Inel TXT) Inel Trused Execuon Technology (Inel TXT) defnes plaform-level enhancemens ha provde he buldng blocks for creang rused plaforms. The Inel TXT plaform helps o provde he auhency of he conrollng envronmen such ha hose wshng o rely on he plaform can make an approprae rus decson. The Inel TXT plaform deermnes he deny of he conrollng envronmen by accuraely measurng and verfyng he conrollng sofware. July 2014 Daashee Volume 1 of 2 Order No.:

36 Processors Technologes Anoher aspec of he rus decson s he ably of he plaform o ress aemps o change he conrollng envronmen. The Inel TXT plaform wll ress aemps by sofware processes o change he conrollng envronmen or bypass he bounds se by he conrollng envronmen. Inel TXT s a se of exensons desgned o provde a measured and conrolled launch of sysem sofware ha wll hen esablsh a proeced envronmen for self and any addonal sofware ha may execue. These exensons enhance wo areas: The launchng of he Measured Launched Envronmen (MLE). The proecon of he MLE from poenal corrupon. The enhanced plaform provdes hese launch and conrol nerfaces usng Safer Mode Exensons (SMX). The SMX nerface ncludes he followng funcons: Measured/Verfed launch of he MLE. Mechansms o ensure he above measuremen s proeced and sored n a secure locaon. Proecon mechansms ha allow he MLE o conrol aemps o modfy self. The processor also offers addonal enhancemens o Sysem Managemen Mode (SMM) archecure for enhanced secury and performance. The processor provdes new MSRs o: Enable a second SMM range Enable SMM code execuon range checkng Selec wheher SMM Save Sae s o be wren o legacy SMRAM or o MSRs Deermne f a hread s gong o be delayed enerng SMM Deermne f a hread s blocked from enerng SMM Targeed SMI, enable/dsable hreads from respondng o SMIs boh VLWs and IPI For he above feaures, IOS mus es he assocaed capably b before aempng o access any of he above regsers. For more nformaon, refer o he Inel Trused Execuon Technology Measured Launched Envronmen Programmng Gude. 3.3 Inel Hyper-Threadng Technology (Inel HT Technology) The processor suppors Inel Hyper-Threadng Technology (Inel HT Technology) ha allows an execuon core o funcon as wo logcal processors. Whle some execuon resources, such as caches, execuon uns, and buses are shared, each logcal processor has s own archecural sae wh s own se of general-purpose regsers and conrol regsers. Ths feaure mus be enabled usng he IOS and requres operang sysem suppor. Daashee Volume 1 of 2 July Order No.:

37 Technologes Processors Inel recommends enablng Inel HT Technology wh Mcrosof Wndows* 8 and Mcrosof Wndows* 7 and dsablng Inel HT Technology usng he IOS for all prevous versons of Wndows* operang sysems. For more nformaon on Inel HT Technology, see hp:// 3.4 Inel Turbo oos Technology 2.0 The Inel Turbo oos Technology 2.0 allows he processor core o opporunscally and auomacally run faser han s raed operang frequency/render clock, f s operang below power, emperaure, and curren lms. The Inel Turbo oos Technology 2.0 feaure s desgned o ncrease performance of boh mul-hreaded and sngle-hreaded workloads. Compared wh prevous generaon producs, Inel Turbo oos Technology 2.0 wll ncrease he rao of applcaon power o TDP. Thus, hermal soluons and plaform coolng ha are desgned o less han hermal desgn gudance mgh experence hermal and performance ssues snce more applcaons wll end o run a he maxmum power lm for sgnfcan perods of me. Noe: Inel Turbo oos Technology 2.0 may no be avalable on all SKUs. Inel Turbo oos Technology 2.0 Frequency To deermne he hghes performance frequency amongs acve cores, he processor akes he followng no consderaon: The number of cores operang n he C0 sae. The esmaed core curren consumpon. The esmaed package pror and presen power consumpon. The package emperaure. Any of hese facors can affec he maxmum frequency for a gven workload. If he power, curren, or hermal lm s reached, he processor wll auomacally reduce he frequency o say whn s TDP lm. Turbo processor frequences are only acve f he operang sysem s requesng he P0 sae. For more nformaon on P-saes and C-saes, see Power Managemen on page Inel Advanced Vecor Exensons 2.0 (Inel AVX2) Inel Advanced Vecor Exensons 2.0 (Inel AVX2) s he laes expanson of he Inel nsrucon se. Inel AVX2 exends he Inel Advanced Vecor Exensons (Inel AVX) wh 256-b neger nsrucons, floang-pon fused mulply add (FMA) nsrucons, and gaher operaons. The 256-b neger vecors benef mah, codec, mage, and dgal sgnal processng sofware. FMA mproves performance n face deecon, professonal magng, and hgh performance compung. Gaher operaons ncrease vecorzaon opporunes for many applcaons. In addon o he vecor exensons, hs generaon of Inel processors adds new b manpulaon nsrucons useful n compresson, encrypon, and general purpose sofware. For more nformaon on Inel AVX, see hp:// July 2014 Daashee Volume 1 of 2 Order No.:

38 Processors Technologes 3.6 Inel Advanced Encrypon Sandard New Insrucons (Inel AES-NI) The processor suppors Inel Advanced Encrypon Sandard New Insrucons (Inel AES-NI) ha are a se of Sngle Insrucon Mulple Daa (SIMD) nsrucons ha enable fas and secure daa encrypon and decrypon based on he Advanced Encrypon Sandard (AES). Inel AES-NI are valuable for a wde range of crypographc applcaons, such as applcaons ha perform bulk encrypon/ decrypon, auhencaon, random number generaon, and auhencaed encrypon. AES s broadly acceped as he sandard for boh governmen and ndusry applcaons, and s wdely deployed n varous proocols. Inel AES-NI consss of sx Inel SSE nsrucons. Four nsrucons, AESENC, AESENCLAST, AESDEC, and AESDELAST faclae hgh performance AES encrypon and decrypon. The oher wo, AESIMC and AESKEYGENASSIST, suppor he AES key expanson procedure. Togeher, hese nsrucons provde a full hardware for supporng AES; offerng secury, hgh performance, and a grea deal of flexbly. PCLMULQDQ Insrucon The processor suppors he carry-less mulplcaon nsrucon, PCLMULQDQ. PCLMULQDQ s a Sngle Insrucon Mulple Daa (SIMD) nsrucon ha compues he 128-b carry-less mulplcaon of wo, 64-b operands whou generang and propagang carres. Carry-less mulplcaon s an essenal processng componen of several crypographc sysems and sandards. Hence, accelerang carry-less mulplcaon can sgnfcanly conrbue o achevng hgh speed secure compung and communcaon. Inel Secure Key The processor suppors Inel Secure Key (formerly known as Dgal Random Number Generaor (DRNG)), a sofware vsble random number generaon mechansm suppored by a hgh qualy enropy source. Ths capably s avalable o programmers hrough he RDRAND nsrucon. The resulan random number generaon capably s desgned o comply wh exsng ndusry sandards n hs regard (ANSI X9.82 and NIST SP ). Some possble usages of he RDRAND nsrucon nclude crypographc key generaon as used n a varey of applcaons, ncludng communcaon, dgal sgnaures, secure sorage, and so on. 3.7 Inel 64 Archecure x2apic The x2apic archecure exends he xapic archecure ha provdes key mechansms for nerrup delvery. Ths exenson s prmarly nended o ncrease processor addressably. Specfcally, x2apic: Reans all key elemens of compably o he xapic archecure: Delvery modes Inerrup and processor prores Inerrup sources Inerrup desnaon ypes Daashee Volume 1 of 2 July Order No.:

39 Technologes Processors Provdes exensons o scale processor addressably for boh he logcal and physcal desnaon modes Adds new feaures o enhance performance of nerrup delvery Reduces complexy of logcal desnaon mode nerrup delvery on lnk based archecures The key enhancemens provded by he x2apic archecure over xapic are he followng: Suppor for wo modes of operaon o provde backward compably and exensbly for fuure plaform nnovaons: In xapic compably mode, APIC regsers are accessed hrough memory mapped nerface o a 4K-ye page, dencal o he xapic archecure. In x2apic mode, APIC regsers are accessed hrough Model Specfc Regser (MSR) nerfaces. In hs mode, he x2apic archecure provdes sgnfcanly ncreased processor addressably and some enhancemens on nerrup delvery. Increased range of processor addressably n x2apic mode: Physcal xapic ID feld ncreases from 8 bs o 32 bs, allowng for nerrup processor addressably up o 4G 1 processors n physcal desnaon mode. A processor mplemenaon of x2apic archecure can suppor fewer han 32- bs n a sofware ransparen fashon. Logcal xapic ID feld ncreases from 8 bs o 32 bs. The 32-b logcal x2apic ID s paroned no wo sub-felds a 16-b cluser ID and a 16-b logcal ID whn he cluser. Consequenly, ((2^20) 16) processors can be addressed n logcal desnaon mode. Processor mplemenaons can suppor fewer han 16 bs n he cluser ID sub-feld and logcal ID sub-feld n a sofware agnosc fashon. More effcen MSR nerface o access APIC regsers: To enhance ner-processor and self-dreced nerrup delvery as well as he ably o vrualze he local APIC, he APIC regser se can be accessed only hrough MSR-based nerfaces n x2apic mode. The Memory Mapped IO (MMIO) nerface used by xapic s no suppored n x2apic mode. The semancs for accessng APIC regsers have been revsed o smplfy he programmng of frequenly-used APIC regsers by sysem sofware. Specfcally, he sofware semancs for usng he Inerrup Command Regser (ICR) and End Of Inerrup (EOI) regsers have been modfed o allow for more effcen delvery and dspachng of nerrups. The x2apic exensons are made avalable o sysem sofware by enablng he local x2apic un n he x2apic mode. To benef from x2apic capables, a new operang sysem and a new IOS are boh needed, wh specal suppor for x2apic mode. The x2apic archecure provdes backward compably o he xapic archecure and forward exendble for fuure Inel plaform nnovaons. Noe: Inel x2apic Technology may no be avalable on all SKUs. For more nformaon, see he Inel 64 Archecure x2apic Specfcaon a hp:// July 2014 Daashee Volume 1 of 2 Order No.:

40 Processors Technologes 3.8 Power Aware Inerrup Roung (PAIR) The processor ncludes enhanced power-performance echnology ha roues nerrups o hreads or cores based on her sleep saes. As an example, for energy savngs, roues he nerrup o he acve cores whou wakng he deep dle cores. For performance, roues he nerrup o he dle (C1) cores whou nerrupng he already heavly loaded cores. Ths enhancemen s mosly benefcal for hgh-nerrup scenaros lke Ggab LAN, WLAN perpherals, and so on. 3.9 Execue Dsable The Execue Dsable allows memory o be marked as execuable when combned wh a supporng operang sysem. If code aemps o run n non-execuable memory, he processor rases an error o he operang sysem. Ths feaure can preven some classes of vruses or worms ha explo buffer overrun vulnerables and can hus help mprove he overall secury of he sysem. See he Inel 64 and IA-32 Archecures Sofware Developer's Manuals for more dealed nformaon Inel oo Guard Inel oo Guard can help proec he plaform boo negry by prevenng execuon of unauhorzed boo blocks. Wh Inel oo Guard, plaform manufacurers can creae boo polces such ha nvocaon of an unauhorzed (or unrused) boo block wll rgger he plaform proecon per he manufacurer's defned polcy. Wh verfcaon based n he hardware, Inel oo Guard exends he rus boundary of he plaform boo process down o he hardware level. Inel oo Guard accomplshes hs by: Provdng hardware-based Sac Roo of Trus for Measuremen (S-RTM) and he Roo of Trus for Verfcaon (RTV) usng Inel archecural componens. Provdng archecural defnon for plaform manufacurer oo Polcy. Enforcng manufacure provded oo Polcy usng Inel archecural componens. enefs of hs proecon s ha Inel oo Guard can help manan plaform negry by prevenng re-purposng of he manufacurer s hardware o run an unauhorzed sofware sack. Noe: 3.11 Inel oo Guard echnology avalably may vary beween he dfferen SKUs. Supervsor Mode Execuon Proecon (SMEP) Supervsor Mode Execuon Proecon provdes he nex level of sysem proecon by blockng malcous sofware aacks from user mode code when he sysem s runnng n he hghes prvlege level. Ths echnology helps o proec from vrus aacks and unwaned code from harmng he sysem. For more nformaon, refer o Inel 64 and IA-32 Archecures Sofware Developer's Manual, Volume 3A a: hp:// Daashee Volume 1 of 2 July Order No.:

41 Technologes Processors 3.12 Inel Transaconal Synchronzaon Exensons - New Insrucons (Inel TSX-NI) New on he processor are he Inel Transaconal Synchronzaon Exensons - New Insrucons (Inel TSX-NI). Inel TSX-NI provdes a se of nsrucon exensons ha allow programmers o specfy regons of code for ransaconal synchronzaon. Programmers can use hese exensons o acheve he performance of fne-gran lockng whle acually programmng usng coarse-gran locks. Deals on Inel TSX-NI are n he Inel Archecure Insrucon Se Exensons Programmng Reference. July 2014 Daashee Volume 1 of 2 Order No.:

42 Processors Power Managemen 4.0 Power Managemen Ths chaper provdes nformaon on he followng power managemen opcs: Advanced Confguraon and Power Inerface (ACPI) Saes Processor Core Inegraed Memory Conroller (IMC) Processor Graphcs Conroller Fgure 8. Processor Power Saes G0 Workng S0 Processor powered on (full on mode / conneced sandby mode) C0 Acve mode P0 Pn C1 Auo hal C1E Auo hal, low freq, low volage C3 L1/L2 caches flush, clocks off C6 save core saes before shudown and PLL off C7 C6 + L3 cache flush C8 C7 nernal volage removal from all power domans C9 C8+ npu o 0V C10 C9+VR12.6 shu off or PS4 G1 Sleepng S3 cold Sleep Suspend To Ram (STR) S4 Hbernae Suspend To Dsk (STD), Wakeup on PCH G2 Sof Off S5 Sof Off no power,wakeup on PCH G3 Mechancal Off * Noe: Power saes avalably may vary beween he dfferen SKUs Daashee Volume 1 of 2 July Order No.:

43 { PACKAGE STATE Power Managemen Processors Fgure 9. Processor Package and Core C-Saes CORE STATE C0 C1 C1E C3 C6 C7 C8 C9 C10 C0 C3 C6 C7 C8 C9 C10 One or more cores or GT execung nsrucons All cores and GT n C3 or deeper, L3 may be flushed and urned off, memory n self refresh, some Uncore clocks sopped, some Uncore volages reduced All cores and GT n C6 or deeper, L3 may be flushed and urned off, memory n self refresh, all Uncore clocks sopped, some Uncore volages reduced Package C6 + L3 flushed and urned off, addonal Uncore volages reduced Package C7 + mos Uncore volages reduced o 0V Package C8 + VR12.6 n low power sae Package C9 + VR12.6 urned off Core behaves he same as Core C6 sae All core clocks are sopped, core sae saved and volage reduce o 0V Cores flush L1/L2 no L3, all core clocks are sopped Core haled, mos core clocks sopped and volage reduced o Pn Core haled, mos core clocks sopped Core s execung code Possble combnaon of core/package saes Impossble combnaon of core/package saes Noe: The core sae relaes o he core whch s n he HIGHEST power sae n he package (mos acve) 4.1 Advanced Confguraon and Power Inerface (ACPI) Saes Suppored Ths secon descrbes he ACPI saes suppored by he processor. Table 13. Sysem Saes Sae Descrpon G0/S0 G0/S0 G1/S3-Cold G1/S4 G2/S5 G3 Full On Mode, Dsplay On. Conneced Sandby Mode, Dsplay Off. Suspend-o-RAM (STR). Conex saved o memory (S3-Ho sae s no suppored by he processor). Suspend-o-Dsk (STD). All power los (excep wakeup on PCH). Sof off. All power los (excep wakeup on PCH). Toal reboo. Mechancal off. All power removed from sysem. Table 14. Processor Core / Package Sae Suppor Sae C0 C1 C1E C3 C6 Acve mode, processor execung code. AuoHALT sae. Descrpon AuoHALT sae wh lowes frequency and volage operang pon. Execuon cores n C3 sae flush her L1 nsrucon cache, L1 daa cache, and L2 cache o he L3 shared cache. Clocks are shu off o each core. Execuon cores n hs sae save her archecural sae before removng core volage. July 2014 Daashee Volume 1 of 2 Order No.:

44 Processors Power Managemen Sae C7 C8 Descrpon Execuon cores n hs sae behave smlarly o he C6 sae. If all execuon cores reques C7 sae, L3 cache ways are flushed unl s cleared. If he enre L3 cache s flushed, volage wll be removed from he L3 cache. Power removal o SA, Cores and L3 wll reduce power consumpon. C7 sae plus volage s removed from all power domans afer requred sae s saved. PLL s powered down. C9 C8 sae plus processor V CC npu volage a 0 V. C10 C9 sae plus VR12.6 s se o low-power sae, near shu off. Table 15. Inegraed Memory Conroller Saes Sae Descrpon Power up Pre-charge Power-down Acve Powerdown Self-Refresh CKE assered. Acve mode. CKE de-assered (no self-refresh) wh all banks closed. CKE de-assered (no self-refresh) wh mnmum one bank acve. CKE de-assered usng devce self-refresh. Table 16. G, S, and C Inerface Sae Combnaons Global (G) Sae Sleep (S) Sae Processor Package (C) Sae Processor Sae Sysem Clocks Descrpon G0 S0 C0 Full On On Full On G0 S0 C1/C1E Auo-Hal On Auo-Hal G0 S0 C3 Deep Sleep On Deep Sleep G0 S0 C6/C7 Deep Powerdown On Deep Power-down G0 S0 C8/C9/C10 On Deeper Powerdown G1 S3 Power off Off, excep RTC Suspend o RAM G1 S4 Power off Off, excep RTC Suspend o Dsk G2 S5 Power off Off, excep RTC Sof Off G3 NA Power off Power off Hard off 4.2 Processor Core Power Managemen Whle execung code, Enhanced Inel SpeedSep Technology opmzes he processor s frequency and core volage based on workload. Each frequency and volage operang pon s defned by ACPI as a P-sae. When he processor s no execung code, s dle. A low-power dle sae s defned by ACPI as a C-sae. In general, deeper power C-saes have longer enry and ex laences Enhanced Inel SpeedSep Technology Key Feaures The followng are he key feaures of Enhanced Inel SpeedSep Technology: Daashee Volume 1 of 2 July Order No.:

45 Power Managemen Processors Mulple frequency and volage pons for opmal performance and power effcency. These operang pons are known as P-saes. Frequency selecon s sofware conrolled by wrng o processor MSRs. The volage s opmzed based on he seleced frequency and he number of acve processor cores. Once he volage s esablshed, he PLL locks on o he arge frequency. All acve processor cores share he same frequency and volage. In a mulcore processor, he hghes frequency P-sae requesed among all acve cores s seleced. Sofware-requesed ransons are acceped a any me. If a prevous ranson s n progress, he new ranson s deferred unl he prevous ranson s compleed. The processor conrols volage ramp raes nernally o ensure glch-free ransons. ecause here s low ranson laency beween P-saes, a sgnfcan number of ransons per-second are possble Low-Power Idle Saes When he processor s dle, low-power dle saes (C-saes) are used o save power. More power savngs acons are aken for numercally hgher C-saes. However, hgher C-saes have longer ex and enry laences. Resoluon of C-saes occur a he hread, processor core, and processor package level. Thread-level C-saes are avalable f Inel Hyper-Threadng Technology s enabled. Cauon: Fgure 10. Long erm relably canno be assured unless all he Low-Power Idle Saes are enabled. Idle Power Managemen reakdown of he Processor Cores Thread 0 Thread 1 Thread 0 Thread 1 Core 0 Sae Core N Sae Processor Package Sae July 2014 Daashee Volume 1 of 2 Order No.:

46 Processors Power Managemen Whle ndvdual hreads can reques low-power C-saes, power savng acons only ake place once he core C-sae s resolved. Core C-saes are auomacally resolved by he processor. For hread and core C-saes, a ranson o and from C0 s requred before enerng any oher C-sae Requesng Low-Power Idle Saes The prmary sofware nerfaces for requesng low-power dle saes are hrough he MWAIT nsrucon wh sub-sae hns and he HLT nsrucon (for C1 and C1E). However, sofware may make C-sae requess usng he legacy mehod of I/O reads from he ACPI-defned processor clock conrol regsers, referred o as P_LVLx. Ths mehod of requesng C-saes provdes legacy suppor for operang sysems ha nae C-sae ransons usng I/O reads. For legacy operang sysems, P_LVLx I/O reads are convered whn he processor o he equvalen MWAIT C-sae reques. Therefore, P_LVLx reads do no drecly resul n I/O reads o he sysem. The feaure, known as I/O MWAIT redrecon, mus be enabled n he IOS. The IOS can wre o he C-sae range feld of he PMG_IO_CAPTURE MSR o resrc he range of I/O addresses ha are rapped and emulae MWAIT lke funconaly. Any P_LVLx reads ousde of hs range do no cause an I/O redrecon o MWAIT(Cx) lke reques. The reads fall hrough lke a normal I/O nsrucon. Noe: When P_LVLx I/O nsrucons are used, MWAIT sub-saes canno be defned. The MWAIT sub-sae s always zero f I/O MWAIT redrecon s used. y defaul, P_LVLx I/O redrecons enable he MWAIT 'break on EFLAGS.IF feaure ha rggers a wakeup on an nerrup, even f nerrups are masked by EFLAGS.IF. Core C-Sae Rules The followng are general rules for all core C-saes, unless specfed oherwse: A core C-sae s deermned by he lowes numercal hread sae (such as Thread 0 requess C1E sae whle Thread 1 requess C3 sae, resulng n a core C1E sae). See he G, S, and C Inerface Sae Combnaons able. A core ransons o C0 sae when: An nerrup occurs There s an access o he monored address f he sae was enered usng an MWAIT/Tmed MWAIT nsrucon The deadlne correspondng o he Tmed MWAIT nsrucon expres An nerrup dreced oward a sngle hread wakes only ha hread. If any hread n a core s n acve (n C0 sae), he core's C-sae wll resolve o C0 sae. Any nerrup comng no he processor package may wake any core. A sysem rese re-nalzes all processor cores. Core C0 Sae The normal operang sae of a core where code s beng execued. Daashee Volume 1 of 2 July Order No.:

47 Power Managemen Processors Core C1/C1E Sae C1/C1E s a low power sae enered when all hreads whn a core execue a HLT or MWAIT(C1/C1E) nsrucon. A Sysem Managemen Inerrup (SMI) handler reurns execuon o eher Normal sae or he C1/C1E sae. See he Inel 64 and IA-32 Archecures Sofware Developer s Manual for more nformaon. Whle a core s n C1/C1E sae, processes bus snoops and snoops from oher hreads. For more nformaon on C1E sae, see Package C-Saes on page 48. Core C3 Sae Indvdual hreads of a core can ener he C3 sae by nang a P_LVL2 I/O read o he P_LK or an MWAIT(C3) nsrucon. A core n C3 sae flushes he conens of s L1 nsrucon cache, L1 daa cache, and L2 cache o he shared L3 cache, whle mananng s archecural sae. All core clocks are sopped a hs pon. ecause he core s caches are flushed, he processor does no wake any core ha s n he C3 sae when eher a snoop s deeced or when anoher core accesses cacheable memory. Core C6 Sae Indvdual hreads of a core can ener he C6 sae by nang a P_LVL3 I/O read or an MWAIT(C6) nsrucon. efore enerng core C6 sae, he core wll save s archecural sae o a dedcaed SRAM. Once complee, a core wll have s volage reduced o zero vols. Durng ex, he core s powered on and s archecural sae s resored. Core C7-C10 Saes Indvdual hreads of a core can ener he C7, C8, C9, or C10 sae by nang a P_LVL4, P_LVL5, P_LVL6, P_LVL7 I/O read (respecvely) o he P_LK or by an MWAIT(C7/C8/C9/C10) nsrucon. The core C7 C10 sae exhbs he same behavor as he core C6 sae. C-Sae Auo-Demoon In general, deeper C-saes, such as C6 or C7 sae, have long laences and have hgher energy enry/ex coss. The resulng performance and energy penales become sgnfcan when he enry/ex frequency of a deeper C-sae s hgh. Therefore, ncorrec or neffcen usage of deeper C-saes have a negave mpac on baery lfe and dle power. To ncrease resdency and mprove baery lfe and dle power n deeper C-saes, he processor suppors C-sae auo-demoon. There are wo C-sae auo-demoon opons: C7/C6 o C3 sae C7/C6/C3 To C1 sae The decson o demoe a core from C6/C7 o C3 or C3/C6/C7 o C1 sae s based on each core s mmedae resdency hsory and nerrup rae. If he nerrup rae experenced on a core s hgh and he resdence n a deep C-sae beween such nerrups s low, he core can be demoed o a C3 or C1 sae. A hgher nerrup paern s requred o demoe a core o C1 sae as compared o C3 sae. July 2014 Daashee Volume 1 of 2 Order No.:

48 Processors Power Managemen Ths feaure s dsabled by defaul. IOS mus enable n he PMG_CST_CONFIG_CONTROL regser. The auo-demoon polcy s also confgured by hs regser Package C-Saes The processor suppors C0, C1/C1E, C3, C6, C7, C8, C9, and C10 power saes.the followng s a summary of he general rules for package C-sae enry. These apply o all package C-saes, unless specfed oherwse: A package C-sae reques s deermned by he lowes numercal core C-sae amongs all cores. A package C-sae s auomacally resolved by he processor dependng on he core dle power saes and he saus of he plaform componens. Each core can be a a lower dle power sae han he package f he plaform does no gran he processor permsson o ener a requesed package C-sae. The plaform may allow addonal power savngs o be realzed n he processor. For package C-saes, he processor s no requred o ener C0 sae before enerng any oher C-sae. Enry no a package C-sae may be subjec o auo-demoon ha s, he processor may keep he package n a deeper package C-sae han requesed by he operang sysem f he processor deermnes, usng heurscs, ha he deeper C-sae resuls n beer power/performance. The processor exs a package C-sae when a break even s deeced. Dependng on he ype of break even, he processor does he followng: If a core break even s receved, he arge core s acvaed and he break even message s forwarded o he arge core. If he break even s no masked, he arge core eners he core C0 sae and he processor eners package C0 sae. If he break even s masked, he processor aemps o re-ener s prevous package sae. If he break even was due o a memory access or snoop reques, u he plaform dd no reques o keep he processor n a hgher package C- sae, he package reurns o s prevous C-sae. And he plaform requess a hgher power C-sae, he memory access or snoop reques s servced and he package remans n he hgher power C- sae. The followng able shows package C-sae resoluon for a dual-core processor. The followng fgure summarzes package C-sae ransons. Daashee Volume 1 of 2 July Order No.:

49 Power Managemen Processors Table 17. Coordnaon of Core Power Saes a he Package Level Package C-Sae Core 1 C0 C1 C3 C6 C7 C8 C9 C10 C0 C0 C0 C0 C0 C0 C0 C0 C0 C1 C0 C1 1 C1 1 C1 1 C1 1 C1 1 C1 1 C1 1 C3 C0 C1 1 C3 C3 C3 C3 C3 C3 Core 0 C6 C0 C1 1 C3 C6 C6 C6 C6 C6 C7 C0 C1 1 C3 C6 C7 C7 C7 C7 C8 C0 C1 1 C3 C6 C7 C8 C8 C8 C9 C0 C1 1 C3 C6 C7 C8 C9 C9 C10 C0 C1 1 C3 C6 C7 C8 C9 C10 Noe: 1. If enabled, he package C-sae wll be C1E f all cores have resolved a core C1 sae or hgher. Fgure 11. Package C-Sae Enry and Ex Package C0 Package C1/C1E Package C3 Package C6 Package C7 Package C8 Package C9 Package C10 Package C0 Sae Ths s he normal operang sae for he processor. The processor remans n he normal sae when a leas one of s cores s n he C0 or C1 sae or when he plaform has no graned permsson o he processor o go no a low-power sae. Indvdual cores may be n lower power dle saes whle he package s n C0 sae. Package C1/C1E Sae No addonal power reducon acons are aken n he package C1 sae. However, f he C1E sub-sae s enabled, he processor auomacally ransons o he lowes suppored core clock frequency, followed by a reducon n volage. The package eners he C1 low-power sae when: A leas one core s n he C1 sae. The oher cores are n a C1 or deeper power sae. The package eners he C1E sae when: All cores have drecly requesed C1E usng MWAIT(C1) wh a C1E sub-sae hn. July 2014 Daashee Volume 1 of 2 Order No.:

50 Processors Power Managemen All cores are n a power sae deeper han C1/C1E sae; however, he package low-power sae s lmed o C1/C1E usng he PMG_CST_CONFIG_CONTROL MSR. All cores have requesed C1 sae usng HLT or MWAIT(C1) and C1E auopromoon s enabled n IA32_MISC_ENALES. No nofcaon o he sysem occurs upon enry o C1/C1E sae. Package C2 Sae Package C2 sae s an nernal processor sae ha canno be explcly requesed by sofware. A processor eners Package C2 sae when: All cores and graphcs have requesed a C3 or deeper power sae; however, consrans (LTR, programmed mer evens n he near fuure, and so on) preven enry o any sae deeper han C 2 sae. Or, All cores and graphcs are n he C3 or deeper power saes, and a memory access reques s receved. Upon compleon of all ousandng memory requess, he processor ransons back no a deeper package C-sae. Package C3 Sae A processor eners he package C3 low-power sae when: A leas one core s n he C3 sae. The oher cores are n a C3 sae or deeper power sae and he processor has been graned permsson by he plaform. The plaform has no graned a reques o a package C6/C7 or deeper sae, however, has allowed a package C6 sae. In package C3 sae, he L3 shared cache s vald. Package C6 Sae A processor eners he package C6 low-power sae when: A leas one core s n he C6 sae. The oher cores are n a C6 or deeper power sae and he processor has been graned permsson by he plaform. The plaform has no graned a package C7 sae or deeper reques; however, has allowed a package C6 sae. If he cores are requesng C7 sae, bu he plaform s lmng o a package C6 sae, he las level cache n hs case can be flushed. In package C6 sae all cores have saved her archecural sae and have had her core volages reduced o zero vols. I s possble he L3 shared cache s flushed and urned off n package C6 sae. If a leas one core s requesng C6 sae, he L3 cache wll no be flushed. Package C7 Sae The processor eners he package C7 low-power sae when all cores are n he C7 sae. In package C7, he processor wll ake acon o remove power from porons of he sysem agen. Core break evens are handled he same way as n package C3 or C6 sae. Daashee Volume 1 of 2 July Order No.:

51 Power Managemen Processors Package C8 Sae The processor eners C8 saes when he core wh he hghes sae s C8. The package C8 sae s smlar o package C7 sae; however, n addon, all nernally generaed volage rals are urned off and he npu V CC s reduced o 1.15 V o 1.3 V. Package C9 Sae The processor eners package C9 saes when he core wh he hghes sae s C9. The package C9 sae s smlar o package C8 sae; n addon, he npu V CC s changed o 0 V. Package C10 Sae The processor eners C10 saes when he core wh he hghes sae s C10. The package C10 sae s smlar o he package C9 sae; n addon, he VR12.6 s n PS4 low-power sae, whch s near o shu off of he VR12.6. Dynamc L3 Cache Szng When all cores reques C7 or deeper C-sae, nernal heurscs s dynamcally flushes he L3 cache. Once he cores ener a deep C-sae, dependng on her MWAIT subsae reques, he L3 cache s eher gradually flushed N-ways a a me or flushed all a once. Upon he cores exng o C0, he L3 cache s gradually expanded based on nernal heurscs Package C-Saes and Dsplay Resoluons The negraed graphcs engne has he frame buffer locaed n sysem memory. When he dsplay s updaed, he graphcs engne feches dsplay daa from sysem memory. Dfferen screen resoluons and refresh raes have dfferen memory laency requremens. These requremens may lm he deepes Package C-sae he processor can ener. Oher elemens ha may affec he deepes Package C-sae avalable are he followng: Dsplay s on or off Sngle or mulple dsplays Nave or non-nave resoluon Panel Self Refresh (PSR) echnology Noe: Dsplay resoluon s no he only facor nfluencng he deepes Package C-sae he processor can ge no. Devce laences, nerrup response laences, and core C- saes are among oher facors ha nfluence he fnal package C-sae he processor can ener. The followng able lss dsplay resoluons and deepes avalable package C-Sae. The dsplay resoluons are examples usng common values for blankng and pxel rae. Acual resuls wll vary. The able shows he deepes possble Package C-sae. Sysem workload, sysem dle, and AC or DC power also affec he deepes possble Package C-sae. July 2014 Daashee Volume 1 of 2 Order No.:

52 Processors Power Managemen Table 18. Deepes Package C-Sae Avalable U-Processor Lne and Y-Processor Lne Panel Self Refresh (PSR) Number of Dsplays 1 Nave Resoluon 2 Deepes Avalable Package C-Sae Dsabled Sngle 800x Hz PC7 Dsabled Sngle 1024x Hz PC7 Dsabled Sngle 1280x Hz PC7 Dsabled Sngle 1920x Hz PC7 Dsabled Sngle 1920x Hz PC7 Dsabled Sngle 1920x Hz PC6 Dsabled Sngle 2048x Hz PC6 Dsabled Sngle 2560x Hz PC6 Dsabled Sngle 2560x Hz PC2 Dsabled Sngle 2880x Hz PC2 Dsabled Sngle 2880x Hz 3 PC2 Dsabled Sngle 3200x Hz 3 PC2 Dsabled Sngle 3200x Hz 3 PC2 Dsabled Sngle 3840x Hz PC2 Dsabled Sngle 4096x Hz PC2 Dsabled Mulple 800x Hz PC7 Dsabled Mulple 1024x Hz PC6 Dsabled Mulple 1280x Hz PC6 Dsabled Mulple 1920x Hz PC2 Dsabled Mulple 1920x Hz PC2 Dsabled Mulple 1920x Hz PC2 Dsabled Mulple 2048x Hz PC2 Dsabled Mulple 2560x Hz PC2 Dsabled Mulple 2560x Hz PC2 Dsabled Mulple 2880x Hz PC2 Dsabled Mulple 2880x Hz 3 PC2 Dsabled Mulple 3200x Hz 3 PC2 Dsabled Mulple 3200x Hz 3 PC2 Dsabled Mulple 3840x Hz PC2 Dsabled Mulple 4096x Hz PC2 Daashee Volume 1 of 2 July Order No.:

53 Power Managemen Processors Panel Self Refresh (PSR) Number of Dsplays 1 Nave Resoluon 2 Deepes Avalable Package C-Sae Enabled Sngle Any nave resoluon 4 PC7 Enabled Mulple Any nave resoluon 1 he gven resoluon wh Same as PSR dsabled for mulple dsplays Noes: 1. For mulple dsplay cases, he resoluon lsed s he hghes nave resoluon of all enabled dsplays, and PSR s nernally dsabled; ha s, dual dsplay wh one 800x Hz dsplay and one 2560x Hz dsplay wll resul n a deepes avalable package C-sae of PC2. 2. For non-nave resoluons, PSR s nernally dsabled, and he deepes avalable package C-Sae wll be beween ha of he PSR dsabled nave resoluon and he PSR dsabled non-nave resoluon.; ha s, a nave 3200x Hz panel usng non-nave 1920x Hz resoluon wll resul n a deepes avalable package C-Sae beween PC2 and PC7. 3. Resoluon no suppored by Y-Processor lne. 4. Mcrocode Updae rev or newer mus be used. 4.3 Inegraed Memory Conroller (IMC) Power Managemen The man memory s power managed durng normal operaon and n low-power ACPI Cx saes Dsablng Unused Sysem Memory Oupus Any sysem memory (SM) nerface sgnal ha goes o a memory n whch s no conneced o any acual memory devces s r-saed. The benefs of dsablng unused SM sgnals are: Reduced power consumpon. Reduced possble overshoo/undershoo sgnal qualy ssues seen by he processor I/O buffer recevers caused by reflecons from poenally unermnaed ransmsson lnes. When a gven rank s no populaed, he correspondng chp selec and CKE sgnals are no drven. A rese, all rows mus be assumed o be populaed, unl can be deermned ha he rows are no populaed. Ths s due o he fac ha when CKE s r-saed wh DRAMs presen, he DRAMs are no ensured o manan daa negry. CKE r-sae should be enabled by IOS where approprae, snce a rese all rows mus be assumed o be populaed. CKE rsae should be enabled by IOS where approprae, snce a rese all rows mus be assumed o be populaed DRAM Power Managemen and Inalzaon The processor mplemens exensve suppor for power managemen on he memory nerface.the processor drves four CKE pns, one per rank. The CKE s one of he power-save means. When CKE s off, he nernal DDR clock s dsabled and he DDR power s reduced. The power-savng dffers accordng o he seleced mode and he DDR ype used. For more nformaon, refer o he IDD able n he DDR specfcaon. July 2014 Daashee Volume 1 of 2 Order No.:

54 Processors Power Managemen The processor suppors four dfferen ypes of power-down modes n package C0. The dfferen power-down modes can be enabled hrough confgurng "PM_PDWN_confg_0_0_0_MCHAR". The ype of CKE power-down can be confgured hrough PDWN_mode (bs 15:12) and he dle mer can be confgured hrough PDWN_dle_couner (bs 11:0). The dfferen power-down modes suppored are: No power-down (CKE dsable) Acve power-down (APD): Ths mode s enered f here are open pages when de-asserng CKE. In hs mode he open pages are reaned. Power-savng n hs mode s he lowes. Power consumpon of DDR s defned by IDD3P. Exng hs mode s defned by XP small number of cycles. For hs mode, DRAM DLL mus be on. PPD/DLL-off: In hs mode he daa-n DLLs on DDR are off. Power-savng n hs mode s he bes among all power modes. Power consumpon s defned by IDD2P1. Exng hs mode s defned by XP, bu also XPDLL (10 20 accordng o DDR ype) cycles unl frs daa ransfer s allowed. For hs mode, DRAM DLL mus be off. Pre-charged power-down (PPD): Ths mode s enered f all banks n DDR are pre-charged when de-asserng CKE. Power savng n hs mode s nermedae beer han APD, bu less han DLL-off. Power consumpon s defned by IDD2P1. Exng hs mode s defned by XP. The dfference from APD mode s ha when wakng-up all page-buffers are empy.) The LPDDR does no have a DLL. As a resul, he power savngs are as good as PPD/DLL-off, bu wll have lower ex laency and hgher performance. The CKE s deermned per rank, whenever s nacve. Each rank has an dlecouner. The dle-couner sars counng as soon as he rank has no accesses, and f expres, he rank may ener power-down whle no new ransacons o he rank arrves o queues. The dle-couner begns counng a he las ncomng ransacon arrval. I s mporan o undersand ha snce he power-down decson s per rank, he IMC can fnd many opporunes o power down ranks, even whle runnng memory nensve applcaons; he savngs are sgnfcan (may be few Was, accordng o he DDR specfcaon). Ths s sgnfcan when each channel s populaed wh more ranks. Selecon of power modes should be accordng o power-performance or hermal rade-offs of a gven sysem: When ryng o acheve maxmum performance and power or hermal consderaon s no an ssue use no power-down In a sysem whch res o mnmze power-consumpon, ry usng he deepes power-down mode possble PPD/DLL-off wh a low dle mer value In hgh-performance sysems wh dense packagng (ha s, rcky hermal desgn) he power-down mode should be consdered n order o reduce he heang and avod DDR hrolng caused by he heang. The defaul value ha IOS confgures n "PM_PDWN_confg_0_0_0_MCHAR" s 6080h ha s, PPD/DLL-off mode wh dle mer of 80h, or 128 DCLKs. Ths s a balanced seng wh deep power-down mode and moderae dle mer value. The dle mer expraon coun defnes he # of DCKLs ha a rank s dle ha causes enry o he seleced powermode. As hs mer s se o a shorer me, he IMC wll have more opporunes o pu DDR n power-down. There s no IOS hook o se hs Daashee Volume 1 of 2 July Order No.:

55 Power Managemen Processors regser. Cusomers choosng o change he value of hs regser can do by changng n he IOS. For expermens, hs regser can be modfed n real me f IOS does no lock he IMC regsers Inalzaon Role of CKE Durng power-up, CKE s he only npu o he SDRAM ha has s level recognzed (oher han he DDR3L/DDR3L-RS rese pn) once power s appled. I mus be drven LOW by he DDR conroller o make sure he SDRAM componens floa DQ and DQS durng power-up. CKE sgnals reman LOW (whle any rese s acve) unl he IOS wres o a confguraon regser. Usng hs mehod, CKE s ensured o reman nacve for much longer han he specfed 200 mcro-seconds afer power and clocks o SDRAM devces are sable Condonal Self-Refresh Durng S0 dle sae, sysem memory may be condonally placed no self-refresh sae when he processor s n package C3 or deeper power sae. Refer o Inel Rapd Memory Power Managemen (Inel RMPM) for more deals on condonal selfrefresh wh Inel HD Graphcs enabled. When enerng he S3 Suspend-o-RAM (STR) sae or S0 condonal self-refresh, he processor core flushes pendng cycles and hen eners SDRAM ranks ha are no used by Inel graphcs memory no self-refresh. The CKE sgnals reman LOW so he SDRAM devces perform self-refresh. The arge behavor s o ener self-refresh for package C3 or deeper power saes as long as here are no memory requess o servce. The arge usage s shown n he followng able. Table 19. Targeed Memory Sae Condons Mode Memory Sae wh Processor Graphcs Memory Sae wh Exernal Graphcs C0, C1, C1E C3, C6, C7 or deeper Dynamc memory rank power-down based on dle condons. If he processor graphcs engne s dle and here are no pendng dsplay requess, hen ener self-refresh. Oherwse, use dynamc memory rank power-down based on dle condons. Dynamc memory rank power-down based on dle condons. If here are no memory requess, hen ener self-refresh. Oherwse, use dynamc memory rank power-down based on dle condons. S3 Self-Refresh Mode Self-Refresh Mode S4 Memory power-down (conens los) Memory power-down (conens los) Dynamc Power-Down Dynamc power-down of memory s employed durng normal operaon. ased on dle condons, a gven memory rank may be powered down. The IMC mplemens aggressve CKE conrol o dynamcally pu he DRAM devces n a power-down sae. The processor core conroller can be confgured o pu he devces n acve powerdown (CKE de-asseron wh open pages) or pre-charge power-down (CKE deasseron wh all pages closed). Pre-charge power-down provdes greaer power savngs, bu has a bgger performance mpac snce all pages wll frs be closed before pung he devces n power-down mode. July 2014 Daashee Volume 1 of 2 Order No.:

56 Processors Power Managemen If dynamc power-down s enabled, all ranks are powered up before dong a refresh cycle and all ranks are powered down a he end of refresh DRAM I/O Power Managemen Unused sgnals should be dsabled o save power and reduce elecromagnec nerference. Ths ncludes all sgnals assocaed wh an unused memory channel. Clocks, CKE, ODE, and CS sgnals are conrolled per DIMM rank and wll be powered down for unused ranks. The I/O buffer for an unused sgnal should be r-saed (oupu drver dsabled), he npu recever (dfferenal sense-amp) should be dsabled, and any DLL crcury relaed ONLY o unused sgnals should be dsabled. The npu pah mus be gaed o preven spurous resuls due o nose on he unused sgnals (ypcally handled auomacally when npu recever s dsabled) DDR Elecrcal Power Gang (EPG) The DDR I/O of he processor suppors Elecrcal Power Gang (DDR-EPG) whle he processor s a C3 or deeper power sae. In C3 or deeper power sae, he processor nernally gaes V DDQ for he majory of he logc o reduce dle power whle keepng all crcal DDR pns such as CKE and VREF n he approprae sae. In C7 or deeper power sae, he processor nernally gaes Vcc ST for all non-crcal sae o reduce dle power. In S3 or C-sae ransons, he DDR does no go hrough ranng mode and wll resore he prevous ranng nformaon Graphcs Power Managemen Inel Rapd Memory Power Managemen (Inel RMPM) Inel Rapd Memory Power Managemen (Inel RMPM) condonally places memory no self-refresh when he processor s n package C3 or deeper power sae o allow he sysem o reman n he lower power saes longer for memory no reserved for graphcs memory. Inel RMPM funconaly depends on graphcs/dsplay sae (relevan only when processor graphcs s beng used), as well as memory raffc paerns generaed by oher conneced I/O devces Graphcs Render C-Sae Render C-sae (RC6) s a echnque desgned o opmze he average power o he graphcs render engne durng mes of dleness. RC6 s enered when he graphcs render engne, bler engne, and he vdeo engne have no workload beng currenly worked on and no ousandng graphcs memory ransacons. When he dleness condon s me, he processor graphcs wll program he graphcs render engne nernal power ral no a low volage sae. Daashee Volume 1 of 2 July Order No.:

57 Power Managemen Processors Inel Smar 2D Dsplay Technology (Inel S2DDT) Inel S2DDT reduces dsplay refresh memory raffc by reducng memory reads requred for dsplay refresh. Power consumpon s reduced by less accesses o he IMC. Inel S2DDT s only enabled n sngle ppe mode. Inel S2DDT s mos effecve wh: Dsplay mages well sued o compresson, such as ex wndows, slde shows, and so on. Poor examples are 3D games. Sac screens such as screens wh sgnfcan porons of he background showng 2D applcaons, processor benchmarks, and so on, or condons when he processor s dle. Poor examples are full-screen 3D games and benchmarks ha flp he dsplay mage a or near dsplay refresh raes Inel Graphcs Dynamc Frequency Inel Graphcs Dynamc Frequency Technology s he ably of he processor and graphcs cores o opporunscally ncrease frequency and/or volage above he guaraneed processor and graphcs frequency for he gven par. Inel Graphcs Dynamc Frequency Technology s a performance feaure ha makes use of unused package power and hermals o ncrease applcaon performance. The ncrease n frequency s deermned by how much power and hermal budge s avalable n he package, and he applcaon demand for addonal processor or graphcs performance. The processor core conrol s mananed by an embedded conroller. The graphcs drver dynamcally adjuss beween P-Saes o manan opmal performance, power, and hermals. The graphcs drver wll always ry o place he graphcs engne n he mos energy effcen P-sae Inel Dsplay Power Savng Technology (Inel DPST) The Inel DPST echnque acheves backlgh power savngs whle mananng a good vsual experence. Ths s accomplshed by adapvely enhancng he dsplayed mage whle decreasng he backlgh brghness smulaneously. The goal of hs echnque s o provde equvalen end-user-perceved mage qualy a a decreased backlgh power level. 1. The orgnal (npu) mage produced by he operang sysem or applcaon s analyzed by he Inel DPST subsysem. An nerrup o Inel DPST sofware s generaed whenever a meanngful change n he mage arbues s deeced. (A meanngful change s when he Inel DPST sofware algorhm deermnes ha enough brghness, conras, or color change has occurred o he dsplayng mages ha he mage enhancemen and backlgh conrol needs o be alered.) 2. Inel DPST subsysem apples an mage-specfc enhancemen o ncrease mage conras, brghness, and oher arbues. 3. A correspondng decrease o he backlgh brghness s appled smulaneously o produce an mage wh smlar user-perceved qualy (such as brghness) as he orgnal mage. Inel DPST 6.0 has mproved he sofware algorhms and has mnor hardware changes o beer handle backlgh phase-n and ensures he documened and valdaed mehod o nerrup hardware phase-n. July 2014 Daashee Volume 1 of 2 Order No.:

58 Processors Power Managemen Inel Auomac Dsplay rghness The Inel Auomac Dsplay rghness feaure dynamcally adjuss he backlgh brghness based upon he curren amben lgh envronmen. Ths feaure requres an addonal sensor o be on he panel fron. The sensor receves he changng amben lgh condons and sends he nerrups o he Inel Graphcs drver. As per he change n Lux, (curren amben lgh llumnance), he new backlgh seng can be adjused hrough LC. The converse apples for a brghly l envronmen. Inel Auomac Dsplay rghness ncreases he backlgh seng Inel Seamless Dsplay Refresh Rae Technology (Inel SDRRS Technology) When a Local Fla Panel (LFP) suppors mulple refresh raes, he Inel Dsplay Refresh Rae Swchng power conservaon feaure can be enabled. The hgher refresh rae wll be used when plugged n wh an AC power adapor or when he end user has no seleced/enabled hs feaure. The graphcs sofware wll auomacally swch o a lower refresh rae for maxmum baery lfe when he noebook s on baery power and when he user has seleced/enabled hs feaure. There are wo dsnc mplemenaons of Inel DRRS sac and seamless. The sac Inel DRRS mehod uses a mode change o assgn he new refresh rae. The seamless Inel DRRS mehod s able o accomplsh he refresh rae assgnmen whou a mode change and herefore does no experence some of he vsual arfacs assocaed wh he mode change (SeMode) mehod. Daashee Volume 1 of 2 July Order No.:

59 Thermal Managemen Processors 5.0 Thermal Managemen The hermal soluon provdes boh componen-level and sysem-level hermal managemen. To allow for he opmal operaon and long-erm relably of Inel processor-based sysems, he sysem/processor hermal soluon should be desgned so ha he processor: Remans below he maxmum juncon emperaure (Tj Max ) specfcaon a he maxmum hermal desgn power (TDP). Conforms o sysem consrans, such as sysem acouscs, sysem sknemperaures, and exhaus-emperaure requremens. Cauon: Thermal specfcaons gven n hs chaper are on he componen and package level and apply specfcally o he processor. Operang he processor ousde he specfed lms may resul n permanen damage o he processor and poenally oher componens n he sysem. 5.1 Thermal Consderaons The processor TDP s he maxmum susaned power ha should be used for desgn of he processor hermal soluon. TDP represens an expeced maxmum susaned power from realsc applcaons. TDP may be exceeded for shor perods of me or f runnng a "power vrus" workload. The processor negraes mulple processng and graphcs cores and PCH on a sngle package.ths may resul n dfferences n he power dsrbuon across he de and mus be consdered when desgnng he hermal soluon. Inel Turbo oos Technology 2.0 allows processor cores and processor graphcs cores o run faser han he guaraneed frequency. I s nvoked opporunscally and auomacally as long as he processor s conformng o s emperaure, power delvery, and curren specfcaon lms. When Inel Turbo oos Technology 2.0 s enabled: Applcaons are expeced o run closer o TDP more ofen as he processor wll aemp o maxmze performance by akng advanage of avalable TDP headroom n he processor package. The processor may exceed he TDP for shor duraons o use any avalable hermal capacance whn he hermal soluon. The duraon and me of such operaon can be lmed by plaform runme confgurable regsers whn he processor. Thermal soluons and plaform coolng ha are desgned o less han hermal desgn gudance may experence hermal and performance ssues snce more applcaons wll end o run a or near TDP for sgnfcan perods of me. Noe: Inel Turbo oos Technology 2.0 avalably may vary beween he dfferen SKUs. July 2014 Daashee Volume 1 of 2 Order No.:

60 Processors Thermal Managemen 5.2 Inel Turbo oos Technology 2.0 Power Monorng When operang n urbo mode, he processor monors s own power and adjuss he urbo frequences o manan he average power whn lms over a hermally sgnfcan me perod. The processor calculaes he package power ha consss of he processor core power and graphcs core power. In he even ha a workload causes he power o exceed program power lms, he processor wll proec self usng he Adapve Thermal Monor. 5.3 Inel Turbo oos Technology 2.0 Power Conrol Illusraon of Inel Turbo oos Technology 2.0 power conrol s shown n he followng secons and fgures. Mulple conrols operae smulaneously allowng for cusomzaon for mulple sysem hermal and power lmaons. These conrols allow for urbo opmzaons whn sysem consrans and are accessble usng MSR, MMIO, or PECI nerfaces Package Power Conrol The package power conrol allows for cusomzaon o mplemen opmal urbo whn plaform power delvery and package hermal soluon lmaons. Table 20. MSR: Address: Inel Turbo oos Technology 2.0 Package Power Conrol Sengs MSR_TURO_POWER_LIMIT 610h Conrol Defaul Descrpon POWER_LIMIT_1 (PL1) 14:0 SKU TDP Ths value ses he average power lm over a long me perod. Ths s normally algned o he TDP of he par and seady-sae coolng capably of he hermal soluon. The defaul value s he TDP for he SKU. PL1 lm may be se lower han TDP n real me for specfc needs, such as respondng o a hermal even. If s se lower han TDP, he processor may requre o use frequences below he guaraneed P1 frequency o conrol he low-power lms. The PL1 Clamp b [16] should be se o enable he processor o use frequences below P1 o conrol he sepower lm. PL1 lm may be se hgher han TDP. If se hgher han TDP, he processor could say a ha power level connuously and coolng soluon mprovemens may be requred. POWER_LIMIT_1_TIME (Turbo Tme Parameer) 23:17 1 sec Ths value s a me parameer ha adjuss he algorhm behavor o manan me averaged power a or below PL1. The hardware defaul value s 1 second; however, 28 seconds s recommended for mos moble applcaons. POWER_LIMIT_2 (PL2) 46: x TDP PL2 esablshes he upper power lm of urbo operaon above TDP, prmarly for plaform power supply consderaons. Power may exceed hs lm for up o 10 ms. The defaul for hs lm s 1.25 x TDP; however, he IOS may reprogram he defaul value o maxmze he performance whn plaform power supply consderaons. Seng hs lm o TDP wll lm he processor o only operae up o he TDP. I does no dsable urbo because urbo s opporunsc and power/emperaure dependen. Many workloads wll allow some urbo frequences for powers a or below TDP. Daashee Volume 1 of 2 July Order No.:

61 Thermal Managemen Processors Fgure 12. Package Power Conrol Turbo Tme Parameer Turbo Tme Parameer s a mahemacal parameer (uns n seconds) ha conrols he Inel Turbo oos Technology 2.0 algorhm usng movng average of energy usage. Durng a maxmum power urbo even of abou 1.25 x TDP, he processor could susan PL2 for up o approxmaely 1.5 mes he Turbo Tme Parameer. If he power value and/or Turbo Tme Parameer s changed durng runme, may ake approxmaely 3 o 5 mes he Turbo Tme Parameer for he algorhm o sele a he new conrol lms. The me vares dependng on he magnude of he change and oher facors. There s an ndvdual Turbo Tme Parameer assocaed wh Package Power Conrol. 5.4 Confgurable TDP (ctdp) and Low-Power Mode Confgurable TDP (ctdp) and Low-Power Mode (LPM) form a desgn vecor where he processor's behavor and package TDP are dynamcally adjused o a desred sysem performance and power envelope. Confgurable TDP and Low-Power Mode echnologes offer opporunes o dfferenae sysem desgn whle runnng acve workloads on selec processor SKUs hrough scalably, confguraon and adapably. The scenaros or mehods by whch each echnology s used are cusomzable bu ypcally nvolve changes o PL1 and assocaed frequences for he scenaro wh a resulan change n performance dependng on sysem's usage. Eher echnology can be rggered by (bu are no lmed o) changes n OS power polces or hardware evens such as dockng a sysem, flppng a swch or pressng a buon. ctdp and LPM are desgned o be confgured dynamcally and do no requre an operang sysem reboo. Noe: Noe: Confgurable TDP and Low-Power Mode echnologes are no baery lfe mprovemen echnologes. Confgurable TDP Confgurable TDP avalably may vary beween he dfferen SKUs. Wh ctdp, he processor s now capable of alerng he maxmum susaned power wh an alernae IA core base frequency. Confgurable TDP allows operaon n suaons where exra coolng s avalable or suaons where a cooler and queer mode of operaon s desred. Confgurable TDP can be enabled usng Inel's DPTF drver or hrough HW/EC frmware. Enablng ctdp usng he DPTF drver s recommended as Inel does no provde specfc applcaon or EC source code. July 2014 Daashee Volume 1 of 2 Order No.:

62 Processors Thermal Managemen ctdp consss of hree modes as shown n he followng able. Table 21. Confgurable TDP Modes Mode Nomnal TDP-Up TDP-Down Descrpon Ths s he processor's raed frequency and TDP. When exra coolng s avalable, hs mode specfes a hgher TDP and hgher guaraneed frequency versus he nomnal mode. When a cooler or queer mode of operaon s desred, hs mode specfes a lower TDP and lower guaraneed frequency versus he nomnal mode. In each mode, he Inel Turbo oos Technology 2.0 power and frequency ranges are reprogrammed and he OS s gven a new effecve HFM operang pon. The Inel DPTF drver assss n all hese operaons. The ctdp mode does no change he max per-core urbo frequency Low-Power Mode Low-Power Mode (LPM) can provde cooler and queer sysem operaon. y combnng several acve power lmng echnques, he processor can consume less power whle runnng a equvalen low frequences. Acve power s defned as processor power consumed whle a workload s runnng and does no refer o he power consumed durng dle modes of operaon. LPM s only avalable usng he Inel DPTF drver. Through he DPTF drver, LPM can be confgured o use each of he followng mehods o reduce acve power: Resrcng Inel Turbo oos Power lms and IA core Turbo oos avalably Off-Lnng core acvy (Move processor raffc o a subse of cores) Placng an IA Core a LFM or LSF (Lowes Suppored Frequency) Ulzng IA clock modulaon Reducng number of acve EUs o GT2 equvalen (Applcable for GT3 SKUs Only) LPM power as lsed n he TDP Specfcaons able s defned a a pon whch IA cores workng a MFM, GT = RPn and 1 core acve Off-lnng core acvy s he ably o dynamcally scale a workload o a lmed subse of cores n conjuncon wh a lower urbo power lm. I s one of he man vecors avalable o reduce acve power. However, no all processor acvy s ensured o be able o shf o a subse of cores. Shfng a workload o a lmed subse of cores allows oher cores o reman dle and save power. Therefore, when LPM s enabled, less power s consumed a equvalen frequences. Mnmum Frequency Mode (MFM) of operaon, whch s he lowes suppored frequency (LSF) a he LFM volage, has been made avalable for use under LPM for furher reducon n acve power beyond LFM capably o enable cooler and queer modes of operaon. 5.5 Thermal and Power Specfcaons The followng noes apply o Table 22 on page 63 and Table 23 on page 64. Daashee Volume 1 of 2 July Order No.:

63 Thermal Managemen Processors Noe 1 Defnon The TDPs gven are no he maxmum power he processor can generae. Analyss ndcaes ha real applcaons are unlkely o cause he processor o consume he heorecal maxmum power dsspaon for susaned perods of me. 2 TDP workload may conss of a combnaon of processor-core nensve and graphcs-core nensve applcaons The hermal soluon needs o ensure ha he processor emperaure does no exceed he maxmum juncon emperaure (Tj MAX ) lm, as measured by he DTS and he crcal emperaure b. The processor juncon emperaure s monored by Dgal Temperaure Sensors (DTS). For DTS accuracy, refer o Dgal Thermal Sensor Accuracy (Taccuracy) on page 68. Dgal Thermal Sensor (DTS) based fan speed conrol s requred o acheve opmal hermal performance. Inel recommends full coolng capably well before he DTS readng reaches Tj MAX. An example of hs s Tj MAX 10 ºC. The dle power specfcaons are no 100% esed. These power specfcaons are deermned by he characerzaon a hgher emperaures and exrapolang he values for he juncon emperaure ndcaed. 7 A Tj of Tj MAX 8 A Tj of 50 ºC 9 A Tj of 35 ºC 10 Can be modfed a runme by MSR wres, wh MMIO and wh PECI commands 'Turbo Tme Parameer' s a mahemacal parameer (un n seconds) ha conrols he processor urbo algorhm usng a movng average of energy usage. Do no se he Turbo Tme Parameer o a value less han 0.1 seconds. Refer o Turbo Tme Parameer on page 61 for furher nformaon. Shown lm s a me averaged power, based upon he Turbo Tme Parameer. Absolue produc power may exceed he se lms for shor duraons or under vrus or uncharacerzed workloads. Processor wll be conrolled o specfed power lm as descrbed n Inel Turbo oos Technology 2.0 Power Monorng on page 60. If he power value and/or 'Turbo Tme Parameer' s changed durng runme, may ake a shor perod of me (approxmaely 3 o 5 mes he 'Turbo Tme Parameer') for he algorhm o sele a he new conrol lms. 14 Ths s a hardware defaul seng and no a behavoral characersc of he par. 15 For conrollable urbo workloads, lm may be exceeded for up o 10 ms. 16 Refer o Table 21 on page 62 for he defnons of 'TDP-Nomnal', 'TDP-Up', 'TDP-Down'. 17 LPM power level s an opporunsc power and s no a guaraneed value as usages and mplemenaons may vary. 18 Power lms may vary dependng on f he produc suppors he 'TDP-up' and/or 'TDP-down' modes. Defaul power lms can be found n he PKG_PWR_SKU MSR (614h). 19 May vary based on SKU. 20 ctdp down power s based on GT2 equvalen graphcs confguraon. ctdp down does no decrease he number of acve Processor Graphcs EUs, bu reles on Power udge Managemen (PL1) o acheve he specfed power level. 21 Hardware defaul values mgh be overrdden by he IOS. Table 22. Thermal Desgn Power (TDP) Specfcaons Segmen Sae Processor Core Frequency Processor Graphcs Core Frequency Thermal Desgn Power Uns Noes U-Processor (Dual Core) 28W GT3 TDP-Nomnal / HFM TDP-Down / LFM 2.0 GHz up o GHz 200 MHz up o 1200 MHz 800 MHz 23 LPM 800 MHz 200 MHz 22.5 W 1, 2, 7, 16, 17, 18 July 2014 Daashee Volume 1 of 2 Order No.:

64 Processors Thermal Managemen Segmen Sae Processor Core Frequency Processor Graphcs Core Frequency Thermal Desgn Power Uns Noes U-Processor (Dual Core) 15W GT3 TDP Nomnal / HFM TDP-Down / LFM 1.3 GHz up o GHz 200 MHz up o 1100 MHz 800 MHz 11.5 LPM 800 MHz 200 MHz 11 W 1, 2, 7, 16, 17, 18 U-Processor (Dual Core) 15W GT2 TDP-Up TDP Nomnal / HFM TDP-Down / LFM 1.6 GHz up o 2.3 GHz 200 MHz up o 1100 MHz 800 MHz W 1, 2, 7, 16, 17, 18 Y-Processor (Dual Core) 11.5W (6W SDP / 4.5W SDP) LPM 800 MHz 200 MHz 11 TDP Nomnal / HFM TDP-Down / LFM 1.3 GHz up o 1.4 GHz 800 MHz 200 MHz up o 850 MHz (6W SDP / 4.5W SDP) LPM 600 MHz 200 MHz 9 W 19 Table 23. Juncon Temperaure Specfcaon Segmen Symbol Package Turbo Parameer Mn Defaul Max Uns Noes U-Processor (Dual Core) T j Juncon emperaure lm ºC 3, 4, 5 Y-Processor (Dual Core) T j Juncon emperaure lm ºC 3, 4, 5 Table 24. Maxmum Idle Power Specfcaon Symbol Parameer U-Processor 15W wh GT3 U-Processor 28W wh GT3 Y-Processor 6W SDP / 4.5W SDP wh GT2 Un Noe P PACKAGE(C7) P PACKAGE(C8) P PACKAGE(C9) P PACKAGE(C10) P PACKAGE(Sx/M3) INT_SUS P PACKAGE(Sx/Moff) INT_SUS Package power n Package C7 sae Package power n Package C8 sae Package power n Package C9 sae Package power n Package C10 sae Package power n Sysem S3/S4/S5 and M3 sae (nernal Suspend) Package power n Sysem S3/S4/S5 and Moff sae (nernal Suspend) Mn Max Mn Max Mn Max W 1, W W W 1, mw 1, mw 1, 2 Daashee Volume 1 of 2 July Order No.:

65 Thermal Managemen Processors Symbol Parameer U-Processor 15W wh GT3 U-Processor 28W wh GT3 Y-Processor 6W SDP / 4.5W SDP wh GT2 Un Noe P PACKAGE(Sx/M3) EXT_SUS P PACKAGE(Sx/Moff) EXT_SUS P PACKAGE(Deep Sx) Package power n Sysem S3/S4/S5 and M3 sae (exernal Suspend) Package power n Sysem S3/S4/S5 and Moff sae (exernal Suspend) Package power n Sysem Deep Sx sae Mn Max Mn Max Mn Max mw 1, mw 1, mw 1, 2 Noes: 1. Package power ncludes boh MCP componens: processor and PCH. 2. Measured a Tj = 35 C. 3. The C7 power s measured wh LLC ON. 4. The C10 power s measured wh LAN dsabled. 5.6 Thermal Managemen Feaures Occasonally he processor may operae n condons ha are near o s maxmum operang emperaure. Ths can be due o nernal overheang or overheang whn he plaform. To proec he processor and he plaform from hermal falure, several hermal managemen feaures exs o reduce package power consumpon and hereby emperaure n order o reman whn normal operang lms. Furhermore, he processor suppors several mehods o reduce memory power Adapve Thermal Monor The purpose of he Adapve Thermal Monor s o reduce processor core power consumpon and emperaure unl operaes a or below s maxmum operang emperaure. Processor core power reducon s acheved by: Adjusng he operang frequency (usng he core rao mulpler) and volage. Modulang (sarng and soppng) he nernal processor core clocks (duy cycle). The Adapve Thermal Monor can be acvaed when he package emperaure, monored by any dgal hermal sensor (DTS) mees or exceeds s maxmum operang emperaure. The maxmum operang emperaure mples eher maxmum juncon emperaure Tj MAX, or Tj MAX mnus TCC Acvaon offse. Exceedng he maxmum operang emperaure acvaes he hermal conrol crcu (TCC), f enabled. When acvaed he hermal conrol crcu (TCC) causes boh he processor core and graphcs core o reduce frequency and volage adapvely. The Adapve Thermal Monor wll reman acve as long as he package emperaure exceeds s specfed lm. Therefore, he Adapve Thermal Monor wll connue o reduce he package frequency and volage unl he TCC s de-acvaed. Tj MAX s facory calbraed and s no user confgurable. The defaul value s sofware vsble n he TEMPERATURE_TARGET (0x1A2) MSR, bs [23:16]. The TEMPERATURE_TARGET value says he same when TCC Acvaon offse s enabled. July 2014 Daashee Volume 1 of 2 Order No.:

66 Processors Thermal Managemen The Adapve Thermal Monor does no requre any addonal hardware, sofware drvers, or nerrup handlng rounes. I s no nended as a mechansm o manan processor TDP. The sysem desgn should provde a hermal soluon ha can manan TDP whn s nended usage range. Noe: Adapve Thermal Monor proecon s always enabled. Thermal Conrol Crcu (TCC) Acvaon Offse TCC Acvaon Offse can be used o acvae he Adapve Thermal Monor a emperaures lower han Tj MAX. I s he preferred hermal proecon mechansm for Inel Turbo oos Technology 2.0 operaon snce ACPI passve hrolng saes wll pull he processor ou of urbo mode operaon when rggered. An offse (n degrees Celsus) can be wren o he TEMPERATURE_TARGET (0x1A2) MSR, bs [29:24]. Ths value wll be subraced from he value found n bs [23:16]. The defaul offse s 0 C, TCC acvaon wll occur a Tj MAX. The offse should be se lower han any oher proecon such as ACPI _PSV rp pons Frequency / Volage Conrol Upon Adapve Thermal Monor acvaon, he processor core aemps o dynamcally reduce processor core power by lowerng he frequency and volage operang pon. The operang pons are auomacally calculaed by he processor core self and do no requre he IOS o program hem as wh prevous generaons of Inel processors. The processor core wll scale he operang pons such ha: The volage wll be opmzed accordng o he emperaure, he core bus rao, and number of cores n deep C-saes. The core power and emperaure are reduced whle mnmzng performance degradaon. Once he emperaure has dropped below he maxmum operang emperaure, he operang frequency and volage wll ranson back o he normal sysem operang pon. Once a arge frequency/bus rao s resolved, he processor core wll ranson o he new arge auomacally. On an upward operang pon ranson, he volage ranson precedes he frequency ranson. On a downward ranson, he frequency ranson precedes he volage ranson. The processor connues o execue nsrucons. However, he processor wll hal nsrucon execuon for frequency ransons. If a processor load-based Enhanced Inel SpeedSep Technology/P-sae ranson (hrough MSR wre) s naed whle he Adapve Thermal Monor s acve, here are wo possble oucomes: If he P-sae arge frequency s hgher han he processor core opmzed arge frequency, he P-sae ranson wll be deferred unl he hermal even has been compleed. If he P-sae arge frequency s lower han he processor core opmzed arge frequency, he processor wll ranson o he P-sae operang pon. Daashee Volume 1 of 2 July Order No.:

67 Thermal Managemen Processors Clock Modulaon If he frequency/volage changes are unable o end an Adapve Thermal Monor even, he Adapve Thermal Monor wll ulze clock modulaon. Clock modulaon s done by alernaely urnng he clocks off and on a a duy cycle (rao beween clock "on" me and oal me) specfc o he processor. The duy cycle s facory confgured o 25% on and 75% off and canno be modfed. The perod of he duy cycle s confgured o 32 mcroseconds when he Adapve Thermal Monor s acve. Cycle mes are ndependen of processor frequency. A small amoun of hyseress has been ncluded o preven excessve clock modulaon when he processor emperaure s near s maxmum operang emperaure. Once he emperaure has dropped below he maxmum operang emperaure, and he hyseress mer has expred, he Adapve Thermal Monor goes nacve and clock modulaon ceases. Clock modulaon s auomacally engaged as par of he Adapve Thermal Monor acvaon when he frequency/volage arges are a her mnmum sengs. Processor performance wll be decreased by he same amoun as he duy cycle when clock modulaon s acve. Snoopng and nerrup processng are performed n he normal manner whle he Adapve Thermal Monor s acve Dgal Thermal Sensor Each processor execuon core has an on-de Dgal Thermal Sensor (DTS) ha deecs he core's nsananeous emperaure. The DTS s he preferred mehod of monorng processor de emperaure because: I s locaed near he hoes porons of he de. I can accuraely rack he de emperaure and ensure ha he Adapve Thermal Monor s no excessvely acvaed. Temperaure values from he DTS can be rereved hrough: A sofware nerface usng processor Model Specfc Regser (MSR). A processor hardware nerface as descrbed n Plaform Envronmenal Conrol Inerface (PECI) on page 29. When emperaure s rereved by he processor MSR, s he nsananeous emperaure of he gven core. When emperaure s rereved usng PECI, s he average of he hghes DTS emperaure n he package over a 256 ms me wndow. Inel recommends usng he PECI repored emperaure for plaform hermal conrol ha benefs from averagng, such as fan speed conrol. The average DTS emperaure may no be a good ndcaor of package Adapve Thermal Monor acvaon or rapd ncreases n emperaure ha rggers he Ou of Specfcaon saus b whn he PACKAGE_THERM_STATUS MSR 11h and IA32_THERM_STATUS MSR 19Ch. Code execuon s haled n C1 or deeper C-saes. Package emperaure can sll be monored hrough PECI n lower C-saes. Unlke radonal hermal devces, he DTS oupus a emperaure relave o he maxmum suppored operang emperaure of he processor (Tj MAX ), regardless of TCC acvaon offse. I s he responsbly of sofware o conver he relave emperaure o an absolue emperaure. The absolue reference emperaure s readable n he TEMPERATURE_TARGET MSR 1A2h. The emperaure reurned by he DTS s an mpled negave neger ndcang he relave offse from Tj MAX. The DTS does no repor emperaures greaer han Tj MAX. The DTS-relave emperaure readou drecly mpacs he Adapve Thermal Monor rgger pon. When a package July 2014 Daashee Volume 1 of 2 Order No.:

68 Processors Thermal Managemen DTS ndcaes ha has reached he TCC acvaon (a readng of 0h, excep when he TCC acvaon offse s changed), he TCC wll acvae and ndcae an Adapve Thermal Monor even. A TCC acvaon wll lower boh IA core and graphcs core frequency, volage, or boh. Changes o he emperaure can be deeced usng wo programmable hresholds locaed n he processor hermal MSRs. These hresholds have he capably of generang nerrups usng he core's local APIC. Refer o he Inel 64 and IA-32 Archecures Sofware Developer s Manual for specfc regser and programmng deals Dgal Thermal Sensor Accuracy (Taccuracy) The error assocaed wh DTS measuremens wll no exceed ±5 C whn he enre operang range Fan Speed Conrol wh Dgal Thermal Sensor Dgal Thermal Sensor based fan speed conrol (T FAN ) s a recommended feaure o acheve opmal hermal performance. A he T FAN emperaure, Inel recommends full coolng capably well before he DTS readng reaches Tj MAX PROCHOT# Sgnal PROCHOT# (processor ho) s assered when he processor emperaure has reached s maxmum operang emperaure (Tj MAX ). Only a sngle PROCHOT# pn exss a a package level. When any core arrves a he TCC acvaon pon, he PROCHOT# sgnal wll be assered. PROCHOT# asseron polces are ndependen of Adapve Thermal Monor enablng Dreconal PROCHOT# y defaul, he PROCHOT# sgnal s se o b-dreconal. However, s recommended o confgure he sgnal as an npu only. When confgured as an npu or b-dreconal sgnal, PROCHOT# can be used for hermally proecng oher plaform componens n case he componens overhea as well. When PROCHOT# s drven by an exernal devce: The package wll mmedaely ranson o he lowes P-Sae (Pn) suppored by he processor and graphcs cores. Ths s conrary o he nernally-generaed Adapve Thermal Monor response. Clock modulaon s no acvaed. The processor package wll reman a he lowes suppored P-sae unl he sysem de-assers PROCHOT#. The processor can be confgured o generae an nerrup upon asseron and de-asseron of he PROCHOT# sgnal. Noe: When PROCHOT# s confgured as a b-dreconal sgnal and PROCHOT# s assered by he processor, s mpossble for he processor o deec a sysem asseron of PROCHOT#. The sysem asseron wll have o wa unl he processor de-assers PROCHOT# before PROCHOT# acon can occur due o he sysem asseron. Whle he processor s ho and asserng PROCHOT#, he power s reduced; however, he reducon rae s slower han he sysem PROCHOT# response of < 100 us. The processor hermal conrol s saged n smaller ncremens over many mllseconds. Ths may cause several mllseconds of delay o a sysem asseron of PROCHOT# whle he oupu funcon s assered. Daashee Volume 1 of 2 July Order No.:

69 Thermal Managemen Processors Volage Regulaor Proecon usng PROCHOT# PROCHOT# may be used for hermal proecon of volage regulaors (VR). Sysem desgners can creae a crcu o monor he VR emperaure and asser PROCHOT# and, f enabled, acvae he TCC when he emperaure lm of he VR s reached. When PROCHOT# s confgured as a b-dreconal or npu only sgnal, f he sysem asseron of PROCHOT# s recognzed by he processor, wll resul n an mmedae ranson o he lowes P-Sae (Pn) suppored by he processor and graphcs cores. Sysems should sll provde proper coolng for he VR and rely on b-dreconal PROCHOT# only as a backup n case of sysem coolng falure. Overall, he sysem hermal desgn should allow he power delvery crcury o operae whn s emperaure specfcaon even whle he processor s operang a s TDP Thermal Soluon Desgn and PROCHOT# ehavor Wh a properly desgned and characerzed hermal soluon, s ancpaed ha PROCHOT# wll only be assered for very shor perods of me when runnng he mos power nensve applcaons. The processor performance mpac due o hese bref perods of TCC acvaon s expeced o be so mnor ha would be mmeasurable. However, an under-desgned hermal soluon ha s no able o preven excessve asseron of PROCHOT# n he ancpaed amben envronmen may: Cause a noceable performance loss. Resul n prolonged operaon a or above he specfed maxmum juncon emperaure and affec he long-erm relably of he processor. May be ncapable of coolng he processor even when he TCC s acve connuously (n exreme suaons) Low-Power Saes and PROCHOT# ehavor Dependng on package power levels durng package C-saes, oubound PROCHOT# may de-asser whle he processor s dle as power s removed from he sgnal. Upon wakeup, f he processor s sll ho, he PROCHOT# wll re-asser, alhough ypcally package dle sae resdency should resolve any hermal ssues. The PECI nerface s fully operaonal durng all C-saes and s expeced ha he plaform connues o manage processor core and package hermals even durng dle saes by regularly pollng for hermal daa over PECI THERMTRIP# Sgnal Regardless of enablng he auomac or on-demand modes, n he even of a caasrophc coolng falure, he package wll auomacally shu down when he slcon has reached an elevaed emperaure ha rsks physcal damage o he produc. A hs pon he THERMTRIP# sgnal wll go acve Crcal Temperaure Deecon Crcal Temperaure deecon s performed by monorng he package emperaure. Ths feaure s nended for graceful shudown before he THERMTRIP# s acvaed. However, he processor execuon s no guaraneed beween crcal emperaure and THERMTRIP#. If he Adapve Thermal Monor s rggered and he emperaure remans hgh, a crcal emperaure saus and scky b are lached n he PACKAGE_THERM_STATUS MSR 11h and he condon also generaes a hermal nerrup, f enabled. For more deals on he nerrup mechansm, refer o he Inel 64 and IA-32 Archecures Sofware Developer s Manual. July 2014 Daashee Volume 1 of 2 Order No.:

70 Processors Thermal Managemen On-Demand Mode The processor provdes an auxlary mechansm ha allows sysem sofware o force he processor o reduce s power consumpon usng clock modulaon. Ths mechansm s referred o as "On-Demand" mode and s dsnc from Adapve Thermal Monor and b-dreconal PROCHOT#. The processor plaforms mus no rely on sofware usage of hs mechansm o lm he processor emperaure. On-Demand Mode can be accomplshed usng processor MSR or chpse I/O emulaon. On-Demand Mode may be used n conjuncon wh he Adapve Thermal Monor. However, f he sysem sofware res o enable On-Demand mode a he same me he TCC s engaged, he facory confgured duy cycle of he TCC wll overrde he duy cycle seleced by he On-Demand mode. If he I/O based and MSR-based On-Demand modes are n conflc, he duy cycle seleced by he I/O emulaon-based On-Demand mode wll ake precedence over he MSR-based On-Demand Mode MSR ased On-Demand Mode If 4 of he IA32_CLOCK_MODULATION MSR s se o a 1, he processor wll mmedaely reduce s power consumpon usng modulaon of he nernal core clock, ndependen of he processor emperaure. The duy cycle of he clock modulaon s programmable usng bs [3:1] of he same IA32_CLOCK_MODULATION MSR. In hs mode, he duy cycle can be programmed n eher 12.5% or 6.25% ncremens (dscoverable usng CPUID). Thermal hrolng usng hs mehod wll modulae each processor core's clock ndependenly I/O Emulaon-ased On-Demand Mode I/O emulaon-based clock modulaon provdes legacy suppor for operang sysem sofware ha naes clock modulaon hrough I/O wres o ACPI defned processor clock conrol regsers on he chpse (PROC_CNT). Thermal hrolng usng hs mehod wll modulae all processor cores smulaneously Inel Memory Thermal Managemen The processor provdes hermal proecon for sysem memory by hrolng memory raffc when usng eher DIMM modules or a memory down mplemenaon. Two levels of hrolng are suppored by he processor eher a warm hreshold or ho hreshold ha s cusomzable hrough memory mapped I/O regsers. Throlng based on he warm hreshold should be an nermedae level of hrolng. Throlng based on he ho hreshold should be he mos severe. The amoun of hrolng s dynamcally conrolled by he processor. Memory emperaure can be acqured hrough an on-board hermal sensor (TS-on- oard), rereved by an embedded conroller and repored o he processor hrough he PECI 3.0 nerface. Ths mehodology s known as PECI njeced emperaures and s a mehod of Closed Loop Thermal Managemen (CLTM). CLTM requres he use of a physcal hermal sensor. EXTTS# s anoher mehod of CLTM; however, s only capable of reporng memory hermal saus o he processor. EXTTS# consss of wo GPIO pns on he PCH where he sae of he pns s communcaed nernally o he processor. Daashee Volume 1 of 2 July Order No.:

71 Thermal Managemen Processors When a physcal hermal sensor s no avalable o repor emperaure, he processor suppors Open Loop Thermal Managemen (OLTM) ha esmaes he power consumed per rank of he memory usng he processor DRAM power meer. A per rank power s assocaed wh he warm and ho hresholds ha, when exceeded, may rgger memory hermal hrolng Scenaro Desgn Power (SDP) Scenaro Desgn Power (SDP) s a usage-based desgn specfcaon, and provdes an addonal reference desgn pon for power consraned plaforms. SDP s a specfed power level under a specfc scenaro workload, emperaure, and frequency. Inel recommends seng POWER_LIMIT_1 (PL1) o he sysem coolng capably (SDP level, or hgher). Whle he SDP specfcaon s characerzed a Tj of 80 C, he funconal lm for he produc remans a Tj MAX. Cusomers may choose o have he processor nvoke TCC Acvaon Throlng a 80 C, bu s no requred. The processors ha have SDP specfed can sll exceed SDP under ceran workloads, such as TDP workloads. TDP power dsspaon s sll possble wh he nended usage models, and proecon mechansms o handle levels beyond coolng capables are recommended. Inel recommends usng such hermal conrol mechansms o manage suaons where power may exceed he hermal desgn capably. Noe: Noe: ctdp-down mode s requred for Inel Core processor producs n order o acheve SDP. Alhough SDP s defned a 80 C, he TCC acvaon emperaure s 100 C, and may be changed n IOS o 80 C. July 2014 Daashee Volume 1 of 2 Order No.:

72 Processors Sgnal Descrpon 6.0 Sgnal Descrpon Ths chaper descrbes he processor sgnals. The sgnals are arranged n funconal groups accordng o he assocaed nerface or caegory. The followng noaons are used o descrbe he sgnal ype. Noaon Sgnal Type I O I/O Inpu pn Oupu pn -dreconal Inpu/Oupu pn The sgnal descrpon also ncludes he ype of buffer used for he parcular sgnal (see he followng able). Table 25. Sgnal Descrpon uffer Types Sgnal Descrpon CMOS DDR3L/DDR3L- RS LPDDR3 A GTL VR Enable CMOS Ref Asynchronous 1 CMOS buffers. 1.05V- oleran DDR3L/DDR3L-RS buffers: 1.35 V-oleran LPDDR3 buffers: 1.2 V- oleran Analog reference or oupu. May be used as a hreshold volage or for buffer compensaon Gunnng Transcever Logc sgnalng echnology Volage Regulaor Asynchronous CMOS oupu Volage reference sgnal Sgnal has no mng relaonshp wh any reference clock. 1. Qualfer for a buffer ype. 6.1 Table 26. Sysem Memory Inerface Sgnals DDR3L / DDR3L-RS Memory Channel A Inerface (Memory-Down / SO-DIMM) Sgnals Sgnal Name Descrpon Drecon / uffer Type SA_S[2:0] SA_WE# ank Selec: These sgnals defne whch banks are seleced whn each SDRAM rank. Wre Enable Conrol Sgnal: Ths sgnal s used wh SA_RAS# and SA_CAS# (along wh SA_CS#) o defne he SDRAM Commands. O O Daashee Volume 1 of 2 July Order No.:

73 Sgnal Descrpon Processors Sgnal Name Descrpon Drecon / uffer Type SA_RAS# SA_CAS# SA_DQSP[7:0] SA_DQSN[7:0] SA_DQ[63:0] SA_MA[15:0] SA_CKP[1:0] SA_CKN[1:0] SA_CS#[1:0] SA_CKE[3:0] RAS Conrol Sgnal: Ths sgnal s used wh SA_CAS# and SA_WE# (along wh SA_CS#) o defne he SRAM Commands. CAS Conrol Sgnal: Ths sgnal s used wh SA_RAS# and SA_WE# (along wh SA_CS#) o defne he SRAM Commands. Daa Srobes: SA_DQS[7:0] and s complemen sgnal group make up a dfferenal srobe par. The daa s capured a he crossng pon of SA_DQS[7:0] and s SA_DQS#[7:0] durng read and wre ransacons. Daa us: Channel A daa sgnal nerface o he SDRAM daa bus. Memory Address: These sgnals are used o provde he mulplexed row and column address o he SDRAM. SDRAM Dfferenal Clock: Channel A SDRAM Dfferenal clock sgnal par. The crossng of he posve edge of SA_CKP and he negave edge of s complemen SA_CKN are used o sample he command and conrol sgnals on he SDRAM. Chp Selec: (1 per rank). These sgnals are used o selec parcular SDRAM componens durng he acve sae. There s one Chp Selec for each SDRAM rank. Clock Enable: (1 per rank). These sgnals are used o: Inalze he SDRAMs durng power-up Power down SDRAM ranks Place all SDRAM ranks no and ou of self-refresh durng STR When 1R DDR3L (SODIMM/MD) CKE[0] s used When 2R DDR3L (SODIMM/MD) CKE[1:0] are used O O I/O I/O O O O O SA_ODT On De Termnaon: Acve Termnaon Conrol. O Table 27. DDR3L / DDR3L-RS Memory Channel Inerface (Memory-Down / SO-DIMM) Sgnals Sgnal Name Descrpon Drecon / uffer Type S_S[2:0] S_WE# S_RAS# S_CAS# S_DQSP[7:0] S_DQSN[7:0] S_DQ[63:0] ank Selec: These sgnals defne whch banks are seleced whn each SDRAM rank. Wre Enable Conrol Sgnal: Ths sgnal s used wh S_RAS# and S_CAS# (along wh S_CS#) o defne he SDRAM Commands. RAS Conrol Sgnal: Ths sgnal s used wh S_CAS# and S_WE# (along wh S_CS#) o defne he SRAM Commands. CAS Conrol Sgnal: Ths sgnal s used wh S_RAS# and S_WE# (along wh S_CS#) o defne he SRAM Commands. Daa Srobes: S_DQS[7:0] and s complemen sgnal group make up a dfferenal srobe par. The daa s capured a he crossng pon of S_DQS[7:0] and s S_DQS#[7:0] durng read and wre ransacons. Daa us: Channel A daa sgnal nerface o he SDRAM daa bus. O O O O I/O I/O July 2014 Daashee Volume 1 of 2 Order No.:

74 Processors Sgnal Descrpon Sgnal Name Descrpon Drecon / uffer Type S_MA[15:0] S_CKP[1:0] S_CKN[1:0] S_CS#[1:0] S_CKE[3:0] Memory Address: These sgnals are used o provde he mulplexed row and column address o he SDRAM. SDRAM Dfferenal Clock: Channel SDRAM Dfferenal clock sgnal par. The crossng of he posve edge of S_CKP and he negave edge of s complemen S_CKN are used o sample he command and conrol sgnals on he SDRAM. Chp Selec: (1 per rank). These sgnals are used o selec parcular SDRAM componens durng he acve sae. There s one Chp Selec for each SDRAM rank. Clock Enable: (1 per rank). These sgnals are used o: Inalze he SDRAMs durng power-up Power down SDRAM ranks Place all SDRAM ranks no and ou of self-refresh durng STR When 1R DDR3L (SODIMM/MD) CKE[0] s used When 2R DDR3L (SODIMM/MD) CKE[1:0] are used O O O O S_ODT On De Termnaon: Acve Termnaon Conrol. O Table 28. LPDDR3 Memory Channel A Inerface (Memory-Down) Sgnals Sgnal Name Descrpon Drecon / uffer Type SA_DQ[63:0] SA_DQSP[7:0] SA_DQSN[7:0] SA_CAA[9:0] SA_CA[9:0] SA_CKP[1:0] SA_CKN[1:0] SA_CS#[1:0] SA_CKE[3:0] Daa us: Channel A daa sgnal nerface o he SDRAM daa bus. Daa Srobes: SA_DQS[7:0] and s complemen sgnal group make up a dfferenal srobe par. The daa s capured a he crossng pon of SA_DQS[7:0] and s SA_DQS#[7:0] durng read and wre ransacons. Command Address: These sgnals are used o provde he mulplexed command and address o he SDRAM. Command Address: These sgnals are used o provde he mulplexed command and address o he SDRAM. SDRAM Dfferenal Clock: Channel A SDRAM Dfferenal clock sgnal par. The crossng of he posve edge of SA_CKP and he negave edge of s complemen SA_CKN are used o sample he command and conrol sgnals on he SDRAM. Chp Selec: (1 per rank). These sgnals are used o selec parcular SDRAM componens durng he acve sae. There s one Chp Selec for each SDRAM rank. Clock Enable: (1 per rank). These sgnals are used o: Inalze he SDRAMs durng power-up Power down SDRAM ranks Place all SDRAM ranks no and ou of self-refresh durng STR When 1R LPDDR3 CKE[0] and CKE[2] are used for Rank 0 When 2R LPDDR3 CKE[0] and CKE[2] are used for Rank 0 & CKE[1] and CKE[3] are used for Rank 1 I/O I/O O O O O O SA_ODT On De Termnaon: Acve Termnaon Conrol. O Daashee Volume 1 of 2 July Order No.:

75 Sgnal Descrpon Processors Table 29. LPDDR3 Memory Channel Inerface (Memory-Down) Sgnals Sgnal Name Descrpon Drecon / uffer Type S_DQ[63:0] S_DQSP[7:0] S_DQSN[7:0] S_CAA[9:0] S_CA[9:0] S_CKP[1:0] S_CKN[1:0] S_CS#[1:0] S_CKE[3:0] Daa us: Channel A daa sgnal nerface o he SDRAM daa bus. Daa Srobes: S_DQS[7:0] and s complemen sgnal group make up a dfferenal srobe par. The daa s capured a he crossng pon of S_DQS[7:0] and s S_DQS#[7:0] durng read and wre ransacons. Command Address: These sgnals are used o provde he mulplexed command and address o he SDRAM. Command Address: These sgnals are used o provde he mulplexed command and address o he SDRAM. SDRAM Dfferenal Clock: Channel A SDRAM Dfferenal clock sgnal par. The crossng of he posve edge of S_CKP and he negave edge of s complemen S_CKN are used o sample he command and conrol sgnals on he SDRAM. Chp Selec: (1 per rank). These sgnals are used o selec parcular SDRAM componens durng he acve sae. There s one Chp Selec for each SDRAM rank. Clock Enable: (1 per rank). These sgnals are used o: Inalze he SDRAMs durng power-up Power down SDRAM ranks. Place all SDRAM no and ou of self-refresh durng STR. When 1R LPDDR3 CKE[0] and CKE[2] are used for Rank0 When 2R LPDDR3 CKE[0] and CKE[2] are used for Rank 0 and CKE[1] and CKE[3] are used for Rank 1 I/O I/O O O O O O S_ODT On De Termnaon: Acve Termnaon Conrol. O 6.2 Table 30. Memory Compensaon and Mscellaneous Sgnals LPDDR3 / DDR3L / DDR3L-RS Reference and Compensaon Sgnals Sgnal Name Descrpon Drecon / uffer Type SM_RCOMP[2:0] Sysem Memory Impedance Compensaon: I SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 SM_PG_CNTL1 Memory Channel A/ DIMM DQ Volage Reference: The oupu pns are conneced o he MD/DIMMs, and holds VDDQ/2 as reference volage. Sysem Memory Power Gae Conrol: Ths sgnal dsables he plaform memory VTT regulaor n C8 and deeper and S3 saes. O CMOS OUTPUT July 2014 Daashee Volume 1 of 2 Order No.:

76 Processors Sgnal Descrpon 6.3 Table 31. Rese and Mscellaneous Sgnals Rese and Mscellaneous Sgnals Sgnal Name Descrpon Drecon / uffer Type CFG[19:0] CFG_RCOMP FC_x IST_TRIGGER IVR_ERROR _TP _NCTF TESTLO_x Confguraon Sgnals: The CFG sgnals have a defaul value of '1' f no ermnaed on he board. CFG[2:0]: Reserved confguraon lane. A es pon may be placed on he board for hese lanes. CFG[3]: MSR Prvacy Feaure 1 = Debug capably s deermned by IA32_Debug_Inerface_MSR (C80h) b[0] seng 0 = IA32_Debug_Inerface_MSR (C80h) b[0] defaul seng overrdden CFG[4]: edp enable 1 = Dsabled 0 = Enabled CFG[19:5]: Reserved confguraon lanes. A es pon may be placed on he board for hese lands. Confguraon ressance compensaon. Use a 49.9 Ω ±1% ressor o ground. FC (Fuure Compably) sgnals are sgnals ha are avalable for compably wh oher processors. A es pon may be placed on he board for hese lands. Sgnal s for IFDIM esng only. Sgnal s for debug. If boh THERMTRIP# and hs sgnal are smulaneously assered, he processor has encounered an unrecoverable power delvery faul and has engaged auomac shudown as a resul. RESERVED: All sgnals ha are and _NCTF mus be lef unconneced on he board. Inel recommends ha all _TP sgnals have va es pons. TESTLO should be ndvdually conneced o V SS hrough a ressor. I/O GTL I CMOS O CMOS No Connec Tes Pon Non-Crcal o Funcon Daashee Volume 1 of 2 July Order No.:

77 Sgnal Descrpon Processors 6.4 Table 32. embedded DsplayPor* (edp*) Sgnals embedded Dsplay Por* Sgnals Sgnal Name Descrpon Drecon / uffer Type edp_txp[3:0] edp_txn[3:0] edp_auxp edp_auxn edp_rcomp edp_disp_util embedded DsplayPor Transm Dfferenal Par embedded DsplayPor Auxlary Dfferenal Par embedded DsplayPor Curren Compensaon Low volage mulpurpose DISP_UTIL pn on he processor for backlgh modulaon conrol of embedded panels and S3D devce conrol for acve shuer glasses. Ths pn wll co-exs wh funconaly smlar o exsng KLTCTL pn on he PCH. O edp O edp I/O A O Asynchronous CMOS 6.5 Table 33. Dsplay Inerface Sgnals Dsplay Inerface Sgnals Sgnal Name Descrpon Drecon / uffer Type DDI_TXP[3:0] DDI_TXN[3:0] DDIC_TXP[3:0] DDIC_TXN[3:0] Dgal Dsplay Inerface Transm Dfferenal Par Dgal Dsplay Inerface Transm Dfferenal Par O DP*/HDMI* O DP*/HDMI* 6.6 Table 34. Tesably Sgnals Tesably Sgnals Sgnal Name Descrpon Drecon / uffer Type PM#[7:0] PRDY# PREQ# PROC_TCK PROC_TDI reakpon and Performance Monor Sgnals: Oupus from he processor ha ndcae he saus of breakpons and programmable couners used for monorng processor performance. Processor Ready: Ths sgnal s a processor oupu used by debug ools o deermne processor debug readness. Processor Reques: Ths sgnal s used by debug ools o reques debug operaon of he processor. Tes Clock: Ths sgnal provdes he clock npu for he processor Tes us (also known as he Tes Access Por). Ths sgnal mus be drven low or allowed o floa durng power on Rese. Processor Tes Daa In: Ths sgnal ransfers seral es daa no he processor. Ths sgnal provdes he seral npu needed for JTAG specfcaon suppor. I/O GTL O GTL I GTL I GTL I GTL July 2014 Daashee Volume 1 of 2 Order No.:

78 Processors Sgnal Descrpon Sgnal Name Descrpon Drecon / uffer Type PROC_TDO PROC_TMS PROC_TRST# Processor Tes Daa Ou: Ths sgnal ransfers seral es daa ou of he processor. Ths sgnal provdes he seral oupu needed for JTAG specfcaon suppor. Processor Tes Mode Selec: Ths s a JTAG specfcaon suppored sgnal used by debug ools. Processor Tes Rese: Ths sgnal reses he Tes Access Por (TAP) logc. Ths sgnal mus be drven low durng power on Rese. O Open Dran I GTL I GTL 6.7 Table 35. Error and Thermal Proecon Sgnals Error and Thermal Proecon Sgnals Sgnal Name Descrpon Drecon / uffer Type CATERR# PECI PROCHOT# THERMTRIP# Caasrophc Error: Ths sgnal ndcaes ha he sysem has experenced a caasrophc error and canno connue o operae. The processor wll se hs for non-recoverable machne check errors or oher unrecoverable nernal errors. CATERR# s used for sgnalng he followng ypes of errors: Legacy MCERRs, CATERR# s assered for 16 CLKs. Legacy IERRs, CATERR# remans assered unl warm or cold rese. Plaform Envronmen Conrol Inerface: A seral sdeband nerface o he processor, s used prmarly for hermal, power, and error managemen. Processor Ho: PROCHOT# goes acve when he processor emperaure monorng sensor(s) deecs ha he processor has reached s maxmum safe operang emperaure. Ths ndcaes ha he processor Thermal Conrol Crcu (TCC) has been acvaed, f enabled. Ths sgnal can also be drven o he processor o acvae he TCC. Thermal Trp: The processor proecs self from caasrophc overheang by use of an nernal hermal sensor. Ths sensor s se well above he normal operang emperaure o ensure ha here are no false rps. The processor wll sop all execuon when he juncon emperaure exceeds approxmaely 130 C. Ths s sgnaled o he sysem by he THERMTRIP# pn. O GTL I/O Asynchronous GTL Inpu Open-Dran Oupu O Asynchronous OD Daashee Volume 1 of 2 July Order No.:

79 Sgnal Descrpon Processors 6.8 Table 36. Power Sequencng Sgnals Power Sequencng Sgnals Sgnal Name Descrpon Drecon / uffer Type PROCPWRGD ST_PWRGD PROC_DETECT# The processor requres hs npu sgnal o be a clean ndcaon ha he V CC and V DDQ power supples are sable and whn specfcaons. Ths requremen apples regardless of he S-sae of he processor. 'Clean' mples ha he sgnal wll reman low (capable of snkng leakage curren), whou glches, from he me ha he power supples are urned on unl he supples come whn specfcaon. The sgnal mus hen ranson monooncally o a hgh sae. The processor requres hs npu sgnal o be a clean ndcaon ha he V CCST and V DDQ power supples are sable and whn specfcaons. Ths sngle mus have a vald level durng boh S0 and S3 power saes. 'Clean' mples ha he sgnal wll reman low (capable of snkng leakage curren), whou glches, from he me ha he power supples are urned on unl he supples come whn specfcaon. The sgnal mus hen ranson monooncally o a hgh sae." (Processor Deec): Ths sgnal s pulled down drecly (0 Ohms) on he processor package o ground. There s no connecon o he processor slcon for hs sgnal. Sysem board desgners may use hs sgnal o deermne f he processor s presen. I Asynchronous CMOS I Asynchronous CMOS 6.9 Table 37. Processor Power Sgnals Processor Power Sgnals Sgnal Name Descrpon Drecon / uffer Type Processor man power ral. Ref VDDQ Processor I/O supply volage for DDR3L/DDR3L-RS/ LPDDR3. Ref ST Susan volage for he processor n sandby modes Ref VIDSOUT VIDSCLK VIDALERT# VR_EN VR_READY VIDALERT#, VIDSCLK, and VIDSCLK comprse a hree sgnal seral synchronous nerface used o ransfer power managemen nformaon beween he processor and he volage regulaor conrollers. Sdeband oupu from he processor whch conrols dsablng of he VR when he processor s n he C10 sae. Ths sgnal wll be used o dsable he VR only f he processor s confgured o suppor VR dsablng usng VR_CURRENT_CONFIG MSR (601h). Sdeband sgnal whch ndcaes o he processor ha he exernal volage regulaor for he V CC power ral s vald. I/O CMOS O CMOS I CMOS O VR Enable CMOS I CMOS July 2014 Daashee Volume 1 of 2 Order No.:

80 Processors Sgnal Descrpon 6.10 Table 38. Sense Sgnals Sense Sgnals Sgnal Name Descrpon Drecon / uffer Type _SENSE _SENSE _SENSE and _SENSE provde an solaed, lowmpedance connecon o he processor npu V CC volage and ground. The sgnals can be used o sense or measure volage near he slcon. O A 6.11 Table 39. Ground and Non-Crcal o Funcon (NCTF) Sgnals Ground and Non-Crcal o Funcon (NCTF) Sgnals Sgnal Name Descrpon Drecon / uffer Type Processor ground node GND _NCTF DAISY_CHAIN_NCTF_[all #] Non-Crcal o Funcon: These sgnals are for package mechancal relably. Dasy Chan Non-Crcal o Funcon: These sgnals are for GA solder jon relably esng and are non-crcal o funcon. These sgnals are conneced on he processor package as follows: Package A1 Corner DAISY_CHAIN_NCTF_2 o DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_C2 o DAISY_CHAIN_NCTF_3 DAISY_CHAIN_NCTF_A3 o DAISY_CHAIN_NCTF_A4 Package A63 Corner DAISY_CHAIN_NCTF_A62 o DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_61 o DAISY_CHAIN_NCTF_62 DAISY_CHAIN_NCTF_63 o DAISY_CHAIN_NCTF_A60 Package AY1 Corner DAISY_CHAIN_NCTF_AW1 o DAISY_CHAIN_NCTF_AW3 DAISY_CHAIN_NCTF_AY3 o DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AY2 o DAISY_CHAIN_NCTF_AV1 Package AY63 Corner DAISY_CHAIN_NCTF_AY60 o DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AY61 o DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AY62 o DAISY_CHAIN_NCTF_AW Table 40. Processor Inernal Pull-Up / Pull-Down Termnaons Processor Inernal Pull-Up / Pull-Down Termnaons Sgnal Name Pull Up / Pull Down Ral Value PM[7:0] Pull Up Vcc IO Ω PREQ# Pull Up Vcc IO Ω PROC_TDI Pull Up Vcc ST Ω Daashee Volume 1 of 2 July Order No.:

81 Sgnal Descrpon Processors Sgnal Name Pull Up / Pull Down Ral Value PROC_TMS Pull Up Vcc ST Ω CFG[19:0] Pull Up Vcc ST 5 8 kω CATERR# Pull Up Vcc ST Ω July 2014 Daashee Volume 1 of 2 Order No.:

82 Processors Elecrcal Specfcaons 7.0 Elecrcal Specfcaons Ths chaper provdes he processor elecrcal specfcaons ncludng negraed volage regulaor (VR), V CC Volage Idenfcaon (VID), reserved and unused sgnals, sgnal groups, Tes Access Pons (TAP), and DC specfcaons. 7.1 Inegraed Volage Regulaor A new feaure o he processor s he negraon of plaform volage regulaors no he processor. Due o hs negraon, he processor has one man volage ral (V CC ) and a volage ral for he memory nerface (V DDQ ), compared o sx volage rals on prevous processors. The V CC volage ral wll supply he negraed volage regulaors whch n urn wll regulae o he approprae volages for he cores, cache, sysem agen, and graphcs. Ths negraon allows he processor o beer conrol on-de volages o opmze beween performance and power savngs. The processor V CC ral wll reman a VID-based volage wh a loadlne smlar o he core volage ral (also called V CC ) n prevous processors. 7.2 Power and Ground Pns The processor has, VDDQ, and (ground) pns for on-chp power dsrbuon. All power pns mus be conneced o her respecve processor power planes; all pns mus be conneced o he sysem ground plane. Use of mulple power and ground planes s recommended o reduce I*R drop. The pns mus be suppled wh he volage deermned by he processor Seral Volage IDenfcaon (SVID) nerface. Table 41 on page 83 specfes he volage level for he varous VIDs. 7.3 V CC Volage Idenfcaon (VID) The processor uses hree sgnals for he seral volage denfcaon nerface o suppor auomac selecon of volages. The followng able specfes he volage level correspondng o he 8-b VID value ransmed over seral VID. A 1 n hs able refers o a hgh volage level and a 0 refers o a low volage level. If he volage regulaon crcu canno supply he volage ha s requesed, he volage regulaor mus dsable self. VID sgnals are CMOS push/pull drvers. See he Volage and Curren Specfcaons secon for he DC specfcaons for hese sgnals. The VID codes wll change due o emperaure and/or curren load changes o mnmze he power of he par. A volage range s provded n he Volage and Curren Specfcaons secon. The specfcaons are se so ha one volage regulaor can operae wh all suppored frequences. Indvdual processor VID values may be se durng manufacurng so ha wo devces a he same core frequency may have dfferen defaul VID sengs. Ths s shown n he VID range values n he Volage and Curren Specfcaons secon. The processor provdes he ably o operae whle ransonng o an adjacen VID and s assocaed volage. Ths wll represen a DC shf n he loadlne. Daashee Volume 1 of 2 July Order No.:

83 Elecrcal Specfcaons Processors Table 41. Volage Regulaor (VR) 12.5 Volage Idenfcaon Hex V CC Hex V CC h h h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh h h July 2014 Daashee Volume 1 of 2 Order No.:

84 Processors Elecrcal Specfcaons Hex V CC Hex V CC h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh h h h h h h Daashee Volume 1 of 2 July Order No.:

85 Elecrcal Specfcaons Processors Hex V CC Hex V CC h h h h Ah h Ch Dh Eh Fh h h h h h h h h h h Ah h Ch Dh Eh Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh Ah ACh ADh AEh AFh h h h h h h h h h h Ah h Ch Dh Eh Fh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h July 2014 Daashee Volume 1 of 2 Order No.:

86 Processors Elecrcal Specfcaons Hex V CC Hex V CC CAh Ch CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh Dh DCh DDh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh Fh FCh FDh FEh FFh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh Eh Daashee Volume 1 of 2 July Order No.:

87 Elecrcal Specfcaons Processors 7.4 Reserved or Unused Sgnals The followng are he general ypes of reserved () sgnals and connecon gudelnes: hese sgnals should no be conneced _TP hese sgnals should be roued o a es pon _NCTF hese sgnals are non-crcal o funcon and may be lef unconneced Arbrary connecon of hese sgnals o, VDDQ,, or o any oher sgnal (ncludng each oher) may resul n componen malfuncon or ncompably wh fuure processors. See Sgnal Descrpon on page 72 for a pn lsng of he processor and he locaon of all reserved sgnals. For relable operaon, always connec unused npus or b-dreconal sgnals o an approprae sgnal level. Unused acve hgh npus should be conneced hrough a ressor o ground (). Unused oupus maybe lef unconneced; however, hs may nerfere wh some Tes Access Por (TAP) funcons, complcae debug probng, and preven boundary scan esng. A ressor mus be used when yng b-dreconal sgnals o power or ground. When yng any sgnal o power or ground, a ressor wll also allow for sysem esably. 7.5 Sgnal Groups Sgnals are grouped by buffer ype and smlar characerscs as lsed n he followng able. The buffer ype ndcaes whch sgnalng echnology and specfcaons apply o he sgnals. All he dfferenal sgnals and seleced DDR3L/DDR3L-RS/LPDDR3 and Conrol Sdeband sgnals have On-De Termnaon (ODT) ressors. Some sgnals do no have ODT and need o be ermnaed on he board. Noe: Table 42. All Conrol Sdeband Asynchronous sgnals are requred o be assered/de-assered for a leas 10 CLKs wh maxmum Trse/Tfall of 6 ns for he processor o recognze he proper sgnal sae. See he DC Specfcaons secon and AC Specfcaons secon. Sgnal Groups Sgnal Group Type Sgnals DDR3L / DDR3L-RS / LPDDR3 Reference Clocks 2 Dfferenal DDR3L/DDR3L-RS/ LPDDR3 Oupu SA_CKP[1:0], SA_CKN[1:0], S_CKP[1:0], S_CKN[1:0] DDR3L / DDR3L-RS/LPDDR3 Command Sgnals 2 Sngle ended DDR3L/DDR3L-RS/ LPDDR3 Oupu DDR3L/DDR3L-RS Mode SA_S2, S_S2 LPDDR3 Mode SA_CAA5, S_CAA5 SA_S1, S_S1 SA_CA6, S_CA6 SA_S0, S_S0 SA_CA4, S_CA4 SA_WE#, S_WE# SA_CA2, S_CA2 SA_RAS#, S_RAS# SA_CA3, S_CA3 SA_CAS#, S_CAS# SA_CA1, S_CA1 July 2014 Daashee Volume 1 of 2 Order No.:

88 Processors Elecrcal Specfcaons Sgnal Group Type Sgnals SA_MA15, S_MA15 SA_MA14, S_MA14 SA_MA13, S_MA13 SA_MA12, S_MA12 SA_MA11, S_MA11 SA_MA10, S_MA10 SA_MA9, S_MA9 SA_MA8, S_MA8 SA_MA7, S_MA7 SA_MA6, S_MA6 SA_MA5, S_MA5 SA_MA4, S_MA4 SA_MA3, S_MA3 SA_MA2, S_MA2 SA_MA1, S_MA1 SA_MA0, S_MA0 SA_CAA8, S_CAA8 SA_CAA9, S_CAA9 SA_CA0, S_CA0 SA_CAA6, S_CAA6 SA_CAA7, S_CAA7 SA_CA7, S_CA7 SA_CAA1, S_CAA1 SA_CAA3, S_CAA3 SA_CAA4, S_CAA4 SA_CAA2, S_CAA2 SA_CAA0, S_CAA0 N/A N/A SA_CA5, S_CA5 SA_CA8, S_CA8 SA_CA9, S_CA9 DDR3L / DDR3L-RS Conrol Sgnals 2 Sngle ended DDR3L/DDR3L-RS Oupu SA_CKE[3:0], S_CKE[3:0], SA_CS#[1:0], S_CS#[1:0], SA_ODT0, S_ODT0, SM_PG_CNTL1 DDR3L / DDR3L-RS Daa Sgnals 2 Sngle ended Dfferenal DDR3L/DDR3L-RS -dreconal DDR3L/DDR3L-RS -dreconal SA_DQ[63:0], S_DQ[63:0] SA_DQSP[7:0], SA_DQSN[7:0], S_DQSP[7:0], S_DQSN[7:0] DDR3L / DDR3L-RS Reference Volage Sgnals DDR3L/DDR3L-RS Oupu SM_VREF_CA, SM_VREF_DQ1, SM_VREF_DQ0 Tesably (ITP/XDP) Sngle ended GTL Inpu PROC_TCK, PROC_TDI, PROC_TMS, PROC_TRST# Sngle ended GTL PROC_TDO Sngle ended GTL PM#[7:0] Sngle ended GTL PREQ# Sngle ended GTL PRDY# Conrol Sdeband Sngle ended Sngle ended GTL Inpu/Open Dran Oupu Asynchronous CMOS Oupu PROCHOT# IVR_ERROR Sngle ended Open Dran Oupu THERMTRIP# Daashee Volume 1 of 2 July Order No.:

89 Elecrcal Specfcaons Processors Sgnal Group Type Sgnals Sngle ended GTL CATERR# Sngle ended Sngle ended Asynchronous CMOS Inpu Asynchronous dreconal RESET#, PROCPWRGD, PWR_DEUG#, ST_PWRGD PECI Sngle ended GTL -dreconal CFG[19:0] Volage Regulaor Sngle ended VR Enable CMOS Oupu VR_EN Sngle ended CMOS Inpu VR_READY Sngle ended CMOS Inpu VIDALERT# Sngle ended Open Dran Oupu VIDSCLK Sngle ended CMOS I/O VIDSOUT Dfferenal Analog Oupu _SENSE, _SENSE Power / Ground / Oher Sngle ended Power, VDDQ, ST Ground, _NCTF 3 No Connec Tes Pon, _NCTF _TP Dgal Dsplay Inerface Oher DAISY_CHAIN_NCTF_[ball #] Dfferenal DDI Oupu DDI_TXP[3:0], DDI_TXN[3:0], DDIC_TXP[3:0], DDIC_TXN[3:0]] Noes: 1. See Sgnal Descrpon on page 72 for sgnal descrpon deals. 2. SA and S refer o DDR3L/DDR3L-RS Channel A and DDR3L/DDR3L-RS Channel. 7.6 Tes Access Por (TAP) Connecon Due o he volage levels suppored by oher componens n he Tes Access Por (TAP) logc, Inel recommends he processor be frs n he TAP chan, followed by any oher componens whn he sysem. A ranslaon buffer should be used o connec o he res of he chan unless one of he oher componens s capable of accepng an npu of he approprae volage. Two copes of each sgnal may be requred wh each drvng a dfferen volage level. The processor suppors oundary Scan (JTAG) IEEE and IEEE sandards. A few of he I/O pns may suppor only one of hose sandards. 7.7 DC Specfcaons The processor DC specfcaons n hs secon are defned a he processor pns, unless noed oherwse. See Sgnal Descrpon on page 72 for he processor pn lsngs and sgnal defnons. July 2014 Daashee Volume 1 of 2 Order No.:

90 Processors Elecrcal Specfcaons The DC specfcaons for he DDR3L/DDR3L-RS/LPDDR3 sgnals are lsed n he Volage and Curren Specfcaons secon. The Volage and Curren Specfcaons secon lss he DC specfcaons for he processor and are vald only whle meeng specfcaons for juncon emperaure, clock frequency, and npu volages. Read all noes assocaed wh each parameer. AC olerances for all DC rals nclude dynamc load currens a swchng frequences up o 1 MHz. 7.8 Table 43. Volage and Curren Specfcaons Processor Core Acve and Idle Mode DC Volage and Curren Specfcaons Symbol Parameer Segmen Mn Typ Max Un Noe 1 Operang Volage Idle Volage Volage Range for Processor Acve Operang Mode Volage Range for Processor Idle Mode (Package C6/C7) All V 1, 2, 7 All V 1, 2, 7 U- Processors 28W 40 I CCMAX Maxmum Processor Core I CC U- Processors 15W 32 A 4, 6, 7 Y-Processors 11.5W (6W SDP / 4.5W SDP) 25 TOL Volage Tolerance PS0, PS1 ±20 PS2, PS3 ±20 mv 6, 8 PS0 ±15 Rpple Rpple Tolerance PS1 ±15 PS2 +50/-15 mv 6, 8 PS3 +60/-15 R_DC_LL R_AC_LL Loadlne slope whn he VR regulaon loop capably Loadlne slope n response o dynamc load ncrease evens mv mω Daashee Volume 1 of 2 July Order No.:

91 Elecrcal Specfcaons Processors Symbol Parameer Segmen Mn Typ Max Un Noe 1 T_OVS_Max Max Overshoo me 500 μs V_OVS Max Overshoo 200 mv Noes: 1. Unless oherwse noed, all specfcaons n hs able are based on esmaes and smulaons or emprcal daa. 2. Each processor s programmed wh a maxmum vald volage denfcaon value (VID) ha s se a manufacurng and canno be alered. Indvdual maxmum VID values are calbraed durng manufacurng such ha wo processors a he same frequency may have dfferen sengs whn he VID range. Noe ha hs dffers from he VID employed by he processor durng a power managemen even (Adapve Thermal Monor, Enhanced Inel SpeedSep Technology, or Low-Power Saes). 3. The volage specfcaon requremens are measured across _SENSE and _SENSE lands a he socke wh a 20 MHz bandwdh osclloscope, 1.5 pf maxmum probe capacance, and 1 MΩ mnmum mpedance. The maxmum lengh of ground wre on he probe should be less han 5 mm. Ensure exernal nose from he sysem s no coupled no he osclloscope probe. 4. Processor core VR o be desgned o elecrcally suppor hs curren. 5. Processor core VR o be desgned o hermally suppor hs curren ndefnely. 6. Long erm relably canno be assured f olerance, rpple, and core nose parameers are volaed. 7. Long erm relably canno be assured n condons above or below Maxmum/Mnmum funconal lms. 8. PSx refers o he volage regulaor power sae as se by he SVID proocol. Table 44. Memory Conroller (V DDQ ) Supply DC Volage and Curren Specfcaons Symbol Parameer Mn Typ Max Un Noe V DDQ (DDR3L/DDR3L-RS) V DDQ (LPDDR3) Processor I/O supply volage for DDR3L/DDR3L- RS Processor I/O supply volage for LPDDR V 2, V 2, 3 TOL DDQ VDDQ Tolerance (AC+DC) -5 5 % 2, 3 Icc MAX_VDDQ (DDR3L/ DDR3L-RS) Icc MAX_VDDQ (LPDDR3) Max Curren for V DDQ Ral (DDR3L/DDR3L-RS) Max Curren for V DDQ Ral (LPDDR3) 1.4 A A 1 Noes: 1. The curren suppled o he DIMM modules s no ncluded n hs specfcaon. 2. Includes AC and DC error, where he AC nose s bandwdh lmed o under 20 MHz. 3. No requremen on he breakdown of AC versus DC nose. Table 45. Vcc Susan (Vcc ST ) Supply DC Volage and Curren Specfcaons Symbol Parameer Mn Typ Max Uns Noes Vcc ST Processor Vcc Susan supply volage - 5% % V Icc MAX_VccST Maxmum Curren for Vcc ST 100 ma July 2014 Daashee Volume 1 of 2 Order No.:

92 Processors Elecrcal Specfcaons Table 46. DDR3L / DDR3L-RS Sgnal Group DC Specfcaons Symbol Parameer Mn Typ Max Uns Noes 1 V IL Inpu Low Volage V DDQ /2 0.43*V DDQ V 2, 4, 11 V IH Inpu Hgh Volage 0.57*V DDQ V DDQ /2 V 3, 11 V IL V IH R ON_UP(DQ) R ON_DN(DQ) R ODT(DQ) V ODT(DC) Inpu Low Volage (SM_DRAMPWROK) Inpu Hgh Volage (SM_DRAMPWROK) DDR3L/DDR3L-RS Daa uffer pull-up Ressance DDR3L/DDR3L-RS Daa uffer pull-down Ressance DDR3L/DDR3L-RS Onde ermnaon equvalen ressance for daa sgnals DDR3L/DDR3L-RS Onde ermnaon DC workng pon (drver se o receve mode) 0.15*V DDQ V 0.45*V DDQ 1.0 V 10, Ω 5, Ω 5, Ω *V DDQ 0.5*V DDQ 0.55*V DDQ V 11 R ON_UP(CK) DDR3L/DDR3L-RS Clock uffer pull-up Ressance Ω 5, 11, 13 R ON_DN(CK) DDR3L/DDR3L-RS Clock uffer pull-down Ressance Ω 5, 11, 13 R ON_UP(CMD) DDR3L/DDR3L-RS Command uffer pullup Ressance Ω 5, 11, 13 R ON_DN(CMD) DDR3L/DDR3L-RS Command uffer pulldown Ressance Ω 5, 11, 13 R ON_UP(CTL) DDR3L/DDR3L-RS Conrol uffer pull-up Ressance Ω 5, 11, 13 R ON_DN(CTL) DDR3L/DDR3L-RS Conrol uffer pull-down Ressance Ω 5, 11, 13 R ON_UP(SM_PG_CNTL1) R ON_DN(SM_PG_CNTL1) I LI Sysem Memory Power Gae Conrol uffer Pull-Up Ressance Sysem Memory Power Gae Conrol uffer Pull-Down Ressance Inpu Leakage Curren (DQ, CK) 0V 0.2*V DDQ 0.8*V DDQ Ω Ω ma Daashee Volume 1 of 2 July Order No.:

93 Elecrcal Specfcaons Processors Symbol Parameer Mn Typ Max Uns Noes 1 I LI SM_RCOMP0 Inpu Leakage Curren (CMD, CTL) 0V 0.2*V DDQ 0.8*V DDQ Command COMP Ressance 1.0 ma Ω 8 SM_RCOMP1 Daa COMP Ressance Ω 8 SM_RCOMP2 ODT COMP Ressance Ω 8 Noes: 1. Unless oherwse noed, all specfcaons n hs able apply o all processor frequences. 2. V IL s defned as he maxmum volage level a a recevng agen ha wll be nerpreed as a logcal low value. 3. V IH s defned as he mnmum volage level a a recevng agen ha wll be nerpreed as a logcal hgh value. 4. V IH and V OH may experence excursons above V DDQ. However, npu sgnal drvers mus comply wh he sgnal qualy specfcaons. 5. Ths s he pull up/down drver ressance. 6. R TERM s he ermnaon on he DIMM and n no conrolled by he processor. 7. The mnmum and maxmum values for hese sgnals are programmable by IOS o one of he wo ses. 8. SM_RCOMPx ressance mus be provded on he sysem board wh 1% ressors. SM_RCOMPx ressors are o V SS. 9. SM_DRAMPWROK rse and fall me mus be < 50 ns measured beween V DDQ *0.15 and V DDQ * SM_VREF s defned as V DDQ /2. 11.Maxmum-mnmum range s correc; however, cener pon s subjec o change durng MRC boo ranng. 12.Processor may be damaged f V IH exceeds he maxmum volage for exended perods. 13.The MRC durng boo ranng mgh opmze R ON ousde he range specfed. Table 47. LPDDR3 Sgnal Group DC Specfcaons Symbol Parameer Mn Typ. Max Un Noe V IL Inpu Low Volage V DDQ /2 0.43*V DDQ V 2, 4, 12 V IH Inpu Hgh Volage 0.57*V DDQ V DDQ /2 V 3, 11 V IL V IH R ON_UP(DQ) R ON_DN(DQ) R ODT(DQ) V ODT(DC) R ON_UP(CK) Inpu Low Volage (SM_DRAMPWROK) Inpu Hgh Volage (SM_DRAMPWROK) LPDDR3 Daa uffer pullup Ressance LPDDR3 Daa uffer pulldown Ressance LPDDR3 On-de ermnaon equvalen ressance for daa sgnals LPDDR3 On-de ermnaon DC workng pon (drver se o receve mode) LPDDR3 Clock uffer pullup Ressance 0.15*V DDQ V 0.45*V DDQ 1.0*V DDQ V 10, Ω 5, Ω 5, Ω *V DDQ 0.5*V DDQ 0.55*V DDQ V Ω 5, 11 July 2014 Daashee Volume 1 of 2 Order No.:

94 Processors Elecrcal Specfcaons Symbol Parameer Mn Typ. Max Un Noe R ON_DN(CK) R ON_UP(CMD) R ON_DN(CMD) R ON_UP(CTL) R ON_DN(CTL) R ON_UP(RST) R ON_DN(RST) I LI I LI LPDDR3 Clock uffer pulldown Ressance LPDDR3 Command uffer pull-up Ressance LPDDR3 Command uffer pull-down Ressance LPDDR3 Conrol uffer pull-up Ressance LPDDR3 Conrol uffer pull-down Ressance LPDDR3 Rese uffer pullup Ressance LPDDR3 Rese uffer pullup Ressance Inpu Leakage Curren (DQ, CK) 0V 0.2* V DDQ 0.8*V DDQ Inpu Leakage Curren (CMD,CTL) 0V 0.2*V DDQ 0.8*V DDQ Ω 5, Ω 5, Ω 5, Ω 5, Ω 5, Ω Ω 0.4 ma 0.6 ma SM_RCOMP0 ODT COMP Ressance Ω 8 SM_RCOMP1 Daa COMP Ressance Ω 8 SM_RCOMP2 Command COMP Ressance Ω 8 Noes: 1. Unless oherwse noed, all specfcaons n hs able apply o all processor frequences. 2. V IL s defned as he maxmum volage level a a recevng agen ha wll be nerpreed as a logcal low value. 3. V IH s defned as he mnmum volage level a a recevng agen ha wll be nerpreed as a logcal hgh value. 4. V IH and V OH may experence excursons above V DDQ. However, npu sgnal drvers mus comply wh he sgnal qualy specfcaons. 5. Ths s he pull up/down drver ressance. 6. RTERM s he ermnaon on he DIMM and n no conrolled by he processor. 7. The mnmum and maxmum values for hese sgnals are programmable by IOS o one of he wo ses. 8. SM_RCOMPx ressance mus be provded on he sysem board wh 1% ressors. SM_RCOMPx ressors are o V SS. 9. SM_DRAMPWROK mus have a maxmum of 15 ns rse or fall me over V DDQ * 0.30 ±100 mv and he edge mus be monoonc. 10.SM_VREF s defned as V DDQ /2 11.Maxmum-mnmum range s correc; however, cener pon s subjec o change durng MRC boo ranng. 12.Processor may be damaged f V IH exceeds he maxmum volage for exended perods. Daashee Volume 1 of 2 July Order No.:

95 Elecrcal Specfcaons Processors Table 48. Dgal Dsplay Inerface Group DC Specfcaons Symbol Parameer Mn Typ Max Uns V IL HPD Inpu Low Volage 0.8 V V IH HPD Inpu Hgh Volage V Vaux(Tx) Vaux(Rx) Aux peak-o-peak volage a ransmng devce Aux peak-o-peak volage a recevng devce V V Table 49. embedded DsplayPor* (edp*) Group DC Specfcaons Symbol Parameer Mn Typ Max Uns V OL edp_disp_util Oupu Low Volage 0.1*V CC V V OH edp_disp_util Oupu Hgh Volage 0.9*V CC V R UP edp_disp_util Inernal pull-up 100 Ω R DOWN edp_disp_util Inernal pull-down 100 Ω Vaux(Tx) Vaux(Rx) Aux peak-o-peak volage a ransmng devce Aux peak-o-peak volage a recevng devce V V edp_rcomp COMP Ressance Ω Noe: 1. COMP ressance s o VCOMP_OUT. Table 50. CMOS Sgnal Group DC Specfcaons Symbol Parameer Mn Max Uns Noes 1 V IL Inpu Low Volage Vcc ST * 0.3 V 2 V IH Inpu Hgh Volage Vcc ST * 0.7 V 2, 4 V OL Oupu Low Volage Vcc ST * 0.1 V 2 V OH Oupu Hgh Volage Vcc ST * 0.9 V 2, 4 R ON uffer on Ressance Ω I LI Inpu Leakage Curren ±150 μa 3 Noes: 1. Unless oherwse noed, all specfcaons n hs able apply o all processor frequences. 2. The Vcc ST referred o n hese specfcaons refers o nsananeous IO_OUT. 3. For VIN beween 0 V and Vcc ST. Measured when he drver s r-saed. 4. V IH and V OH may experence excursons above Vcc ST. However, npu sgnal drvers mus comply wh he sgnal qualy specfcaons. Table 51. GTL Sgnal Group and Open Dran Sgnal Group DC Specfcaons Symbol Parameer Mn Max Uns Noes 1 V IL V IH Inpu Low Volage (TAP, excep PROC_TCK, PROC_TRST#) Inpu Hgh Volage (TAP, excep PROC_TCK, PROC_TRST#) Vcc ST * 0.6 V 2 Vcc ST * 0.72 V 2, 4 July 2014 Daashee Volume 1 of 2 Order No.:

96 Processors Elecrcal Specfcaons Symbol Parameer Mn Max Uns Noes 1 V IL V IH Inpu Low Volage (PROC_TCK, PROC_TRST#) Inpu Hgh Volage (PROC_TCK, PROC_TRST#) Vcc ST * 0.3 V 2 Vcc ST * 0.7 V 2, 4 V HYSTERESIS Hyseress Volage Vcc ST * 0.2 V R ON uffer on Ressance (TDO) 7 17 Ω V IL Inpu Low Volage (oher GTL) Vcc ST * 0.6 V 2 V IH Inpu Hgh Volage (oher GTL) Vcc ST * 0.72 V 2, 4 R ON uffer on Ressance (CFG/PM) Ω R ON uffer on Ressance (oher GTL) Ω I LI Inpu Leakage Curren ±150 μa 3 Noes: 1. Unless oherwse noed, all specfcaons n hs able apply o all processor frequences. 2. The Vcc ST referred o n hese specfcaons refers o nsananeous Vcc ST. 3. For VIN beween 0 V and Vcc ST. Measured when he drver s r-saed. 4. V IH and V OH may experence excursons above Vcc ST. However, npu sgnal drvers mus comply wh he sgnal qualy specfcaons. Table 52. VR Enable CMOS Sgnal Group DC Specfcaon Symbol Parameer Mn Max Uns Noes R ON uffer on Ressance Ω V HYSTERESIS Hyseress Volage 0.15* Vcc ST V Table 53. VCOMP_OUT and IO_TERM Symbol Parameer Typ Max Uns Noes VCOMP_OUT Termnaon Volage 1.0 V 1 IO_TERM Termnaon Volage 1.0 V 2 Noes: 1. VCOMP_OUT may only be used o connec edp_rcomp. 2. Inernal processor power for sgnal ermnaon Plaform Envronmen Conrol Inerface (PECI) DC Characerscs The PECI nerface operaes a a nomnal volage se by Vcc ST. The se of DC elecrcal specfcaons shown n he followng able s used wh devces normally operang from a Vcc ST nerface supply. Vcc ST nomnal levels wll vary beween processor famles. All PECI devces wll operae a he Vcc ST level deermned by he processor nsalled n he sysem. Table 54. Plaform Envronmen Conrol Inerface (PECI) DC Elecrcal Lms Symbol Defnon and Condons Mn Max Uns Noes 1 R up Inernal pull up ressance Ω 3 V n Inpu Volage Range Vcc ST V Daashee Volume 1 of 2 July Order No.:

97 Elecrcal Specfcaons Processors Symbol Defnon and Condons Mn Max Uns Noes 1 V hyseress Hyseress 0.1 * Vcc ST N/A V V n V p Negave-Edge Threshold Volage Posve-Edge Threshold Volage * Vcc ST * Vcc ST V * Vcc ST * Vcc ST V C bus us Capacance per Node N/A 10 pf C pad Pad Capacance pf Ileak000 leakage curren a 0 V 0.6 ma Ileak025 Ileak050 Ileak075 leakage curren a 0.25* Vcc ST 0.4 ma leakage curren a 0.50* Vcc ST 0.2 ma leakage curren a 0.75* Vcc ST 0.13 ma Ileak100 leakage curren a Vcc ST 0.10 ma Noes: 1. Vcc ST supples he PECI nerface. PECI behavor does no affec Vcc ST mnmum / maxmum specfcaons. 2. The leakage specfcaon apples o powered devces on he PECI bus. 3. The PECI buffer nernal pull-up ressance measured a 0.75* Vcc ST Inpu Devce Hyseress The npu buffers n boh clen and hos models mus use a Schm-rggered npu desgn for mproved nose mmuny. Use he followng fgure as a gude for npu buffer desgn. Fgure 13. Inpu Devce Hyseress V TTD Maxmum V P PECI Hgh Range Mnmum V P Maxmum V N Mnmum Hyseress Vald Inpu Sgnal Range Mnmum V N PECI Low Range PECI Ground July 2014 Daashee Volume 1 of 2 Order No.:

98 Processors Package Specfcaons 8.0 Package Specfcaons 8.1 Package Mechancal Arbues The U-Processor Lne and Y-Processor Lne use a Flp Chp echnology and Mul-Chp package (MCP) avalable n a all Grd Array (GA) package. The followng able provdes an overvew of he mechancal arbues of hs package. Table 55. Package Mechancal Arbues Parameer U-Processor Lne and Y-Processor Lne Package Technology Package Type Inerconnec Lead Free Halogenaed Flame Reardan Free Flp Chp all Grd Array all Grd Array (GA) Yes Yes Solder all Composon SAC 405 all/pn Coun 1168 Package Confguraon Package Dmensons Grd Array Paern Land Sde Capacors De Sde Capacors De Confguraon Nomnal Package Sze Mn all/pn pch alls Anywhere Yes No Mul-Chp Package (MCP) / 2 des 40.0 mm x 24.0 mm 0.65 mm 8.2 Table 56. Package Loadng Specfcaons Package Loadng Specfcaons Maxmum Sac Normal Load Lm Noes Y-Processor Lne 22 N (15 lbf) 1, 2, 3 U-Processor Lne/ Y-Processor Lne GA 67 N (15 lbf) 1, 2, 3 Noes: 1. The hermal soluon aach mechansm mus no nduce connuous sress o he package. I may only apply a unform load o he de o manan a hermal nerface. 2. Ths specfcaon apples o he unform compressve load n he drecon perpendcular o he des op surface. 3. Ths specfcaon s based on lmed esng for desgn characerzaon. Daashee Volume 1 of 2 July Order No.:

99 Package Specfcaons Processors 8.3 Table 57. Package Sorage Specfcaons Package Sorage Specfcaons Parameer Descrpon Mn Max Noes T ASOLUTE STORAGE T SUSTAINED STORAGE RH SUSTAINED STORAGE The non-operang devce sorage emperaure. Damage (laen or oherwse) may occur when subjeced o hs emperaure for any lengh of me. The amben sorage emperaure lm (n shppng meda) for a susaned perod of me. The maxmum devce sorage relave humdy for a susaned perod of me. -25 C 125 C 1, 2, 3-5 C 40 C 4, 5 24 C 5, 6 TIME SUSTAINED STORAGE A prolonged or exended perod of me: ypcally assocaed wh cusomer shelf lfe. 0 monhs 6 monhs 6 Noes: 1. Refers o a componen devce ha s no assembled n a board or socke ha s no o be elecrcally conneced o a volage reference or I/O sgnals. 2. Specfed emperaures are based on daa colleced. Excepons for surface moun reflow are specfed by applcable JEDEC sandards. 3. T ASOLUTE STORAGE apples o he unassembled componen only and does no apply o he shppng meda, mosure barrer bags or desccan. 4. Inel-branded board producs are cerfed o mee he followng emperaure and humdy lms ha are gven as an example only (Non-Operang Temperaure Lm: -40 C o 70 C, Humdy 50% o 90%, non-condensng wh a maxmum we bulb of 28 C). Pos board aach sorage emperaure lms are no specfed for non-inel branded boards. 5. The JEDEC, J-JSTD-020 mosure level rang and assocaed handlng pracces apply o all mosure sensve devces removed from he mosure barrer bag. 6. Nomnal emperaure and humdy condons and duraons are gven and esed whn he consrans mposed by T SUSTAINED STORAGE and cusomer shelf lfe n applcable Inel boxes and bags. July 2014 Daashee Volume 1 of 2 Order No.:

100 Processors Processor all and Sgnal Informaon 9.0 Processor all and Sgnal Informaon Ths chaper provdes he processor all nformaon. Table 58. all Ls by Sgnal Name for DDR3L Confguraon ACPRESENT / GPIO31 APWROK ATLOW# / GPIO72 MUSY# / GPIO76 PM#0 PM#1 PM#2 PM#3 PM#4 PM#5 PM#6 PM#7 CATERR# CFG[0] CFG[1] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] CFG[18] CFG[19] CFG[2] CFG[3] AJ8 A5 AN4 P1 J60 H60 H61 H62 K59 H63 K60 J61 K61 AC60 AC62 V60 U60 T63 T62 T61 T60 AA62 AA61 U63 U62 AC63 AA63 CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG_RCOMP CL_CLK CL_DATA CL_RST# CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_PCIE_N0 CLKOUT_PCIE_N1 CLKOUT_PCIE_N2 CLKOUT_PCIE_N3 CLKOUT_PCIE_N4 CLKOUT_PCIE_N5 CLKOUT_PCIE_P0 CLKOUT_PCIE_P1 CLKOUT_PCIE_P2 CLKOUT_PCIE_P3 CLKOUT_PCIE_P4 CLKOUT_PCIE_P5 CLKRUN# / GPIO32 AA60 Y62 Y61 Y60 V62 V61 V63 AF2 AD2 AF4 35 A35 AN15 AP15 C43 41 C41 38 A39 37 C42 A41 42 C37 39 A37 V5 DAISY_CHAIN_NCT F_A3 DAISY_CHAIN_NCT F_A4 DAISY_CHAIN_NCT F_A60 DAISY_CHAIN_NCT F_A61 DAISY_CHAIN_NCT F_A62 DAISY_CHAIN_NCT F_AV1 DAISY_CHAIN_NCT F_AW1 DAISY_CHAIN_NCT F_AW2 DAISY_CHAIN_NCT F_AW3 DAISY_CHAIN_NCT F_AW61 DAISY_CHAIN_NCT F_AW62 DAISY_CHAIN_NCT F_AW63 DAISY_CHAIN_NCT F_AY2 DAISY_CHAIN_NCT F_AY3 DAISY_CHAIN_NCT F_AY60 DAISY_CHAIN_NCT F_AY61 DAISY_CHAIN_NCT F_AY62 DAISY_CHAIN_NCT F_2 A3 A4 A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63 AY2 AY3 AY60 AY61 AY62 2 Daashee Volume 1 of 2 July Order No.:

101 Processor all and Sgnal Informaon Processors DAISY_CHAIN_NCT F_3 DAISY_CHAIN_NCT F_ DDP_CTRLDATA DDP_HPD DDPC_AUXN C9 C8 6 GPIO25 GPIO26 GPIO27 AM4 AN3 AN5 DAISY_CHAIN_NCT F_62 DAISY_CHAIN_NCT F_ DDPC_AUXP DDPC_CTRLCLK DDPC_CTRLDATA A6 D9 D11 GPIO28 GPIO44 GPIO45 AD7 AK4 AG5 DAISY_CHAIN_NCT F_C1 DAISY_CHAIN_NCT F_C2 C1 C2 DDPC_HPD DEVSLP0 / GPIO33 DEVSLP1 / GPIO38 A8 P2 L2 GPIO46 GPIO47 GPIO48 AG3 A6 U4 DCPRTC AE7 DEVSLP2 / GPIO39 N5 GPIO49 Y3 DCPSUS1 AD10 DIFFCLK_IASREF C26 GPIO50 P3 DCPSUS1 AD8 DPWROK AV5 GPIO51 R5 DCPSUS2 AH13 DSWVRMEN AW7 GPIO52 L1 DCPSUS3 J13 EDP_AUXN A45 GPIO53 L4 DCPSUS4 A8 EDP_AUXP 45 GPIO54 L3 DCPSUSYP AG19 edp_klctl 8 GPIO55 U7 DCPSUSYP AG20 edp_klen A9 GPIO56 AG6 DDI1_TXN[0] C54 EDP_DISP_UTIL A43 GPIO57 AP1 DDI1_TXN[1] 58 EDP_HPD D6 GPIO58 AL4 DDI1_TXN[2] 55 EDP_RCOMP D20 GPIO59 AT5 DDI1_TXN[3] A57 EDP_TXN0 C45 GPIO8 AU2 DDI1_TXP[0] C55 EDP_TXN1 A47 GPIO9 AM3 DDI1_TXP[1] DDI1_TXP[2] DDI1_TXP[3] C58 A55 57 EDP_TXN2 EDP_TXN3 EDP_TXP0 C47 A49 46 GSPI_MOSI / GPIO90 GSPI0_CLK / GPIO84 K2 L6 DDI2_TXN[0] DDI2_TXN[1] DDI2_TXN[2] C51 C53 C49 EDP_TXP1 EDP_TXP2 EDP_TXP3 47 C46 49 GSPI0_CS# / GPIO83 GSPI0_MISO / GPIO85 R6 N6 DDI2_TXN[3] DDI2_TXP[0] DDI2_TXP[1] A53 C50 54 edp_vdden GPIO10 GPIO13 C6 AM2 AT3 GSPI0_MOSI / GPIO86 GSPI1_CLK / GPIO88 L8 L5 DDI2_TXP[2] DDI2_TXP[3] DDP_AUXN C5 GPIO14 GPIO15 GPIO16 AH4 AD6 Y1 GSPI1_CS# / GPIO87 GSPI1_MISO / GPIO89 R7 N7 DDP_AUXP DDP_CTRLCLK 5 9 GPIO17 GPIO24 T3 AD5 HDA_CLK / I2S0_SCLK AW8 July 2014 Daashee Volume 1 of 2 Order No.:

102 Processors Processor all and Sgnal Informaon HDA_DOCK_EN# / I2S1_TXD HDA_DOCK_RST# / I2S1_SFRM AW10 AV10 PCH_TRST# PCIE_IREF PCIE_RCOMP AU62 27 A27 PETn5_L3 PETp1 / US3Tp3 PETp2 / US3Tp4 22 C31 A31 HDA_RST# / I2S_MCLK HDA_SDI0 / I2S0_RXD HDA_SDI1 / I2S1_RXD HDA_SDO / I2S0_TXD HDA_SYNC / I2S0_SFRM HSIOPC / GPIO71 I2C0_SCL / GPIO5 I2C0_SDA / GPIO4 I2C1_SCL / GPIO7 I2C1_SDA / GPIO6 I2S1_SCLK INTRUDER# INTVRMEN JTAGX LAD0 LAD1 LAD2 LAD3 LAN_PHY_PWR_CT RL / GPIO12 LFRAME# OC0# / GPIO40 OC1# / GPIO41 OC2# / GPIO42 OC3# / GPIO43 PCH_OPI_RCOMP PCH_PWROK PCH_TCK PCH_TDI PCH_TDO PCH_TMS AU8 AY10 AU12 AU11 AV11 Y2 F3 F2 F1 G4 AY8 AU6 AV7 AE63 AU14 AW12 AY12 AW11 AM7 AV12 AL3 AT1 AH2 AV3 AW15 AY7 AE62 AD61 AE61 AD62 PCIECLKRQ0# / GPIO18 PCIECLKRQ1# / GPIO19 PCIECLKRQ2# / GPIO20 PCIECLKRQ3# / GPIO21 PCIECLKRQ4# / GPIO22 PCIECLKRQ5# / GPIO23 PECI PERn1 / US3Rn3 PERn2 / US3Rn4 PERn3 PERn4 PERn5_L0 PERn5_L1 PERn5_L2 PERn5_L3 PERp1 / US3Rp3 PERp2 / US3Rp4 PERp3 PERp4 PERp5_L0 PERp5_L1 PERp5_L2 PERp5_L3 PETn1 / US3Tn3 PETn2 / US3Tn4 PETn3 PETn4 PETn5_L0 PETn5_L1 PETn5_L2 U2 Y5 AD1 N1 U5 T2 N62 G17 F15 G11 F13 F10 F8 H10 E6 F17 G15 F11 G13 E10 E8 G10 F6 C30 31 C29 29 C PETp3 30 PETp4 A29 PETp5_L0 C22 PETp5_L1 A23 PETp5_L2 C21 PETp5_L3 A21 PIRQA# / GPIO77 U6 PIRQ# / GPIO78 P4 PIRQC# / GPIO79 N4 PIRQD# / GPIO80 N2 PLTRST# AG7 PME# AD4 PRDY# J62 PREQ# K62 PROC_DETECT# D61 PROC_OPI_RCOMP AY15 PROC_TCK E60 PROC_TDI F63 PROC_TDO F62 PROC_TMS E61 PROC_TRST# E59 PROCHOT# K63 PROCPWRGD C61 PWR_DEUG# H59 PWRTN# AL7 RCIN# / GPIO82 V4 RSMRST# AW6 W23 Y22 43 T59 AD60 AD59 Daashee Volume 1 of 2 July Order No.:

103 Processor all and Sgnal Informaon Processors AA59 D15 RTCX1 AW5 AE60 AU10 RTCX2 AY5 AC59 AU15 SA_A0 AU35 AG58 E1 SA_A1 AV35 V59 D1 SA_A2 AY41 U59 J20 SA_CAS# AU34 AL1 H18 SA_CKE0 AU43 AP7 AN10 SA_CKE1 AW43 AM11 AM10 SA_CKE2 AY42 AV62 L59 SA_CKE3 AY43 D58 J58 SA_CLK#0 AU37 P20 Y20 SA_CLK#1 AW36 R20 AC20 SA_CLK0 AV37 N60 V21 SA_CLK1 AY36 AV2 N58 SA_CS#0 AP33 AF20 AC58 SA_CS#1 AR32 A21 A23 SA_DQ0 AH63 AY14 AD23 SA_DQ1 AH62 AW14 AA23 SA_DQ10 AP63 E15 AE59 SA_DQ11 AP62 E13 K18 SA_DQ12 AM61 AL11 M20 SA_DQ13 AM60 AC4 K21 SA_DQ14 AP61 A5 M21 SA_DQ15 AP60 N23 _TP AV63 SA_DQ32 AY58 T23 _TP AU63 SA_DQ33 AW58 U10 _TP C63 SA_DQ34 AY56 R23 _TP C62 SA_DQ35 AW56 L11 _TP A51 SA_DQ2 AK63 K10 _TP 51 SA_DQ36 AV58 F22 _TP P60 SA_DQ37 AU58 H22 _TP P61 SA_DQ38 AV56 J21 IVR_ERROR N59 SA_DQ39 AU56 AT2 IST_TRIGGER N61 SA_DQ40 AY54 AU44 _TP L60 SA_DQ41 AW54 AV44 RTCRST# AU7 SA_DQ42 AY52 July 2014 Daashee Volume 1 of 2 Order No.:

104 Processors Processor all and Sgnal Informaon SA_DQ43 AW52 SA_DQ6 AK61 SA_MA6 AV40 SA_DQ44 AV54 S_DQ44 AV19 SA_MA7 AW39 SA_DQ45 AU54 S_DQ45 AU19 SA_MA8 AY39 SA_DQ3 AK62 S_DQ46 AV17 SA_MA9 AU40 SA_DQ46 AV52 S_DQ47 AU17 SA_ODT0 AP32 SA_DQ47 AU52 SA_DQ7 AK60 SA_RAS# AY34 S_DQ0 AY31 SA_DQ8 AM63 SA_WE# AW34 S_DQ1 AW31 SA_DQ9 AM62 SATA_IREF A12 S_DQ2 AY29 SA_DQSN0 AJ61 SATA_RCOMP C12 S_DQ3 S_DQ4 S_DQ5 AW29 AV31 AU31 SA_DQSN1 SA_DQSN4 SA_DQSN5 AN62 AV57 AV53 SATA_Rn0 / PERn6_L3 SATA_Rn1 / PERn6_L2 J5 J8 S_DQ6 S_DQ7 SA_DQ4 AV29 AU29 AH61 S_DQSN0 S_DQSN1 S_DQSN4 AW30 AV26 AW22 SATA_Rn2 / PERn6_L1 SATA_Rn3 / PERn6_L0 J6 F5 S_DQ8 S_DQ9 S_DQ10 AY27 AW27 AY25 S_DQSN5 SA_DQSP0 SA_DQSP1 AV18 AJ62 AN61 SATA_Rp0 / PERp6_L3 SATA_Rp1 / PERp6_L2 H5 H8 S_DQ11 S_DQ12 S_DQ13 AW25 AV27 AU27 SA_DQSP4 SA_DQSP5 S_DQSP0 AW57 AW53 AV30 SATA_Rp2 / PERp6_L1 SATA_Rp3 / PERp6_L0 H6 E5 S_DQ14 S_DQ15 AV25 AU25 S_DQSP1 S_DQSP4 AW26 AV22 SATA_Tn0 / PETn6_L3 15 S_DQ32 S_DQ33 SA_DQ5 AY23 AW23 AH60 S_DQSP5 SA_MA0 SA_MA1 AW18 AU36 AY37 SATA_Tn1 / PETn6_L2 SATA_Tn2 / PETn6_L1 A17 14 S_DQ34 S_DQ35 S_DQ36 AY21 AW21 AV23 SA_MA10 SA_MA11 SA_MA12 AP35 AW41 AU41 SATA_Tn3 / PETn6_L0 SATA_Tp0 / PETp6_L3 C17 A15 S_DQ37 S_DQ38 S_DQ39 AU23 AV21 AU21 SA_MA13 SA_MA14 SA_MA15 AR35 AV42 AU42 SATA_Tp1 / PETp6_L2 SATA_Tp2 / PETp6_L1 17 C15 S_DQ40 S_DQ41 S_DQ42 S_DQ43 AY19 AW19 AY17 AW17 SA_MA2 SA_MA3 SA_MA4 SA_MA5 AR38 AP36 AU39 AR36 SATA_Tp3 / PETp6_L0 SATA0GP / GPIO34 SATA1GP / GPIO35 D17 V1 U1 Daashee Volume 1 of 2 July Order No.:

105 Processor all and Sgnal Informaon Processors SATA2GP / GPIO36 V6 SA_DQ58 AM49 S_DQ59 AL18 SATA3GP / GPIO37 AC1 SA_DQ59 AK49 SA_DQ22 AR57 SATALED# U3 SA_DQ60 AM48 S_DQ60 AK20 S_A0 AL35 SA_DQ61 AK48 S_DQ61 AM20 S_A1 AM36 SA_DQ19 AK57 S_DQ62 AR18 S_A2 AU49 SA_DQ62 AM51 S_DQ63 AP18 S_CAS# AM33 SA_DQ63 AK51 SA_DQ23 AN57 S_CK#0 AM38 S_DQ16 AM29 SA_DQ24 AP55 S_CK#1 AK38 S_DQ17 AK29 SA_DQ25 AR55 S_CK0 AN38 S_DQ18 AL28 SA_DQSN2 AM58 S_CK1 AL38 S_DQ19 AK28 SA_DQSN3 AM55 S_CKE0 AY49 S_DQ20 AR29 SA_DQSN6 AL43 S_CKE1 AU50 S_DQ21 AN29 SA_DQSN7 AL48 S_CKE2 AW49 S_DQ22 AR28 S_DQSN2 AN28 S_CKE3 AV50 S_DQ23 AP28 S_DQSN3 AN25 S_CS#0 AM32 SA_DQ20 AL58 S_DQSN6 AN21 S_CS#1 AK32 S_DQ24 AN26 S_DQSN7 AN18 SA_DQ16 AP58 S_DQ25 AR26 SA_DQSP2 AN58 SA_DQ17 AR58 S_DQ26 AR25 SA_DQSP3 AN55 SA_DQ26 AM54 S_DQ27 AP25 SA_DQSP6 AL42 SA_DQ27 AK54 S_DQ28 AK26 SA_DQSP7 AL49 SA_DQ28 AL55 S_DQ29 AM26 S_DQSP2 AM28 SA_DQ29 AK55 S_DQ30 AK25 S_DQSP3 AM25 SA_DQ30 AR54 S_DQ31 AL25 S_DQSP6 AM21 SA_DQ31 AN54 S_DQ48 AR21 S_DQSP7 AM18 SA_DQ48 AK40 S_DQ49 AR22 S_MA0 AP40 SA_DQ49 AK42 SA_DQ21 AK58 S_MA1 AR40 SA_DQ50 AM43 S_DQ50 AL21 S_MA10 AK36 SA_DQ51 AM45 S_DQ51 AM22 S_MA11 AV47 SA_DQ18 AM57 S_DQ52 AN22 S_MA12 AU47 SA_DQ52 AK45 S_DQ53 AP21 S_MA13 AK33 SA_DQ53 AK43 S_DQ54 AK21 S_MA14 AR46 SA_DQ54 AM40 S_DQ55 AK22 S_MA15 AP46 SA_DQ55 AM42 S_DQ56 AN20 S_MA2 AP42 SA_DQ56 AM46 S_DQ57 AR20 S_MA3 AR42 SA_DQ57 AK46 S_DQ58 AK18 S_MA4 AR45 July 2014 Daashee Volume 1 of 2 Order No.:

106 Processors Processor all and Sgnal Informaon S_MA5 S_MA6 S_MA7 S_MA8 S_MA9 S_ODT0 S_RAS# S_WE# SDIO_CLK / GPIO64 SDIO_CMD / GPIO65 SDIO_D0 / GPIO66 SDIO_D1 / GPIO67 SDIO_D2 / GPIO68 SDIO_D3 / GPIO69 SDIO_POWER_EN / GPIO70 SERIRQ SLP_A# SLP_LAN# SLP_S0# SLP_S3# AP45 AW46 AY46 AY47 AU46 AL32 AM35 AK35 E3 F4 D3 E4 C3 E2 C4 T4 AL5 AJ7 AF3 AT4 SMCLK SMDATA SML0ALERT# / GPIO60 SML0CLK SML0DATA SML1ALERT# / PCHHOT# / GPIO73 SML1CLK / GPIO75 SML1DATA / GPIO74 SPI_CLK SPI_CS0# SPI_CS1# SPI_CS2# SPI_IO2 SPI_IO3 SPI_MISO SPI_MOSI SPKR / GPIO81 SRTCRST# SUS_STAT# / GPIO61 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3 AA3 Y7 Y4 AC2 Y6 AF1 AA4 AA2 V2 AV6 AG4 UART0_RTS# / GPIO93 UART0_RXD / GPIO91 UART0_TXD / GPIO92 UART1_CTS# / GPIO3 UART1_RST# / GPIO2 UART1_RXD / GPIO0 UART1_TXD / GPIO1 US2n0 US2n1 US2n2 US2n3 US2n4 US2n5 US2n6 US2n7 US2p0 US2p1 US2p2 J2 J1 K3 J4 J3 K4 G2 AN8 AR7 AR8 AR10 AM15 AM13 AP11 AR13 AM8 AT7 AP8 SLP_S4# AJ6 SUSACK# AK2 US2p3 AT10 SLP_S5# / GPIO63 AP5 SUSCLK / GPIO62 AE6 US2p4 AL15 SLP_SUS# SLP_WLAN# / GPIO29 SM_DRAMRST# SM_PG_CNTL1 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 SMALERT# / GPIO11 AP4 AM5 AV15 AV61 AU60 AV60 AU61 AP49 AR51 AP51 AN2 SUSWARN# / SUSPWRDNACK / GPIO30 SYS_PWROK SYS_RESET# TD_IREF TESTLOW_AK8 TESTLOW_AL8 TESTLOW_C34 TESTLOW_C35 THERMTRIP# UART0_CTS# / GPIO94 AV4 AG2 AC3 12 AK8 AL8 C34 C35 D60 G1 US2p5 US2p6 US2p7 US3Rn1 US3Rn2 US3Rp1 US3Rp2 US3Tn1 US3Tn2 US3Tp1 US3Tp2 USRIAS AN13 AN11 AP13 G20 E18 H20 F18 C A33 AJ11 Daashee Volume 1 of 2 July Order No.:

107 Processor all and Sgnal Informaon Processors USRIAS# AJ10 F40 1_05 AE8 F59 F44 1_05 AF22 A57 F48 1_05 H11 AD57 F52 1_05 H15 AG57 F56 1_05 J11 C24 G23 1_05 AG16 C28 G25 1_05 AG17 C32 G27 3_3 V8 C36 G29 3_3 W9 C40 G31 3_3 K14 C44 G33 3_3 K16 C48 G35 ACLKPLL A20 C52 G37 APLL AA21 C56 G39 APLL W21 E23 G41 ASW AE9 E25 G43 ASW AF9 E27 G45 ASW AG8 E29 G47 ASW AG13 E31 G49 ASW AG14 E33 G51 CLK J18 E35 G53 CLK K19 E37 G55 CLK J17 E39 G57 CLK T21 E41 H23 CLK R21 E43 J23 DSW3_3 AH10 E45 K23 HDA AH14 E47 K57 HSIO M9 E49 L22 HSIO K9 E51 M23 HSIO L10 E53 M57 IO_OUT A59 E55 P57 VCOMP_OUT E20 E57 U57 RTC AG10 F24 W57 SATA3PLL 11 F28 _SENSE E63 SDIO U8 F32 1_05 P9 SDIO T9 F36 1_05 N8 SPI Y8 July 2014 Daashee Volume 1 of 2 Order No.:

108 Processors Processor all and Sgnal Informaon ST AC22 A32 AH17 ST AE22 A36 AH19 ST AE23 A40 AH20 ST_PWRGD 59 A48 AH22 SUS3_3 AH11 A52 AH24 SUS3_3 AA9 A56 AH28 SUS3_3 AC9 AA1 AH30 SUS3_3 AE20 A44 AH32 SUS3_3 AE21 AA58 AH34 TS1_5 J15 A10 AH36 US3PLL 18 A20 AH38 VDDQ AH26 AE5 AH40 VDDQ AJ31 A22 AH42 VDDQ AJ33 A7 AH44 VDDQ AJ37 AC61 AH49 VDDQ AN33 AD3 AH51 VDDQ AP43 AD63 AH53 VDDQ AR48 AE10 AH55 VDDQ AY35 AD21 AH57 VDDQ AY40 AE58 AJ13 VDDQ AY44 AR43 AJ14 VDDQ AY50 C39 AJ23 VIDALERT# L62 AF11 AJ25 VIDSCLK N63 AF12 AJ27 VIDSOUT L63 AF14 AJ29 VR_EN F60 AF15 AJ35 VR_READY C59 AF17 AJ39 P62 AF18 AJ41 D63 AG21 AJ43 P22 AG23 AJ45 N21 AG1 AJ47 A11 AG11 AJ50 A14 AG60 AJ52 A18 AG61 AJ54 A24 AG62 AJ56 A28 AG63 AJ58 Daashee Volume 1 of 2 July Order No.:

109 Processor all and Sgnal Informaon Processors AJ60 AN36 AR49 AJ63 AN39 AR5 AK23 AN40 AR52 AK3 AN42 AT13 AK52 AN43 AT35 AL10 AN45 AT37 AL13 AN46 AT40 AL17 AN48 AT42 AL20 AN49 AT43 AL22 AN51 AT46 AL23 AN52 AT49 AL26 AN60 AT61 AL29 AN63 AT62 AL31 AN7 AT63 AL33 AP10 AU1 AL36 AP17 AU16 AL39 AP20 AU18 AL40 AP22 AU20 AL45 AP23 AU22 AL46 AP26 AU24 AL51 AP29 AU26 AL52 AP3 AU28 AL54 AP31 AU30 AL57 AP38 AU33 AL60 AP39 AU51 AL61 AP52 AU53 AM1 AP54 AU55 AM17 AP57 AU57 AM23 AR11 AU59 AM31 AR15 AV14 AM52 AR17 D62 AN17 AR23 AV16 AN23 AR31 AV20 AN31 AR33 AV24 AN32 AR39 AV28 AN35 AP48 AV33 July 2014 Daashee Volume 1 of 2 Order No.:

110 Processors Processor all and Sgnal Informaon AV34 AY59 D34 AV36 AY6 D35 AV39 AY4 D37 AV41 20 D38 AV43 24 D39 AV46 26 D41 AV49 28 D42 AV51 32 D43 AV55 C38 D45 AV59 36 D46 AV8 4 D47 AW16 40 D49 AW24 44 D50 AW33 C14 D51 AW35 48 D53 AW37 52 D54 AW4 56 D55 AW40 60 D57 AW42 C11 D59 AW44 C18 E11 AW47 C20 E17 AW50 C25 F42 AW51 C27 F20 AW59 D12 D5 AW60 D14 F26 AY11 D18 F30 AY16 D21 F34 AY18 D23 F38 AY22 D25 G6 AY24 D26 F46 AY26 D27 F50 AY30 D29 F54 AY33 D2 F58 AY51 D30 F61 AY53 D31 G18 AY57 D33 G22 Daashee Volume 1 of 2 July Order No.:

111 Processor all and Sgnal Informaon Processors G3 V3 G5 V7 G8 W20 H13 Y10 H17 U9 H57 Y59 J10 Y63 J22 W22 J59 V58 J63 AH46 K1 V23 K12 AH16 R22 _SENSE E62 L13 WAKE# AJ5 L15 XTAL24_IN A25 L17 XTAL24_OUT 25 L18 L20 L58 L61 L7 M22 N10 N3 C57 P59 P63 R10 R8 T1 T58 D8 U20 U22 U61 V10 July 2014 Daashee Volume 1 of 2 Order No.:

112 Processors Processor all and Sgnal Informaon Table 59. all Ls by Sgnal Name for LPDDR3 Confguraon ACPRESENT / GPIO31 APWROK ATLOW# / GPIO72 MUSY# / GPIO76 PM#0 PM#1 PM#2 PM#3 PM#4 PM#5 PM#6 PM#7 CATERR# CFG[0] CFG[1] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] AJ8 A5 AN4 P1 J60 H60 H61 H62 K59 H63 K60 J61 K61 AC60 AC62 V60 U60 T63 T62 T61 CFG_RCOMP CL_CLK CL_DATA CL_RST# CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_PCIE_N0 CLKOUT_PCIE_N1 CLKOUT_PCIE_N2 CLKOUT_PCIE_N3 CLKOUT_PCIE_N4 CLKOUT_PCIE_N5 CLKOUT_PCIE_P0 CLKOUT_PCIE_P1 CLKOUT_PCIE_P2 CLKOUT_PCIE_P3 CLKOUT_PCIE_P4 CLKOUT_PCIE_P5 CLKRUN# / GPIO32 V63 AF2 AD2 AF4 35 A35 AN15 AP15 C43 41 C41 38 A39 37 C42 A41 42 C37 39 A37 V5 DAISY_CHAIN_NCT F_AW61 DAISY_CHAIN_NCT F_AW62 DAISY_CHAIN_NCT F_AW63 DAISY_CHAIN_NCT F_AY2 DAISY_CHAIN_NCT F_AY3 DAISY_CHAIN_NCT F_AY60 DAISY_CHAIN_NCT F_AY61 DAISY_CHAIN_NCT F_AY62 DAISY_CHAIN_NCT F_2 DAISY_CHAIN_NCT F_3 DAISY_CHAIN_NCT F_61 DAISY_CHAIN_NCT F_62 DAISY_CHAIN_NCT F_63 DAISY_CHAIN_NCT F_C1 AW61 AW62 AW63 AY2 AY3 AY60 AY61 AY C1 CFG[15] CFG[16] CFG[17] CFG[18] CFG[19] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] T60 AA62 AA61 U63 U62 AC63 AA63 AA60 Y62 Y61 Y60 V62 V61 DAISY_CHAIN_NCT F_A3 DAISY_CHAIN_NCT F_A4 DAISY_CHAIN_NCT F_A60 DAISY_CHAIN_NCT F_A61 DAISY_CHAIN_NCT F_A62 DAISY_CHAIN_NCT F_AV1 DAISY_CHAIN_NCT F_AW1 DAISY_CHAIN_NCT F_AW2 DAISY_CHAIN_NCT F_AW3 A3 A4 A60 A61 A62 AV1 AW1 AW2 AW3 DAISY_CHAIN_NCT F_C2 DCPRTC DCPSUS1 DCPSUS1 DCPSUS2 DCPSUS3 DCPSUS4 DCPSUSYP DCPSUSYP DDI1_TXN[0] DDI1_TXN[1] DDI1_TXN[2] DDI1_TXN[3] C2 AE7 AD10 AD8 AH13 J13 A8 AG19 AG20 C A57 Daashee Volume 1 of 2 July Order No.:

113 Processor all and Sgnal Informaon Processors DDI1_TXP[0] C55 EDP_TXN1 A47 GPIO9 AM3 DDI1_TXP[1] DDI1_TXP[2] DDI1_TXP[3] C58 A55 57 EDP_TXN2 EDP_TXN3 EDP_TXP0 C47 A49 46 GSPI_MOSI / GPIO90 GSPI0_CLK / GPIO84 K2 L6 DDI2_TXN[0] DDI2_TXN[1] DDI2_TXN[2] C51 C53 C49 EDP_TXP1 EDP_TXP2 EDP_TXP3 47 C46 49 GSPI0_CS# / GPIO83 GSPI0_MISO / GPIO85 R6 N6 DDI2_TXN[3] DDI2_TXP[0] DDI2_TXP[1] A53 C50 54 edp_vdden GPIO10 GPIO13 C6 AM2 AT3 GSPI0_MOSI / GPIO86 GSPI1_CLK / GPIO88 L8 L5 DDI2_TXP[2] DDI2_TXP[3] DDP_AUXN C5 GPIO14 GPIO15 GPIO16 AH4 AD6 Y1 GSPI1_CS# / GPIO87 GSPI1_MISO / GPIO89 R7 N7 DDP_AUXP DDP_CTRLCLK 5 9 GPIO17 GPIO24 T3 AD5 HDA_CLK / I2S0_SCLK AW8 DDP_CTRLDATA DDP_HPD DDPC_AUXN C9 C8 6 GPIO25 GPIO26 GPIO27 AM4 AN3 AN5 HDA_DOCK_EN# / I2S1_TXD HDA_DOCK_RST# / I2S1_SFRM AW10 AV10 DDPC_AUXP DDPC_CTRLCLK DDPC_CTRLDATA A6 D9 D11 GPIO28 GPIO44 GPIO45 AD7 AK4 AG5 HDA_RST# / I2S_MCLK HDA_SDI0 / I2S0_RXD AU8 AY10 DDPC_HPD DEVSLP0 / GPIO33 DEVSLP1 / GPIO38 A8 P2 L2 GPIO46 GPIO47 GPIO48 AG3 A6 U4 HDA_SDI1 / I2S1_RXD HDA_SDO / I2S0_TXD AU12 AU11 DEVSLP2 / GPIO39 N5 DIFFCLK_IASREF C26 DPWROK AV5 DSWVRMEN AW7 EDP_AUXN A45 EDP_AUXP 45 edp_klctl 8 edp_klen A9 EDP_DISP_UTIL A43 EDP_HPD D6 EDP_RCOMP D20 EDP_TXN0 C45 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO8 Y3 P3 R5 L1 L4 L3 U7 AG6 AP1 AL4 AT5 AU2 HDA_SYNC / I2S0_SFRM HSIOPC / GPIO71 I2C0_SCL / GPIO5 I2C0_SDA / GPIO4 I2C1_SCL / GPIO7 I2C1_SDA / GPIO6 I2S1_SCLK INTRUDER# INTVRMEN JTAGX LAD0 AV11 Y2 F3 F2 F1 G4 AY8 AU6 AV7 AE63 AU14 July 2014 Daashee Volume 1 of 2 Order No.:

114 Processors Processor all and Sgnal Informaon LAD1 AW12 PERn5_L3 E6 PROC_TDI F63 LAD2 AY12 PERp1 / US3Rp3 F17 PROC_TDO F62 LAD3 AW11 PERp2 / US3Rp4 G15 PROC_TMS E61 LAN_PHY_PWR_CT RL / GPIO12 LFRAME# OC0# / GPIO40 OC1# / GPIO41 OC2# / GPIO42 OC3# / GPIO43 PCH_OPI_RCOMP PCH_PWROK PCH_TCK PCH_TDI PCH_TDO PCH_TMS PCH_TRST# PCIE_IREF PCIE_RCOMP PCIECLKRQ0# / GPIO18 AM7 AV12 AL3 AT1 AH2 AV3 AW15 AY7 AE62 AD61 AE61 AD62 AU62 27 A27 U2 PERp3 PERp4 PERp5_L0 PERp5_L1 PERp5_L2 PERp5_L3 PETn1 / US3Tn3 PETn2 / US3Tn4 PETn3 PETn4 PETn5_L0 PETn5_L1 PETn5_L2 PETn5_L3 PETp1 / US3Tp3 PETp2 / US3Tp4 PETp3 F11 G13 E10 E8 G10 F6 C30 31 C29 29 C C31 A31 30 PROC_TRST# PROCHOT# PROCPWRGD PWR_DEUG# PWRTN# RCIN# / GPIO82 RSMRST# E59 K63 C61 H59 AL7 V4 AW6 W23 Y22 43 T59 AD60 AD59 AA59 AE60 AC59 AG58 PCIECLKRQ1# / GPIO19 PCIECLKRQ2# / GPIO20 Y5 AD1 PETp4 PETp5_L0 PETp5_L1 A29 C22 A23 V59 U59 AL1 PCIECLKRQ3# / GPIO21 PCIECLKRQ4# / GPIO22 N1 U5 PETp5_L2 PETp5_L3 PIRQA# / GPIO77 C21 A21 U6 AP7 AM11 AV62 PCIECLKRQ5# / GPIO23 PECI PERn1 / US3Rn3 PERn2 / US3Rn4 PERn3 PERn4 PERn5_L0 PERn5_L1 PERn5_L2 T2 N62 G17 F15 G11 F13 F10 F8 H10 PIRQ# / GPIO78 P4 PIRQC# / GPIO79 N4 PIRQD# / GPIO80 N2 PLTRST# AG7 PME# AD4 PRDY# J62 PREQ# K62 PROC_DETECT# D61 PROC_OPI_RCOMP AY15 PROC_TCK E60 D58 P20 R20 N60 AV2 AF20 A21 AY14 AW14 E15 Daashee Volume 1 of 2 July Order No.:

115 Processor all and Sgnal Informaon Processors E13 K18 SA_DQ12 AM61 AL11 M20 SA_DQ13 AM60 AC4 K21 SA_DQ14 AP61 A5 M21 SA_DQ15 AP60 N23 _TP AV63 SA_DQ32 AY58 T23 _TP AU63 SA_DQ33 AW58 U10 _TP C63 SA_DQ34 AY56 R23 _TP C62 SA_DQ35 AW56 L11 _TP A51 SA_DQ2 AK63 K10 _TP 51 SA_DQ36 AV58 F22 _TP P60 SA_DQ37 AU58 H22 _TP P61 SA_DQ38 AV56 J21 IVR_ERROR N59 SA_DQ39 AU56 AT2 IST_TRIGGER N61 SA_DQ40 AY54 AU44 _TP L60 SA_DQ41 AW54 AV44 RTCRST# AU7 SA_DQ42 AY52 D15 RTCX1 AW5 SA_DQ43 AW52 AU10 RTCX2 AY5 SA_DQ44 AV54 AU15 SA_CA4 AU35 SA_DQ45 AU54 E1 SA_CA6 AV35 SA_DQ3 AK62 D1 SA_CAA5 AY41 SA_DQ46 AV52 J20 SA_CA1 AU34 SA_DQ47 AU52 H18 SA_CKE0 AU43 S_DQ0 AY31 AN10 SA_CKE1 AW43 S_DQ1 AW31 AM10 SA_CKE2 AY42 S_DQ2 AY29 L59 SA_CKE3 AY43 S_DQ3 AW29 J58 SA_CLK#0 AU37 S_DQ4 AV31 Y20 SA_CLK#1 AW36 S_DQ5 AU31 AC20 SA_CLK0 AV37 S_DQ6 AV29 V21 SA_CLK1 AY36 S_DQ7 AU29 N58 SA_CS#0 AP33 SA_DQ4 AH61 AC58 SA_CS#1 AR32 S_DQ8 AY27 A23 SA_DQ0 AH63 S_DQ9 AW27 AD23 SA_DQ1 AH62 S_DQ10 AY25 AA23 SA_DQ10 AP63 S_DQ11 AW25 AE59 SA_DQ11 AP62 S_DQ12 AV27 July 2014 Daashee Volume 1 of 2 Order No.:

116 Processors Processor all and Sgnal Informaon S_DQ13 S_DQ14 S_DQ15 AU27 AV25 AU25 S_DQSP0 S_DQSP1 S_DQSP4 AV30 AW26 AV22 SATA_Rp3 / PERp6_L0 SATA_Tn0 / PETn6_L3 E5 15 S_DQ32 S_DQ33 SA_DQ5 AY23 AW23 AH60 S_DQSP5 SA_CA9 SA_CA8 AW18 AU36 AY37 SATA_Tn1 / PETn6_L2 SATA_Tn2 / PETn6_L1 A17 14 S_DQ34 S_DQ35 S_DQ36 AY21 AW21 AV23 SA_CA7 SA_CAA7 SA_CAA6 AP35 AW41 AU41 SATA_Tn3 / PETn6_L0 SATA_Tp0 / PETp6_L3 C17 A15 S_DQ37 S_DQ38 S_DQ39 AU23 AV21 AU21 SA_CA0 SA_CAA9 SA_CAA8 AR35 AV42 AU42 SATA_Tp1 / PETp6_L2 SATA_Tp2 / PETp6_L1 17 C15 S_DQ40 S_DQ41 AY19 AW19 SA_CA5 NOT USED AR38 AP36 SATA_Tp3 / PETp6_L0 D17 S_DQ42 AY17 NOT USED AU39 SATA0GP / GPIO34 V1 S_DQ43 AW17 SA_CAA0 AR36 SATA1GP / GPIO35 U1 SA_DQ6 AK61 SA_CAA2 AV40 SATA2GP / GPIO36 V6 S_DQ44 AV19 SA_CAA4 AW39 SATA3GP / GPIO37 AC1 S_DQ45 AU19 SA_CAA3 AY39 SATALED# U3 S_DQ46 AV17 SA_CAA1 AU40 S_CA4 AL35 S_DQ47 AU17 SA_ODT0 AP32 S_CA6 AM36 SA_DQ7 AK60 SA_CA3 AY34 S_CAA5 AU49 SA_DQ8 AM63 SA_CA2 AW34 S_CA1 AM33 SA_DQ9 AM62 SATA_IREF A12 S_CK#0 AM38 SA_DQSN0 AJ61 SATA_RCOMP C12 S_CK#1 AK38 SA_DQSN1 SA_DQSN4 SA_DQSN5 S_DQSN0 S_DQSN1 S_DQSN4 S_DQSN5 SA_DQSP0 SA_DQSP1 SA_DQSP4 SA_DQSP5 AN62 AV57 AV53 AW30 AV26 AW22 AV18 AJ62 AN61 AW57 AW53 SATA_Rn0 / PERn6_L3 SATA_Rn1 / PERn6_L2 SATA_Rn2 / PERn6_L1 SATA_Rn3 / PERn6_L0 SATA_Rp0 / PERp6_L3 SATA_Rp1 / PERp6_L2 SATA_Rp2 / PERp6_L1 J5 J8 J6 F5 H5 H8 H6 S_CK0 S_CK1 S_CKE0 S_CKE1 S_CKE2 S_CKE3 S_CS#0 S_CS#1 SA_DQ16 SA_DQ17 SA_DQ26 AN38 AL38 AY49 AU50 AW49 AV50 AM32 AK32 AP58 AR58 AM54 Daashee Volume 1 of 2 July Order No.:

117 Processor all and Sgnal Informaon Processors SA_DQ27 AK54 S_DQ28 AK26 SA_DQSP7 AL49 SA_DQ28 AL55 S_DQ29 AM26 S_DQSP2 AM28 SA_DQ29 AK55 S_DQ30 AK25 S_DQSP3 AM25 SA_DQ30 AR54 S_DQ31 AL25 S_DQSP6 AM21 SA_DQ31 AN54 S_DQ48 AR21 S_DQSP7 AM18 SA_DQ48 AK40 S_DQ49 AR22 S_CA9 AP40 SA_DQ49 AK42 SA_DQ21 AK58 S_CA8 AR40 SA_DQ50 AM43 S_DQ50 AL21 S_CA7 AK36 SA_DQ51 AM45 S_DQ51 AM22 S_CAA7 AV47 SA_DQ18 AM57 S_DQ52 AN22 S_CAA6 AU47 SA_DQ52 AK45 S_DQ53 AP21 S_CA0 AK33 SA_DQ53 AK43 S_DQ54 AK21 S_CAA9 AR46 SA_DQ54 AM40 S_DQ55 AK22 S_CAA8 AP46 SA_DQ55 AM42 S_DQ56 AN20 S_CA5 AP42 SA_DQ56 AM46 S_DQ57 AR20 NOT USED AR42 SA_DQ57 AK46 S_DQ58 AK18 NOT USED AR45 SA_DQ58 AM49 S_DQ59 AL18 S_CAA0 AP45 SA_DQ59 AK49 SA_DQ22 AR57 S_CAA2 AW46 SA_DQ60 AM48 S_DQ60 AK20 S_CAA4 AY46 SA_DQ61 AK48 S_DQ61 AM20 S_CAA3 AY47 SA_DQ19 AK57 S_DQ62 AR18 S_CAA1 AU46 SA_DQ62 AM51 S_DQ63 AP18 S_ODT0 AL32 SA_DQ63 AK51 SA_DQ23 AN57 S_CA3 AM35 S_DQ16 AM29 SA_DQ24 AP55 S_CA2 AK35 S_DQ17 S_DQ18 S_DQ19 AK29 AL28 AK28 SA_DQ25 SA_DQSN2 SA_DQSN3 AR55 AM58 AM55 SDIO_CLK / GPIO64 SDIO_CMD / GPIO65 E3 F4 S_DQ20 AR29 SA_DQSN6 AL43 SDIO_D0 / GPIO66 D3 S_DQ21 AN29 SA_DQSN7 AL48 SDIO_D1 / GPIO67 E4 S_DQ22 AR28 S_DQSN2 AN28 SDIO_D2 / GPIO68 C3 S_DQ23 AP28 S_DQSN3 AN25 SDIO_D3 / GPIO69 E2 SA_DQ20 S_DQ24 S_DQ25 S_DQ26 S_DQ27 AL58 AN26 AR26 AR25 AP25 S_DQSN6 S_DQSN7 SA_DQSP2 SA_DQSP3 SA_DQSP6 AN21 AN18 AN58 AN55 AL42 SDIO_POWER_EN / GPIO70 SERIRQ SLP_A# SLP_LAN# C4 T4 AL5 AJ7 July 2014 Daashee Volume 1 of 2 Order No.:

118 Processors Processor all and Sgnal Informaon SLP_S0# SLP_S3# SLP_S4# SLP_S5# / GPIO63 SLP_SUS# SLP_WLAN# / GPIO29 SM_DRAMRST# SM_PG_CNTL1 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 SMALERT# / GPIO11 SMCLK SMDATA AF3 AT4 AJ6 AP5 AP4 AM5 AV15 AV61 AU60 AV60 AU61 AP49 AR51 AP51 AN2 AP2 AH1 SUS_STAT# / GPIO61 SUSACK# SUSCLK / GPIO62 SUSWARN# / SUSPWRDNACK / GPIO30 SYS_PWROK SYS_RESET# TD_IREF TESTLOW_AK8 TESTLOW_AL8 TESTLOW_C34 TESTLOW_C35 THERMTRIP# UART0_CTS# / GPIO94 UART0_RTS# / GPIO93 UART0_RXD / GPIO91 AG4 AK2 AE6 AV4 AG2 AC3 12 AK8 AL8 C34 C35 D60 G1 J2 J1 US2p2 US2p3 US2p4 US2p5 US2p6 US2p7 US3Rn1 US3Rn2 US3Rp1 US3Rp2 US3Tn1 US3Tn2 US3Tp1 US3Tp2 USRIAS USRIAS# AP8 AT10 AL15 AN13 AN11 AP13 G20 E18 H20 F18 C A33 AJ11 AJ10 F59 A57 SML0ALERT# / GPIO60 SML0CLK SML0DATA SML1ALERT# / PCHHOT# / GPIO73 SML1CLK / GPIO75 SML1DATA / GPIO74 SPI_CLK SPI_CS0# SPI_CS1# SPI_CS2# SPI_IO2 SPI_IO3 SPI_MISO SPI_MOSI SPKR / GPIO81 SRTCRST# AL2 AN1 AK1 AU4 AU3 AH3 AA3 Y7 Y4 AC2 Y6 AF1 AA4 AA2 V2 AV6 UART0_TXD / GPIO92 UART1_CTS# / GPIO3 UART1_RST# / GPIO2 UART1_RXD / GPIO0 UART1_TXD / GPIO1 US2n0 US2n1 US2n2 US2n3 US2n4 US2n5 US2n6 US2n7 US2p0 US2p1 K3 J4 J3 K4 G2 AN8 AR7 AR8 AR10 AM15 AM13 AP11 AR13 AM8 AT7 AD57 AG57 C24 C28 C32 C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 Daashee Volume 1 of 2 July Order No.:

119 Processor all and Sgnal Informaon Processors E37 G55 CLK J17 E39 G57 CLK T21 E41 H23 CLK R21 E43 J23 DSW3_3 AH10 E45 K23 HDA AH14 E47 K57 HSIO M9 E49 L22 HSIO K9 E51 M23 HSIO L10 E53 M57 IO_OUT A59 E55 P57 VCOMP_OUT E20 E57 U57 RTC AG10 F24 W57 SATA3PLL 11 F28 _SENSE E63 SDIO U8 F32 1_05 P9 SDIO T9 F36 1_05 N8 SPI Y8 F40 1_05 AE8 ST AC22 F44 1_05 AF22 ST AE22 F48 1_05 H11 ST AE23 F52 1_05 H15 ST_PWRGD 59 F56 1_05 J11 SUS3_3 AH11 G23 1_05 AG16 SUS3_3 AA9 G25 1_05 AG17 SUS3_3 AC9 G27 3_3 V8 SUS3_3 AE20 G29 3_3 W9 SUS3_3 AE21 G31 3_3 K14 TS1_5 J15 G33 3_3 K16 US3PLL 18 G35 ACLKPLL A20 VDDQ AH26 G37 APLL AA21 VDDQ AJ31 G39 APLL W21 VDDQ AJ33 G41 ASW AE9 VDDQ AJ37 G43 ASW AF9 VDDQ AN33 G45 ASW AG8 VDDQ AP43 G47 ASW AG13 VDDQ AR48 G49 ASW AG14 VDDQ AY35 G51 CLK J18 VDDQ AY40 G53 CLK K19 VDDQ AY44 July 2014 Daashee Volume 1 of 2 Order No.:

120 Processors Processor all and Sgnal Informaon VDDQ AY50 C39 AJ23 VIDALERT# L62 AF11 AJ25 VIDSCLK N63 AF12 AJ27 VIDSOUT L63 AF14 AJ29 VR_EN F60 AF15 AJ35 VR_READY C59 AF17 AJ39 P62 AF18 AJ41 D63 AG21 AJ43 P22 AG23 AJ45 N21 AG1 AJ47 A11 AG11 AJ50 A14 AG60 AJ52 A18 AG61 AJ54 A24 AG62 AJ56 A28 AG63 AJ58 A32 AH17 AJ60 A36 AH19 AJ63 A40 AH20 AK23 A48 AH22 AK3 A52 AH24 AK52 A56 AH28 AL10 AA1 AH30 AL13 A44 AH32 AL17 AA58 AH34 AL20 A10 AH36 AL22 A20 AH38 AL23 AE5 AH40 AL26 A22 AH42 AL29 A7 AH44 AL31 AC61 AH49 AL33 AD3 AH51 AL36 AD63 AH53 AL39 AE10 AH55 AL40 AD21 AH57 AL45 AE58 AJ13 AL46 AR43 AJ14 AL51 Daashee Volume 1 of 2 July Order No.:

121 Processor all and Sgnal Informaon Processors AL52 AP3 AU28 AL54 AP31 AU30 AL57 AP38 AU33 AL60 AP39 AU51 AL61 AP52 AU53 AM1 AP54 AU55 AM17 AP57 AU57 AM23 AR11 AU59 AM31 AR15 AV14 AM52 AR17 D62 AN17 AR23 AV16 AN23 AR31 AV20 AN31 AR33 AV24 AN32 AR39 AV28 AN35 AP48 AV33 AN36 AR49 AV34 AN39 AR5 AV36 AN40 AR52 AV39 AN42 AT13 AV41 AN43 AT35 AV43 AN45 AT37 AV46 AN46 AT40 AV49 AN48 AT42 AV51 AN49 AT43 AV55 AN51 AT46 AV59 AN52 AT49 AV8 AN60 AT61 AW16 AN63 AT62 AW24 AN7 AT63 AW33 AP10 AU1 AW35 AP17 AU16 AW37 AP20 AU18 AW4 AP22 AU20 AW40 AP23 AU22 AW42 AP26 AU24 AW44 AP29 AU26 AW47 July 2014 Daashee Volume 1 of 2 Order No.:

122 Processors Processor all and Sgnal Informaon AW50 C25 F42 AW51 C27 F20 AW59 D12 D5 AW60 D14 F26 AY11 D18 F30 AY16 D21 F34 AY18 D23 F38 AY22 D25 G6 AY24 D26 F46 AY26 D27 F50 AY30 D29 F54 AY33 D2 F58 AY51 D30 F61 AY53 D31 G18 AY57 D33 G22 AY59 D34 G3 AY6 D35 G5 AY4 D37 G8 20 D38 H13 24 D39 H17 26 D41 H57 28 D42 J10 32 D43 J22 C38 D45 J59 36 D46 J63 4 D47 K1 40 D49 K12 44 D50 R22 C14 D51 L13 48 D53 L15 52 D54 L17 56 D55 L18 60 D57 L20 C11 D59 L58 C18 E11 L61 C20 E17 L7 Daashee Volume 1 of 2 July Order No.:

123 Processor all and Sgnal Informaon Processors _SENSE WAKE# XTAL24_IN XTAL24_OUT M22 N10 N3 C57 P59 P63 R10 R8 T1 T58 D8 U20 U22 U61 V10 V3 V7 W20 Y10 U9 Y59 Y63 W22 V58 AH46 V23 AH16 E62 AJ5 A25 25 July 2014 Daashee Volume 1 of 2 Order No.: