Introducing the Dezyne Modelling Language
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1 Introducing the Dezyne Modelling Language Bits & Chips Smart Systems, 20 November 2014 Paul Hoogendijk.
2 Software Controlled Systems
3 Software Controlled Systems Event driven Concurrent, complex High cost-of-non-quality Field defects (SLA) and field updates Difficult and expensive to test Many scenario's: events interleaving, exceptions (errors) Dependency on hardware availability Managing complexity is key
4 designer/engineer wants Trust
5 designer/engineer wants Trust proper spec?
6 designer/engineer wants Trust proper spec? clean & clear architecture/design?
7 designer/engineer wants Trust proper spec? clean & clear architecture/design? code implements architecture/design?
8 designer/engineer wants Trust proper spec? clean & clear architecture/design? code implements architecture/design? code quality and complexity?
9 designer/engineer wants Trust proper spec? clean & clear architecture/design? code implements architecture/design? code quality and complexity? unit tests?
10 designer/engineer wants Trust proper spec? clean & clear architecture/design? code implements architecture/design? code quality and complexity? unit tests? end-to-end tests?
11 designer/engineer wants Trust proper spec? clean & clear architecture/design? code implements architecture/design? code quality and complexity? unit tests? end-to-end tests? test coverage, including all exceptions?
12 Title Body
13
14
15 Title Body
16 Title Body
17 Create. Dezyne Modelling Language System models subcomponents declaration bindings between ports Component models provides & requires ports declaration behaviour Interface models in & out events declaration behaviour
18
19
20 Components, ports and bindings
21 Components, ports and bindings
22 Interfaces: events and behaviour
23 Interfaces: events and behaviour
24 Interfaces: in and out events
25 Interfaces: in and out events
26 Component: ports and behaviour
27 Component: ports and behaviour
28 Title Body
29 Explore: Simulation and Views Sequence diagrams shown are simulator runs User selects next events from list of possible events Exploring interfaces proper specification? Exploring components use cases present?
30 Explore: Simulation and Views
31 Title Body
32 Verify: discover hidden defects Automatic full simulation based on Formal Methods For all possible execution scenarios for component check Adheres to its interfaces No deadlock No livelock Handles race conditions correctly If issue found: trace generated leading to problem 100% coverage while no test code written (!)
33 Verify: discover hidden defects Automatic full simulation based on Formal Methods For all possible execution scenarios for component check Adheres to its interfaces No deadlock No livelock Handles race conditions correctly If issue found: trace generated leading to problem 100% coverage while no test code written (!)
34 Title Body
35 Trust: code generation Efficient and readable code I could have written that 100% of code is generated No (foreign) code snippets in models Easy integration with external code Via an Dezyne Interface makes assumption about external code explicit Thin wrapper layer Connect to: Legacy software Hardware drivers Non Dezyne subsystem...
36 Trust: code generation (cont.) Due to Create Explore Verify cycle: Validated: proper specification (interfaces) all use cases present (components) Verified: All component implement their specification correctly No deadlock, no livelock and handles all races correctly Code that can be trusted
37 Trust based on hard evidence
38 9 Questions? stand 35
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