LTC3891 Low I Q, 60V Synchronous Step-Down Controller APPLICATIONS TYPICAL APPLICATION

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1 Low I Q, 60V Synchronous Step-Down Controller FEATURES n Wide Range: 4V to 60V (65V Abs Max) n Low Operating I Q : 50μA n Wide Output Voltage Range: 0.8V 24V n R SENSE or DCR Current Sensing n Phase-Lockable Frequency (75kHz to 750kHz) n Programmable Fixed Frequency (50kHz to 900kHz) n Selectable Continuous, Pulse-Skipping or Low Ripple Burst Mode Operation at Light Load n Selectable Current Limit n Very Low Dropout Operation: 99% Duty Cycle n Adjustable Output Voltage Soft-Start or Tracking n Power Good Output Voltage Monitor n Output Overvoltage Protection n Low Shutdown I Q : < 14μA n Internal LDO Powers Gate Drive from or EXTV CC n No Current Foldback During Start-Up n Small 20-Pin 3mm 4mm QFN and TSSOP Packages APPLICATIONS n Automotive Always-On Systems n Battery Powered Digital Devices n Distributed DC Power Systems TYPICAL APPLICATION High Efficiency 3.3V Step-Down Converter DESCRIPTION The LTC 3891 is a high performance step-down switching regulator DC/DC controller that drives an all N-channel synchronous power MOSFET stage. A constant frequency current mode architecture allows a phase-lockable frequency of up to 750kHz. The 50μA no-load quiescent current extends operating run time in battery-powered systems. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The features a precision 0.8V reference and power good output indicator. A wide 4V to 60V input supply range encompasses a wide range of intermediate bus voltages and battery chemistries. The output voltage of the can be programmed between 0.8V to 24V. The TRACK/SS pin ramps the output voltages during start-up. Current foldback limits MOSFET heat dissipation during short-circuit conditions. The PLLIN/MODE pin selects among Burst Mode operation, pulse-skipping mode, or continuous conduction mode at light loads. L, LT, LTC, LTM, OPTI-LOOP, Burst Mode, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents, including , , , , , Efficiency and Power Loss vs Output Current 4V TO 60V 2200pF 41.2k 100pF 22µF 10k 0.1µF FREQ ITH TRACK/SS INTV CC TG BOOST SW BG SENSE + SENSE V FB PGOOD 2.2µF 0.1µF 4.7µH 100k INTV CC 8mΩ 100k 31.6k 150µF 3.3V 5A EFFICIENCY (%) 100 = 12V = 3.3V OUTPUT CURRENT (A) 3891 TA01b POWER LOSS (mw) 3891 TA01a 1

2 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage ( ) V to 65V Topside Driver Voltage (BOOST) V to 71V Switch Voltage (SW)... 5V to 65V (BOOST-SW) V to 6V RUN V to 8V Maximum Current Sourced into Pin from Source > 8V...100μA SENSE +, SENSE Voltages V to 28V PLLIN/MODE, INTV CC Voltages V to 6V I LIM, FREQ Voltages V to INTV CC EXTV CC V to 14V ITH, V FB Voltages V to 6V PGOOD Voltage V to 6V TRACK/SS Voltage V to 6V Operating Junction Temperature Range (Notes 2, 3) E, I C to 125 C H C to 150 C MP C to 150 C Maximum Junction Temperature (Notes 2, 3) E, I C H, MP C Storage Temperature Range C to 150 C PIN CONFIGURATION PLLIN/MODE RUN SENSE SENSE TOP VIEW FREQ TRACK/SS ILIM V FB ITH PGOOD TG UDC PACKAGE 20-LEAD (3mm 4mm) PLASTIC QFN T JMAX = 150 C, θ JA = 43 C/W EXPOSED PAD (PIN 21) IS, MUST BE SOLDERED TO PCB PGND EXTV CC INTV CC BG BOOST SW TRACK/SS FREQ PLLIN/MODE RUN SENSE SENSE + V FB ITH TOP VIEW I LIM PGND 17 EXTV CC 16 INTV CC 15 BG 14 BOOST 13 SW 12 TG 11 PGOOD FE PACKAGE 20-LEAD PLASTIC TSSOP T JMAX = 150 C, θ JA = 38 C/W EXPOSED PAD (PIN 21) IS, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE EUDC#PBF EUDC#TRPBF LFXV 20-Lead (3mm 4mm) Plastic QFN 40 C to 125 C IUDC#PBF IUDC#TRPBF LFXV 20-Lead (3mm 4mm) Plastic QFN 40 C to 125 C HUDC#PBF HUDC#TRPBF LFXV 20-Lead (3mm 4mm) Plastic QFN 40 C to 150 C MPUDC#PBF MPUDC#TRPBF LFXV 20-Lead (3mm 4mm) Plastic QFN 55 C to 150 C 2

3 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE EFE#PBF EFE#TRPBF FE 20-Lead Plastic TSSOP 40 C to 125 C IFE#PBF IFE#TRPBF FE 20-Lead Plastic TSSOP 40 C to 125 C HFE#PBF HFE#TRPBF FE 20-Lead Plastic TSSOP 40 C to 150 C MPFE#PBF MPFE#TRPBF FE 20-Lead Plastic TSSOP 55 C to 150 C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: For more information on tape and reel specifications, go to: ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at T A = 25 C (Note 2), = 12V, V RUN = 5V, EXTV CC = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supply Operating Voltage Range 4 60 V V FB Regulated Feedback Voltage (Note 4); I TH Voltage = 1.2V 40 C to 85 C E, I H, MP I FB Feedback Current (Note 4) ±5 ±50 na V REFLNREG Reference Voltage Line Regulation (Note 4); = 4.5V to 60V %/V V LOADREG Output Voltage Load Regulation (Note 4) l % Measured in Servo Loop; I TH Voltage = 1.2V to 0.7V (Note 4) l % Measured in Servo Loop; I TH Voltage = 1.2V to 2V g m Transconductance Amplifier g m (Note 4); I TH = 1.2V; Sink/Source 5µA 2 mmho I Q Input DC Supply Current (Note 5) Pulse Skip or Forced Continuous Mode V FB = 0.83V (No Load) 2 ma Sleep Mode V FB = 0.83V (No Load) µa Shutdown RUN = 0V µa UVLO Undervoltage Lockout INTV CC Ramping Up INTV CC Ramping Down l l l l 3.6 V OVL Feedback Overvoltage Protection Measured at V FB Relative to Regulated V FB % I + SENSE SENSE + Pin Current ±1 µa I SENSE SENSE Pins Current V SENSE < INTV CC 0.5V V SENSE > INTV CC + 0.5V V V V V V ±2 µa µa DF MAX Maximum Duty Factor In Dropout % I TRACK/SS Soft-Start Charge Current V TRACK = 0V µa V RUN On RUN Pin On Threshold V RUN Rising l V V RUN Hyst RUN Pin Hysteresis 50 mv V SENSE(MAX) Maximum Current Sense Threshold V FB = 0.7V, V SENSE = 3.3V, I LIM = 0 V FB = 0.7V, V SENSE = 3.3V, I LIM = INTV CC V FB = 0.7V, V SENSE = 3.3V, I LIM = FLOAT l l l mv mv mv 3

4 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at T A = 25 C (Note 2), = 12V, V RUN = 5V, EXTV CC = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Gate Driver TG BG TG t r TG t f BG t r BG t f TG/BG t 1D BG/TG t 1D 4 Pull-Up On-Resistance Pull-Down On-Resistance Pull-Up On-Resistance Pull-Down On-Resistance TG Transition Time: Rise Time Fall Time BG Transition Time: Rise Time Fall Time Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time (Note 6) C LOAD = 3300pF C LOAD = 3300pF (Note 6) C LOAD = 3300pF C LOAD = 3300pF C LOAD = 3300pF 30 ns C LOAD = 3300pF 30 ns t ON(MIN) Minimum On-Time (Note 7) 95 ns INTV CC Linear Regulator TVCCVIN Internal V CC Voltage 6V < < 60V, V EXTVCC = 0V V V LDOVIN INTV CC Load Regulation I CC = 0mA to 50mA, V EXTVCC = 0V % TVCCEXT Internal V CC Voltage 6V < V EXTVCC < 13V V V LDOEXT INTV CC Load Regulation I CC = 0mA to 50mA, % V EXTVCC = 8.5V V EXTVCC EXTV CC Switchover Voltage I CC = 0mA to 50mA, V EXTV CC Ramping Positive V LDOHYS EXTV CC Hysteresis 250 mv Oscillator and Phase-Locked Loop f 25kΩ Programmable Frequency R FREQ = 25k; 105 khz PLLIN/MODE = DC Voltage f 65kΩ Programmable Frequency R FREQ = 65k; khz PLLIN/MODE = DC Voltage f 105kΩ Programmable Frequency R FREQ =105k; 835 khz PLLIN/MODE = DC Voltage f LOW Low Fixed Frequency V FREQ = 0V; khz PLLIN/MODE = DC Voltage f HIGH High Fixed Frequency V FREQ = INTV CC ; khz PLLIN/MODE = DC Voltage f SYNC Synchronizable Frequency PLLIN/MODE = External Clock l khz PGOOD1 Output V PGL PGOOD Voltage Low I PGOOD = 2mA V I PGOOD PGOOD Leakage Current V PGOOD = 5V ±1 µa V PG PGOOD Trip Level V FB with Respect to Set Regulated Voltage V FB Ramping Negative % Hysteresis 2.5 % V FB Ramping Positive % Hysteresis 2.5 % t PG Delay for Reporting a Fault 25 µs Ω Ω Ω Ω ns ns ns ns

5 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The is tested under pulsed load conditions such that T J T A. The E is guaranteed to meet performance specifications from 0 C to 85 C. Specifications over the 40 C to 125 C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The I is guaranteed over the 40 C to 125 C operating junction temperature range, the H is guaranteed over the 40 C to 150 C operating junction temperature range and the MP is tested and guaranteed over the 55 C to 150 C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125 C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: The junction temperature (T J, in C) is calculated from the ambient temperature (T A, in C) and power dissipation (P D, in Watts) according to the formula: T J = T A + (P D θ JA ), where θ JA is 43 C/W for the QFN or 38 C/W for the TSSOP. Note 4: The is tested in a feedback loop that servos V ITH to a specified voltage and measures the resultant V FB. The specification at 85 C is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125 C for the E/I, 150 C for the H/MP). For the MP, the specification at 40 C is not tested in production and is assured by design, characterization and correlation to production testing at 55 C. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of I MAX (See Minimum On-Time Considerations in the Applications Information section). TYPICAL PERFORMANCE CHARACTERISTICS EFFICIENCY (%) Efficiency and Power Loss vs Output Current Efficiency vs Output Current Efficiency vs Input Voltage = 12V = 3.3V FCM LOSS 50 BURST LOSS PULSE-SKIPPING 40 LOSS FCM EFFICIENCY 1 10 PULSE-SKIPPING 0 EFFICIENCY OUTPUT CURRENT (A) FIGURE 12 CIRCUIT BURST EFFICIENCY 3891 G POWER LOSS (mw) EFFICIENCY (%) = 8.5V = 3.3V 20 Burst Mode OPERATION 10 = 12V OUTPUT CURRENT (A) FIGURES 12, 14 CIRCUITS 3891 G02 EFFICIENCY (%) = 3.3V = 8.5V 82 I LOAD = 2A INPUT VOLTAGE (V) FIGURES 12, 14 CIRCUITS 3891 G03 5

6 TYPICAL PERFORMANCE CHARACTERISTICS Load Step Burst Mode Operation Load Step Pulse-Skipping Mode Load Step Forced Continuous Mode 100mV/DIV AC- COUPLED 100mV/DIV AC- COUPLED 100mV/DIV AC- COUPLED I L 2A/DIV I L 2A/DIV I L 2A/DIV 50µs/DIV LOAD STEP = 100mA TO 3A = 12V = 3.3V FIGURE 12 CIRCUIT 3891 G04 50µs/DIV LOAD STEP = 100mA TO 3A = 12V = 3.3V FIGURE 12 CIRCUIT 3891 G05 50µs/DIV LOAD STEP = 100mA TO 3A = 12V = 3.3V FIGURE 12 CIRCUIT 3891 G06 Inductor Current at Light Load Soft Start-Up Tracking Start-Up FORCED CONTINUOUS MODE = 8.5V 2V/DIV MASTER 2V/DIV Burst Mode OPERATION 1A/DIV = 3.3V 2V/DIV 2V/DIV PULSE-SKIPPING MODE = 12V = 3.3V I LOAD = 200µA 5µs/DIV 3891 G07 2ms/DIV FIGURES 12, 14 CIRCUITS 3891 G08 2ms/DIV 3891 G09 SUPPLY CURRENT (µa) Total Input Supply Current vs Input Voltage 300µA LOAD NO LOAD FIGURE 12 CIRCUIT INPUT VOLTAGE (V) EXTV CC AND INTV CC VOLTAGE (V) EXTV CC Switchover and INTV CC Voltages vs Temperature INTV CC EXTV CC RISING EXTV CC FALLING TEMPERATURE ( C) INTV CC VOLTAGE (V) INTV CC Line Regulation I LOAD = 10mA INPUT VOLTAGE (V) 3891 G G G12 6

7 TYPICAL PERFORMANCE CHARACTERISTICS CURRENT SENSE THESHOLD (mv) Maximum Current Sense Voltage vs I TH Voltage 5% DUTY CYCLE PULSE-SKIPPING MODE Burst Mode OPERATION FORCED CONTINUOUS MODE V ITH (V) I LIM = GND I LIM = INTV CC I LIM = FLOAT SENSE CURRENT (µa) SENSE Pin Input Bias Current V SENSE COMMON MODE VOLTAGE (V) MAXIMUM CURRENT SENSE VOLTAGE (mv) Maximum Current Sense Threshold vs Duty Cycle I LIM = FLOAT I LIM = INTV CC I LIM = GND DUTY CYCLE (%) 3891 G G G15 MAXIMUM CURRENT SENSE VOLTAGE (mv) Foldback Current Limit Quiescent Current vs Temperature INTV CC vs Load Current I LIM = FLOAT I LIM = INTV CC I LIM = GND QUIESCENT CURRENT (µa) 80 = 12V FEEDBACK VOLTAGE (MV) TEMPERATURE ( C) INTV CC VOLTAGE (V) 5.50 = 12V EXTV CC = 0V EXTV CC = 8.5V EXTV CC = 5V LOAD CURRENT (ma) 3891 G G G TRACK/SS Pull-Up Current vs Temperature 1.30 Shutdown (RUN) Threshold vs Temperature 808 Regulated Feedback Voltage vs Temperature TRACK/SS CURRENT (µa) RUN PIN VOLTAGE (V) RUN FALLING RUN RISING REGULATED FEEDBACK VOLTAGE (mv) TEMPERATURE ( C) TEMPERATURE ( C) TEMPERATURE ( C) 3891 G G G21 7

8 TYPICAL PERFORMANCE CHARACTERISTICS 800 SENSE Pin Input Bias Current vs Temperature 30 Shutdown Current vs Input Voltage 600 Oscillator Frequency vs Temperature SENSE CURRENT (µa) > INTV CC + 0.5V < INTV CC 0.5V SHUTDOWN CURRENT (µa) FREQUENCY (khz) FREQ = INTV CC FREQ = GND TEMPERATURE ( C) INPUT VOLTAGE (V) TEMPERATURE ( C) 3891 G G G Undervoltage Lockout Threshold vs Temperature 356 Oscillator Frequency vs Input Voltage FREQ = GND Shutdown Current vs Temperature 22 = 12V INTV CC VOLTAGE (V) RISING FALLING OSCILLATOR FREQUENCY (khz) SHUTDOWN CURRENT (µa) TEMPERATURE ( C) INPUT VOLTAGE (V) TEMPERATURE ( C) 3891 G G G27 8

9 PIN FUNCTIONS (QFN/eTSSOP) PLLIN/MODE (Pin 1/Pin 3): External Synchronization Input to Phase Detector and Forced Continuous Mode Input. When an external clock is applied to this pin, the phase-locked loop will force the rising TG signal to be synchronized with the rising edge of the external clock, and the regulator operates in forced continuous mode. When not synchronizing to an external clock, this input determines how the operates at light loads. Pulling this pin to ground selects Burst Mode operation. An internal 100k resistor to ground also invokes Burst Mode operation when the pin is floated. Tying this pin to INTV CC forces continuous inductor current operation. Tying this pin to a voltage greater than 1.2V and less than INTV CC 1.3V selects pulse-skipping operation. (Pins 2, 3, Exposed Pad Pin 21/Pins 4, 5, Exposed Pad Pin 21): Small-signal ground, must be routed separately from high current grounds to the common ( ) terminals of the C IN capacitor. Pins 2, 3/4, 5, must both be electrically connected to small signal ground for proper operation.the exposed pad must be soldered to PCB ground for rated thermal performance. RUN (Pin 4/Pin 6): Digital Run Control Input. Forcing this pin below 1.16V shuts down the controller. Forcing this pin below 0.7V shuts down the entire, reducing quiescent current to approximately 14µA. SENSE (Pin 5/Pin 7): The ( ) Input to the Differential Current Comparator. When greater than INTV CC 0.5V, the SENSE pin supplies power to the current comparator. SENSE + (Pin 6/Pin 8): The (+) input to the differential current comparator is normally connected to DCR sensing network or current sensing resistor. The ITH pin voltage and controlled offsets between the SENSE and SENSE + pins in conjunction with R SENSE set the current trip threshold. V FB (Pin 7/Pin 9): Receives the remotely sensed feedback voltage from an external resistive divider across the output. ITH (Pin 8/Pin 10): Error Amplifier Outputs and Switching Regulator Compensation Point. The current comparator trip point increases with this control voltage. PGOOD (Pin 9/Pin 11): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on the V FB pin is not within 10% of its set point. TG (Pin 10/Pin 12): High Current Gate Drives for Top N-channel MOSFET. This is the output of floating driver with a voltage swing equal to INTV CC superimposed on the switch node voltage SW. SW (Pin 11/ Pin 13): Switch Node Connection to Inductor. BOOST (Pin 12/Pin 14): Bootstrapped Supply to the Topside Floating Driver. A capacitor is connected between the BOOST and SW pin and a Schottky diode is tied between the BOOST and INTV CC pins. Voltage swing at the BOOST pin is from INTV CC to ( + INTV CC ). BG (Pin 13/Pin 15): High Current Gate Drive for Bottom (Synchronous) N-channel MOSFET. Voltage swing at this pin is from ground to INTV CC. INTV CC (Pin 14/Pin 16): Output of the Internal Linear Low Dropout Regulator. The driver and control circuits are powered from this voltage source. Must be decoupled to PGND with a minimum of 2.2µF ceramic or other low ESR capacitor. Do not use the INTV CC pin for any other purpose. EXTV CC (Pin 15/Pin 17): External Power Input to an Internal LDO Connected to INTV CC. This LDO supplies INTV CC power, bypassing the internal LDO powered from whenever EXTV CC is higher than 4.7V. See EXTV CC Connection in the Applications Information section. Do not float or exceed 14V on this pin. PGND (Pin 16/Pin 18): Driver Power Ground. Connects to the source of bottom (synchronous) N-channel MOSFET and the ( ) terminal of C IN. (Pin 17/Pin 19): Main Supply Pin. A bypass capacitor should be tied between this pin and the pins. I LIM (Pin 18/Pin 20): Current Comparator Sense Voltage Range Inputs. Tying this pin to, FLOAT or INTV CC sets the maximum current sense threshold to one of three different levels for the comparator. 9

10 PIN FUNCTIONS TRACK/SS (Pin 19/Pin 1): External Tracking and Soft- Start Input. The regulates the V FB voltage to the smaller of 0.8V or the voltage on the TRACK/SS pin. An internal 10μA pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output voltage. Alternatively, a resistor divider on another voltage supply connected to this pin allows the output to track another supply during start-up. FREQ (Pin 20/Pin 2): The frequency control pin for the internal VCO. Connecting the pin to GND forces the VCO to a fixed low frequency of 350kHz. Connecting the pin to INTV CC forces the VCO to a fixed high frequency of 535kHz. Other frequencies between 50kHz and 900kHz can be programmed by using a resistor between FREQ and GND. An internal 20µA pull-up current develops the voltage to be used by the VCO to control the frequency. FUNCTIONAL DIAGRAM INTV CC PGOOD V BOOST D B + V FB 0.72V S Q DROP OUT DET BOT TOP ON TOP TG SW C B D C IN FREQ 20µA VCO CLK1 CLK2 R Q SHDN BOT INTV CC BG PGND C OUT 0.425V + SWITCH LOGIC SLEEP L R SENSE PLLIN/MODE SYNC DET PFD 2.7V 0.65V ICMP + + 2mV IR SENSE + SENSE SLOPE COMP + + I LIM 100k CURRENT LIMIT EA V TRACK/SS V FB R A R B EXTV CC OV V ITH C C 5.1V LDO EN 5.1V LDO EN 7µA SHDN RST 2(V FB ) FOLDBACK 10µA TRACK/SS C C2 R C 4.7V + 11V SHDN C SS 3891 FD INTV CC RUN 10

11 OPERATION Main Control Loop The uses a constant frequency, current mode step-down architecture. During normal operation, the external top MOSFET is turned on when the clock for that channel sets the RS latch, and is turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP trips and resets the latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier, EA. The error amplifier compares the output voltage feedback signal at the V FB pin (which is generated with an external resistor divider connected across the output voltage,, to ground) to the internal 0.800V reference voltage. When the load current increases, it causes a slight decrease in V FB relative to the reference, which causes the EA to increase the ITH voltage until the average inductor current matches the new load current. After the top MOSFET is turned off each cycle, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current comparator IR, or the beginning of the next clock cycle. INTV CC /EXTV CC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTV CC pin. When the EXTV CC pin is tied to a voltage less than 4.7V, the LDO (low dropout linear regulator) supplies 5.1V from to INTV CC. If EXTV CC is taken above 4.7V, the LDO is turned off and an EXTV CC LDO is turned on. Once enabled, the EXTV CC LDO supplies 5.1V from EXTV CC to INTV CC. Using the EXTV CC pin allows the INTV CC power to be derived from a high efficiency external source such as one of the switching regulator outputs. The top MOSFET driver is biased from the floating bootstrap capacitor, C B, which normally recharges during each cycle through an external diode when the top MOSFET turns off. If the input voltage,, decreases to a voltage close to, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one twelfth of the clock period every tenth cycle to allow C B to recharge. Shutdown and Start-Up (RUN, TRACK/SS Pins) The can be shut down using the RUN pin. Pulling this pin below 1.16V shuts down the main control loop. Pulling the RUN pin below 0.7V disables the controller and most internal circuits, including the INTV CC LDOs. In this state, the draws only 14μA of quiescent current. Releasing the RUN pin allows a small internal current to pull up the pin to enable the controller. The RUN pin has a 7μA pull-up which is designed to be large enough so that the RUN pin can be safely floated (to always enable the controller) without worry of condensation or other small board leakage pulling the pin down. This is ideal for always-on applications where the controller is enabled continuously and never shut down. The RUN pin may be externally pulled up or driven directly by logic. When driving the RUN pin with a low impedance source, do not exceed the absolute maximum rating of 8V. The RUN pin has an internal 11V voltage clamp that allows the RUN pin to be connected through a resistor to a higher voltage (for example, ), so long as the maximum current into the RUN pin does not exceed 100μA. The RUN pin can also be implemented as a UVLO by connecting it to the output of an external resistor divider network off (see Applications Information section). The start-up of the controller s output voltage is controlled by the voltage on the TRACK/SS pin. When the voltage on the TRACK/SS pin is less than the 0.8V internal reference, the regulates the V FB voltage to the TRACK/SS pin voltage instead of the 0.8V reference. This allows the TRACK/SS pin to be used to program a soft-start by connecting an external capacitor from the TRACK/SS pin to. An internal 10μA pull-up current charges this capacitor creating a voltage ramp on the TRACK/SS pin. As the TRACK/SS voltage rises linearly from 0V to 0.8V (and beyond up to 5V), the output voltage rises smoothly from zero to its final value. Alternatively the TRACK/SS pin can be used to cause the start-up of to track that of another supply. Typically, this requires connecting to the TRACK/SS pin an external resistor divider from the other supply to ground (see Applications Information section). 11

12 OPERATION Light Load Current Operation (Burst Mode Operation, Pulse-Skipping or Forced Continuous Mode) (PLLIN/MODE Pin) The can be enabled to enter high efficiency Burst Mode operation, constant frequency pulse-skipping mode, or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/MODE pin to. To select forced continuous operation, tie the PLLIN/MODE pin to INTV CC. To select pulse-skipping mode, tie the PLLIN/MODE pin to a DC voltage greater than 1.2V and less than INTV CC 1.3V. When the controller is enabled for Burst Mode operation, the minimum peak current in the inductor is set to approximately 25% of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.425V, the internal sleep signal goes high (enabling sleep mode) and both external MOSFETs are turned off. The ITH pin is then disconnected from the output of the EA and parked at 0.450V. In sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the draws to only 50μA. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA s output begins to rise. When the output voltage drops enough, the ITH pin is reconnected to the output of the EA, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator, IR, turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation or clocked by an external clock source to use the phase-locked loop (see Frequency Selection and Phase-Locked Loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is deter- 12 mined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry. In forced continuous mode, the output ripple is independent of load current. When the PLLIN/MODE pin is connected for pulse-skipping mode, the operates in PWM pulse-skipping mode at light loads. In this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. At very light loads, the current comparator, ICMP, may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ and PLLIN/MODE Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the can be selected using the FREQ pin. If the PLLIN/MODE pin is not being driven by an external clock source, the FREQ pin can be tied to, tied to INTV CC or programmed through an external resistor. Tying FREQ to selects 350kHz while tying FREQ to INTV CC selects 535kHz. Placing a resistor between FREQ and allows the frequency to be programmed between 50kHz and 900kHz, as shown in Figure 9. A phase-locked loop (PLL) is available on the to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. The

13 OPERATION s phase detector adjusts the voltage (through an internal lowpass filter) of the VCO input to align the turn-on of the controller s external top MOSFET to the rising edge of the synchronizing signal. The VCO input voltage is prebiased to the operating frequency set by the FREQ pin before the external clock is applied. If prebiased near the external clock frequency, the PLL loop only needs to make slight changes to the VCO input in order to synchronize the rising edge of the external clock s to the rising edge of TG. The ability to prebias the loop filter allows the PLL to lock-in rapidly without deviating far from the desired frequency. The typical capture range of the phase-locked loop is from approximately 55kHz to 900kHz, with a guarantee to be between 75kHz and 750kHz. In other words, the s PLL is guaranteed to lock to an external clock source whose frequency is between 75kHz and 750kHz. The typical input clock thresholds on the PLLIN/MODE pin are 1.6V (rising) and 1.2V (falling). Output Overvoltage Protection An overvoltage comparator guards against transient overshoots as well as other more serious conditions that may overvoltage the output. When the V FB pin rises by more than 10% above its regulation point of 0.800V, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Power Good Pin The PGOOD pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the V FB pin voltage is not within ±10% of the 0.8V reference voltage. The PGOOD pin is also pulled low when the RUN pin is low (shut down). When the V FB pin voltage is within the ±10% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6V. Foldback Current When the output voltage falls to less than 70% of its nominal level, foldback current limiting is activated, progressively lowering the peak current limit in proportion to the severity of the overcurrent or short-circuit condition. Foldback current limiting is disabled during the soft-start interval (as long as the V FB voltage is keeping up with the TRACK/SS voltage). 13

14 APPLICATIONS INFORMATION The Typical Application on the first page is a basic application circuit. can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of R SENSE (if R SENSE is used) and inductor value. Next, the power MOSFETs and Schottky diodes are selected. Finally, input and output capacitors are selected. Current Limit Programming The I LIM pin is a tri-level logic input which sets the maximum current limit of the controller. When I LIM is grounded, the maximum current limit threshold voltage of the current comparator is programmed to be 30mV. When I LIM is floated, the maximum current limit threshold is 75mV. When I LIM is tied to INTV CC, the maximum current limit threshold is set to 50mV. SENSE + and SENSE Pins The SENSE + and SENSE pins are the inputs to the current comparators. The common mode voltage range on these pins is 0V to 28V (abs max), enabling the to regulate output voltages up to a nominal 24V (allowing margin for tolerances and transients). The SENSE + pin is high impedance over the full common mode range, drawing at most ±1μA. This high impedance allows the current comparators to be used in inductor DCR sensing. The impedance of the SENSE pin changes depending on the common mode voltage. When SENSE is less than INTV CC 0.5V, a small current of less than 1μA flows out of the pin. When SENSE is above INTV CC + 0.5V, a higher current (~700μA) flows into the pin. Between INTV CC 0.5V and INTV CC + 0.5V, the current transitions from the smaller current to the higher current. 14 Filter components mutual to the sense lines should be placed close to the, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. If inductor DCR sensing is used (Figure 2b), sense resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. TO SENSE FILTER, NEXT TO THE CONTROLLER C OUT 3891 F01 INDUCTOR OR R SENSE Figure 1. Sense Lines Placement with Inductor or Sense Resistor INTV CC BOOST TG SW BG SENSE + SENSE *R1 AND C1 ARE OPTIONAL INTV CC BOOST TG SW BG SENSE + SENSE *PLACE C1 NEAR SENSE PINS C1* R1* PLACE CAPACITOR NEAR SENSE PINS R SENSE (2a) Using a Resistor to Sense Current C1* R2 (R1 R2) C1 = R1 L DCR INDUCTOR L R SENSE(EQ) = DCR DCR R2 R1 + R2 (2b) Using the Inductor DCR to Sense Current Figure 2. Current Sensing Methods 3891 F02a 3891 F02b

15 APPLICATIONS INFORMATION Low Value Resistor Current Sensing A typical sensing circuit using a discrete resistor is shown in Figure 2a. R SENSE is chosen based on the required output current. The current comparator has a maximum threshold V SENSE(MAX) determined by the I LIM setting. The current comparator threshold voltage sets the peak of the inductor current, yielding a maximum average output current, I MAX, equal to the peak value less half the peak-to-peak ripple current, ΔI L. To calculate the sense resistor value, use the equation: R SENSE = V SENSE(MAX) I MAX + DI L 2 To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the Maximum Current Sense Threshold (V SENSE(MAX) ) in the Electrical Characteristics table (30mV, 50mV or 75mV, depending on the state of the I LIM pin). When using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. A curve is provided in the Typical Performance Characteristics section to estimate this reduction in peak inductor current depending upon the operating duty factor. Inductor DCR Sensing For applications requiring the highest possible efficiency at high load currents, the is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 2b. The DCR of the inductor represents the small amount of DC resistance of the copper wire, which can be less than 1mΩ for today s low value, high current inductors. In a high current application requiring such an inductor, power loss through a sense resistor would cost several points of efficiency compared to inductor DCR sensing. If the external (R1 R2) C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the DCR of the inductor must be known. It can be measured using a good RLC meter, but the DCR tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. Using the inductor ripple current value from the Inductor Value Calculation section, the target sense resistor value is: R SENSE(EQUIV) = V SENSE(MAX) I MAX + DI L 2 To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the Maximum Current Sense Threshold (V SENSE(MAX) ) in the Electrical Characteristics table (30mV, 50mV or 75mV, depending on the state of the I LIM pin). Next, determine the DCR of the inductor. When provided, use the manufacturer s maximum value, usually given at 20 C. Increase this value to account for the temperature coefficient of copper resistance, which is approximately 0.4%/ C. A conservative value for T L(MAX) is 100 C. To scale the maximum inductor DCR to the desired sense resistor value (R D ), use the divider ratio: R SENSE(EQUIV) R D = DCR MAX att L(MAX) C1 is usually selected to be in the range of 0.1μF to 0.47μF. This forces R1 R2 to around 2k, reducing error that might have been caused by the SENSE + pin s ±1μA current. 15

16 APPLICATIONS INFORMATION The equivalent resistance R1 R2 is scaled to the temperature inductance and maximum DCR: R1 R2 = L ( DCR at 20 C) C1 The sense resistor values are: R1 = R1 R2 ; R2 = R1 R D R D 1 R D The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: P LOSS R1 = ( (MAX) ) R1 Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. Inductor Value Calculation The operating frequency and inductor selection are interrelated n that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET switching and gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current, ΔI L, decreases with higher inductance or higher frequency and increases with higher : ΔI L = 1 f ( )( L) 1 Accepting larger values of ΔI L allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ΔI L = 0.3(I MAX ). The maximum ΔI L occurs at the maximum input voltage. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by R SENSE. Lower inductor values (higher ΔI L ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance value selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! 16

17 APPLICATIONS INFORMATION Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for the controller: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTV CC voltage. This voltage is typically 5.1V during start-up (see EXTV CC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. Pay close attention to the BV DSS specification for the MOSFETs as well. Selection criteria for the power MOSFETs include the onresistance, R DS(ON), Miller capacitance, C MILLER, input voltage and maximum output current. Miller capacitance, C MILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers datasheet. C MILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in V DS. This result is then multiplied by the ratio of the application applied V DS to the gate charge curve specified V DS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = Synchronous Switch Duty Cycle = The MOSFET power dissipations at maximum output current are given by: P MAIN = ( I MAX ) 2 ( 1+ δ)r DS(ON) + ( ) 2 I MAX R 2 DR 1 + TVCC V THMIN ( )( C MILLER ) 1 V THMIN f ( ) where δ is the temperature dependency of R DS(ON) and R DR (approximately 2Ω) is the effective driver resistance at the MOSFET s Miller threshold voltage. V THMIN is the typical MOSFET minimum threshold voltage. Both MOSFETs have I 2 R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For < 20V the high current efficiency generally improves with larger MOSFETs, while for > 20V the transition losses rapidly increase to the point that the use of a higher R DS(ON) device with lower C MILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1+ δ) is generally given for a MOSFET in the form of a normalized R DS(ON) vs Temperature curve, but δ = 0.005/ C can be used as an approximation for low voltage MOSFETs. A Schottky diode can be inserted in parallel with the bottom MOSFET to conduct during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. C IN and C OUT Selection The selection of C IN is usually based off the worst-case RMS input current. The highest ( )(I OUT ) product needs to be used in the formula shown in Equation 1 to determine the maximum RMS capacitor current requirement. In continuous mode, the source current of the top MOSFET is a square wave of duty cycle ( )/( ). To prevent large voltage transients, a low ESR capacitor sized for the P SYNC = ( I MAX ) 2 ( 1+ δ)r DS(ON) 17

18 APPLICATIONS INFORMATION maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: C IN Required I RMS I MAX 18 ( ) ( ) 1/2 (1) This formula has a maximum at = 2, where I RMS = I OUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the, ceramic capacitors can also be used for C IN. Always consult the manufacturer if there is any question. A small (0.1μF to 1μF) bypass capacitor between the chip pin and ground, placed close to the, is also suggested. A small ( 10Ω) resistor placed between C IN (C1) and the pin provides further isolation. The selection of C OUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (Δ ) is approximated by: 1 Δ ΔI L ESR + 8 f C OUT where f is the operating frequency, C OUT is the output capacitance and ΔI L is the ripple current in the inductor. The output ripple is highest at maximum input voltage since ΔI L increases with input voltage. Setting Output Voltage The output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in Figure 3. The regulated output voltage is determined by: = 0.8V 1+ R B R A To improve the frequency response, a feedforward capacitor, C FF, may be used. Great care should be taken to route the V FB line away from noise sources, such as the inductor or the SW line. V FB RUN Pin The is enabled using the RUN pin. It has a rising threshold of 1.21V with 50mV of hysteresis. Pulling the RUN pin below 1.16V shuts down the main control loop. Pulling it below 0.7V disables the controller and most internal circuits, including the INTV CC LDOs. In this state, the draws only 14μA of quiescent current. Releasing the RUN pin allows a small 7μA internal current to pull up the pin to enable the controller. The RUN pin may be externally pulled up or driven directly by logic. When driving the RUN pin with a low impedance source, do not exceed the absolute maximum rating of 8V. The RUN pin has an internal 11V voltage clamp that allows the RUN pin to be connected through a resistor to a higher voltage (for example, ), so long as the maximum current into the RUN pin does not exceed 100μA. The RUN pin can be implemented as a UVLO by connecting it to the output of an external resistor divider network off, as shown in Figure 4. R B R A 3891 F03 C FF Figure 3. Setting Output Voltage RUN R B R A 3891 F04 Figure 4. Using the RUN Pin as a UVLO

19 APPLICATIONS INFORMATION The rising and falling UVLO thresholds are calculated using the RUN pin thresholds: V UVLO(RISING) = 1.21V 1+ R B R A V UVLO(FALLING) = 1.16V 1+ R B The resistor values should be carefully chosen such that the absolute maximum ratings of the RUN pin do not get violated over the entire voltage range. R A pin of the slave supply ( ), as shown in Figure 7. During start-up will track V X according to the ratio set by the resistor divider: V X R = A R TRACKA + R TRACKB R TRACKA R A + R B For coincident tracking ( = V X during start-up): R A = R TRACKA R B = R TRACKB Tracking and Soft-Start (TRACK/SS Pin) The start-up of is controlled by the voltage on the TRACK/SS pin. When the voltage on the TRACK/SS pin is less than the internal 0.8V reference, the regulates the V FB pin voltage to the voltage on the TRACK/SS pin instead of 0.8V. The TRACK/SS pin can be used to program an external soft-start function or to allow to track another supply during start-up. Soft-start is enabled by simply connecting a capacitor from the TRACK/SS pin to ground, as shown in Figure 5. An internal 10μA current source charges the capacitor, providing a linear ramping voltage at the TRACK/SS pin. The will regulate the V FB pin (and hence ) according to the voltage on the TRACK/SS pin, allowing to rise smoothly from 0V to its final regulated value. The total soft-start time will be approximately: OUTPUT VOLTAGE OUTPUT VOLTAGE V X(MASTER) (SLAVE) 3891 F06a TIME (6a) Coincident Tracking V X(MASTER) (SLAVE) t SS = C SS 0.8V 10µA C SS TRACK/SS 3891 F05 TIME 3891 F06b (6b) Ratiometric Tracking Figure 6. Two Different Modes of Output Voltage Tracking V x R B V FB Figure 5. Using the TRACK/SS Pin to Program Soft-Start Alternatively, the TRACK/SS pin can be used to track another supply during start-up, as shown qualitatively in Figures 6a and 6b. To do this, a resistor divider should be connected from the master supply (V X ) to the TRACK/SS R TRACKB R TRACKA R A TRACK/SS 3891 F07 Figure 7. Using the TRACK/SS Pin for Tracking 19

20 APPLICATIONS INFORMATION INTV CC Regulators The features two separate internal P-channel low dropout linear regulators (LDO) that supply power at the INTV CC pin from either the supply pin or the EXTV CC pin depending on the connection of the EXTV CC pin. INTV CC powers the gate drivers and much of the s internal circuitry. The LDO and the EXTV CC LDO regulate INTV CC to 5.1V. Each of these can supply a peak current of at least 50mA and must be bypassed to ground with a minimum of 2.2μF ceramic capacitor. No matter what type of bulk capacitor is used, an additional 1μF ceramic capacitor placed directly adjacent to the INTV CC and PGND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the to be exceeded. The INTV CC current, which is dominated by the gate charge current, may be supplied by either the LDO or the EXTV CC LDO. When the voltage on the EXTV CC pin is less than 4.7V, the LDO is enabled. Power dissipation for the IC in this case is highest and is equal to I INTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, the INTV CC current is limited to less than 32mA from a 40V supply when not using the EXTV CC supply at a 70 C ambient temperature: T J = 70 C + (32mA)(40V)(43 C/W for QFN) = 125 C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in forced continuous mode (PLLIN/MODE = INTV CC ) at maximum. When the voltage applied to EXTV CC rises above 4.7V, the LDO is turned off and the EXTV CC LDO is enabled. The EXTV CC LDO remains on as long as the voltage applied to EXTV CC remains above 4.5V. The EXTV CC LDO attempts to regulate the INTV CC voltage to 5.1V, so while EXTV CC is less than 5.1V, the LDO is in dropout and the INTV CC voltage is approximately equal to EXTV CC. When EXTV CC is greater than 5.1V, up to an absolute maximum of 14V, INTV CC is regulated to 5.1V. Using the EXTV CC LDO allows the MOSFET driver and control power to be derived from one of the s switching regulator outputs (4.7V 14V) during normal operation and from the LDO when the output is out of regulation (e.g., start-up, short-circuit). If more current is required through the EXTV CC LDO than is specified, an external Schottky diode can be added between the EXTV CC and INTV CC pins. In this case, do not apply more than 6V to the EXTV CC pin and make sure that EXTV CC. Significant efficiency and thermal gains can be realized by powering INTV CC from the output, since the current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). For 5V to 14V regulator outputs, this means connecting the EXTV CC pin directly to. Tying the EXTV CC pin to an 8.5V supply reduces the junction temperature in the previous example from 125 C to: T J = 70 C + (32mA)(8.5V)(43 C/W) = 82 C However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTV CC power from the output. The following list summarizes the four possible connections for EXTV CC : 1. EXTV CC Grounded. This will cause INTV CC to be powered from the internal 5.1V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTV CC Connected Directly to. This is the normal connection for a 5V to 14V regulator and provides the highest efficiency. 3. EXTV CC Connected to an External Supply. If an external supply is available in the 5V to 14V range, it may be used to power EXTV CC providing it is compatible with the MOSFET gate drive requirements. Ensure that EXTV CC <. 20

21 APPLICATIONS INFORMATION 4. EXTV CC Connected to an Output-Derived Boost Network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTV CC to an output-derived voltage that has been boosted to greater than 4.7V. This can be done with the capacitive charge pump shown in Figure 8. Ensure that EXTV CC <. EXTV CC C IN TG SW BG MTOP MBOT BAT85 L NDS7002 R SENSE BAT85 BAT85 C OUT Fault Conditions: Current Limit and Current Foldback The includes current foldback to help limit load current when the output is shorted to ground. If the output voltage falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 100% to 45% of its maximum selected value. Under shortcircuit conditions with very low duty cycles, the will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time, t ON(MIN), of the ( 95ns), the input voltage and inductor value: V ΔI L(SC) = t IN ON(MIN) L PGND 3891 F08 The resulting average short-circuit current is: Figure 8. Capacitive Charge Pump for EXTV CC I SC = 45% I LIM(MAX) 1 2 DI L(SC) Topside MOSFET Driver Supply (C B, D B ) An external bootstrap capacitor, C B, connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. Capacitor C B in the Functional Diagram is charged though external diode D B from INTV CC when the SW pin is low. When the topside MOSFET is to be turned on, the driver places the C B voltage across the gate-source of the MOSFET. This enhances the top MOSFET switch and turns it on. The switch node voltage, SW, rises to and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: V BOOST = + TVCC. The value of the boost capacitor, C B, needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than (MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. Fault Conditions: Overvoltage Protection (Crowbar) The overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. The crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top MOSFET if the short occurs while the controller is operating. A comparator monitors the output for overvoltage conditions. The comparator detects faults greater than 10% above the nominal output voltage. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The bottom MOSFET remains on continuously for as long as the overvoltage condition persists; if returns to a safe level, normal operation automatically resumes. A shorted top MOSFET will result in a high current condition which will open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty cycle to accommodate the leakage. 21

22 APPLICATIONS INFORMATION Phase-Locked Loop and Frequency Synchronization The has an internal phase-locked loop (PLL) comprised of a phase frequency detector, a lowpass filter, and a voltage-controlled oscillator (VCO). This allows the turn-on of the top MOSFET to be locked to the rising edge of an external clock signal applied to the PLLIN/MODE pin. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. If the external clock frequency is greater than the internal oscillator s frequency, f OSC, then current is sourced continuously from the phase detector output, pulling up the VCO input. When the external clock frequency is less than f OSC, current is sunk continuously, pulling down the VCO input. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage at the VCO input is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the internal filter capacitor, CLP, holds the voltage at the VCO input. Note that the can only be synchronized to an external clock whose frequency is within range of the s internal VCO, which is nominally 55kHz to 900kHz. This is guaranteed to be between 75kHz and 750kHz. Typically, the external clock (on the PLLIN/MODE pin) input high threshold is 1.6V, while the input low threshold is 1.1V. Rapid phase locking can be achieved by using the FREQ pin to set a free-running frequency near the desired synchronization frequency. The VCO s input voltage is prebiased at a frequency corresponding to the frequency set by the FREQ pin. Once prebiased, the PLL only needs to adjust the frequency slightly to achieve phase lock and synchronization. Although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the PLL locks. FREQUENCY (khz) FREQ PIN RESISTOR (kω) 3891 F09 Figure 9. Relationship Between Oscillator Frequency and Resistor Value at the FREQ Pin Table 2 summarizes the different states in which the FREQ pin can be used. Table 2 FREQ PIN PLLIN/MODE PIN FREQUENCY 0V DC Voltage 350kHz INTV CC DC Voltage 535kHz Resistor DC Voltage 50kHz to 900kHz Any of the Above External Clock Phase Locked to External Clock Minimum On-Time Considerations Minimum on-time, t ON(MIN), is the smallest time duration that the is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate 22

23 APPLICATIONS INFORMATION charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t ON(MIN) < f ( ) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the is approximately 95ns. However, as the peak sense voltage decreases the minimum on-time gradually increases up to about 130ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% (L1 + L2 + L3 +...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in circuits: 1) IC current, 2) INTV CC regulator current, 3) I 2 R losses, 4) topside MOSFET transition losses. 1. The current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. current typically results in a small (<0.1%) loss. 2. INTV CC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge, dq, moves from INTV CC to ground. The resulting dq/dt is a current out of INTV CC that is typically much larger than the control circuit current. In continuous mode, I GATECHG = f(q T + Q B ), where Q T and Q B are the gate charges of the topside and bottom side MOSFETs. Supplying INTV CC from an output-derived source power through EXTV CC will scale the current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTV CC current results in approximately 2.5mA of current. This reduces the midcurrent loss from 10% or more (if the driver was powered directly from ) to only a few percent. 3. I 2 R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor and input and output capacitor ESR. In continuous mode the average output current flows through L and R SENSE, but is chopped between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same R DS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, R SENSE and ESR to obtain I 2 R losses. For example, if each R DS(ON) = 30mΩ, R L = 50mΩ, R SENSE = 10mΩ and R ESR = 40mΩ (sum of both input and output capacitance losses), then the total resistance is 130mΩ. This results in losses ranging from 3% to 13% as the output current increases from 1A to 5A for a 5V output, or a 4% to 20% loss for a 3.3V output. Efficiency varies as the inverse square of for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. Transition losses apply only to the topside MOSFET(s), and become significant only when operating at high input voltages (typically 15V or greater). Transition losses can be estimated from: Transition Loss = (1.7) 2 I O(MAX) C RSS f 23

24 APPLICATIONS INFORMATION Other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these system level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that C IN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20μF to 40μF of capacitance having a maximum of 20mΩ to 50mΩ of ESR. Other losses including body diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, shifts by an amount equal to ΔI LOAD (ESR), where ESR is the effective series resistance of C OUT. ΔI LOAD also begins to charge or discharge C OUT generating the feedback error signal that forces the regulator to adapt to the current change and return to its steady-state value. During this recovery time can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior, but it also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in Figure 10 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly to optimize transient response once the final PC layout is done and the particular output capacitor type and value 24 have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with C OUT, causing a rapid drop in. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of C LOAD to C OUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 C LOAD. Thus a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. Design Example As a design example, assume = 12V (nominal), = 22V (max), = 3.3V, I MAX = 5A, V SENSE(MAX) = 75mV and f = 350kHz. The inductance value is chosen first based on a 30% ripple current

25 APPLICATIONS INFORMATION assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the FREQ pin to GND, generating 350kHz operation. The minimum inductance for 30% ripple current is: ΔI L = V OUT ( f) ( L) 1 V OUT V IN(NOM) A 4.7μH inductor will produce 29% ripple current. The peak inductor current will be the maximum DC value plus one half the ripple current, or 5.73A. Increasing the ripple current will also help ensure that the minimum on-time of 95ns is not violated. The minimum on-time occurs at maximum : t ON(MIN) = (MAX) f ( ) = 3.3V 22V ( 350kHz ) = 429ns The equivalent R SENSE resistor value can be calculated by using the minimum value for the maximum current sense threshold (64mV): R SENSE 64mV 5.73A 0.01Ω Choosing 1% resistors: R A = 25k and R B = 78.7k yields an output voltage of 3.32V. The power dissipation on the topside MOSFET can be easily estimated. Choosing a Fairchild FDS6982S dual MOSFET results in: R DS(ON) = 0.035Ω/0.022Ω, C MILLER = 215pF. At maximum input voltage with T(estimated) = 50 C: P MAIN = 3.3V 22V 5A ( ) 2 1+ ( 0.005) ( 50 C 25 C) ( 0.035Ω) + 22V ( ) 2 5A ( 2 2.5Ω ) ( 215pF ) 1 5V 2.3V kHz 2.3V ( ) = 331mW A short-circuit to ground will result in a folded back current of: ( ) 4.7µH I SC = 34mV 0.01Ω 1 95ns 22V 2 = 3.18A with a typical value of R DS(ON) and δ = (0.005/ C)(25 C) = The resulting power dissipated in the bottom MOSFET is: P SYNC = ( 3.28A) 2 ( 1.125) ( 0.022Ω) = 250mW which is less than under full-load conditions. C IN is chosen for an RMS current rating of at least 3A at temperature assuming only this channel is on. C OUT is chosen with an ESR of 0.02Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: V ORIPPLE = R ESR (DI L ) = 0.02Ω(1.45A) = 29mV P-P PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. Check the following in your layout: 1. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of C INTVCC must return to the combined C OUT ( ) terminals. The path formed by the top N-channel MOSFET, Schottky diode and the C IN capacitor should have short leads and PC trace lengths. The output capacitor ( ) terminals should be connected as close as possible to the ( ) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 2. Does the V FB pin s resistive divider connect to the (+) terminal of C OUT? The resistive divider must be connected between the (+) terminal of C OUT and signal ground. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 25

26 APPLICATIONS INFORMATION 3. Are the SENSE and SENSE + leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the SENSE resistor. 4. Is the INTV CC decoupling capacitor connected close to the IC, between the INTV CC and the power ground pins? This capacitor carries the MOSFET drivers current peaks. An additional 1μF ceramic capacitor placed immediately next to the INTV CC and PGND pins can help improve noise performance substantially. 5. Keep the SW, TG, and BOOST nodes away from sensitive small-signal nodes. All of these nodes have very large and fast moving signals and therefore should be kept on the output side of the and occupy minimum PC trace area. 6. Use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTV CC decoupling capacitor, the bottom of the voltage feedback resistive divider and the pin of the IC. PC Board Layout Debugging It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold typically 25% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Reduce from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between C IN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the pin of the IC. An embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. The output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor don t worry, the regulator will still maintain control of the output voltage. 26

27 APPLICATIONS INFORMATION TRACK/SS FREQ PLLIN/MODE I LIM PGND EXTV CC INTV CC C INTVCC + C IN 1µF CERAMIC GND C OUT + RUN BG R1* C1* SENSE SENSE + V FB ITH BOOST SW TG PGOOD M1 M2 L1 R OUT V PULL-UP PGOOD D1* R SENSE *R1, C1 AND D1 ARE OPTIONAL 3891 F10 Figure 10. Recommended Printed Circuit Layout Diagram L1 SW R SENSE VOUT R IN C IN D1 C OUT R L F11 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. Figure 11. Branch Current Waveforms 27

28 APPLICATIONS INFORMATION 4V TO 60V C IN 22µF INTV CC 100k PGOOD RUN INTV CC PGND 2.2µF 2200pF 41.2k 100pF 10k I LIM EXTV CC PLLIN/MODE FREQ ITH TG BOOST SW BG D1 0.1µF MTOP L1 4.7µH MBOT R SENSE 8mΩ C OUT 150µF 3.3V 5A 0.1µF TRACK/SS SENSE + SENSE V FB 1nF 100k 31.6k MTOP, MBOT: Si7850DP L1 COILCRAFT SER KL C OUT : SANYO 6TPE470M D1: DFLS F12 Figure 12. High Efficiency 3.3V Step-Down Converter 12.5V TO 60V C IN 22µF INTV CC 100k PGOOD RUN INTV CC PGND 2.2µF 470pF 34.8k 100pF I LIM EXTV CC PLLIN/MODE FREQ ITH TG BOOST SW BG D1 0.1µF MTOP L1 8µH MBOT R SENSE 9mΩ C OUT 180µF 12V 3A 0.1µF TRACK/SS SENSE + SENSE V FB 1nF 100k 6.98k MTOP, MBOT: BSC100N06LS3 L1 COILCRAFT SER KL C OUT : SANYO 16SVP180MX D1: DFLS F13 28 Figure 13. High Efficiency 12V Step-Down Converter

29 PACKAGE DESCRIPTION Please refer to for the most recent package drawings. UDC Package 20-Lead Plastic QFN (3mm 4mm) (Reference LTC DWG # Rev Ø) 0.70 ± ± ± REF 1.65 ± ±0.05 PACKAGE OUTLINE 0.25 ± BSC 2.50 REF 3.10 ± ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.75 ± ±0.10 R = 0.05 TYP 1.50 REF PIN 1 NOTCH R = 0.20 OR CHAMFER 0.40 ± ±0.10 PIN 1 TOP MARK (NOTE 6) 2.50 REF 2.65 ± ±0.10 (UDC20) QFN 1106 REV Ø REF R = ±0.05 TYP 0.50 BSC BOTTOM VIEW EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 29

30 PACKAGE DESCRIPTION Please refer to for the most recent package drawings. FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # Rev I) Exposed Pad Variation CB 3.86 (.152) * ( ) 3.86 (.152) ± ±0.10 SEE NOTE (.108) 0.45 ± (.108) 6.40 (.252) BSC 1.05 ±0.10 RECOMMENDED SOLDER PAD LAYOUT * ( ) 0.65 BSC 0.25 REF (.047) MAX ( ) ( ) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 0.65 (.0256) BSC ( ) TYP 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE ( ) FE20 (CB) TSSOP REV I

31 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 10/12 Added INTV CC to Absolute Maximum Ratings 2 Updated FE package 30 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31

32 TYPICAL APPLICATION 9V TO 60V C IN 22µF INTV CC 100k PGOOD RUN INTV CC PGND 2.2µF 470pF 34.8k I LIM EXTV CC PLLIN/MODE FREQ ITH TG BOOST SW BG D1 0.1µF MTOP L1 8µH MBOT R SENSE 10mΩ C OUT 330µF 8.5V 3A 0.1µF TRACK/SS SENSE + SENSE V FB 1nF 100k 10.5k MTOP, MBOT: Si7850DP L1 COILCRAFT SER KL C OUT : SANYO 10TPE330M D1: DFLS F14 Figure 14. High Efficiency 8.5V Step-Down Converter RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3890/LTC V, Low I Q, Dual Output 2-Phase Synchronous Step- Down DC/DC Controller Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V 60V, 0.8V 24V, I Q = 50µA LTC3857/LTC Low I Q, Dual Output 2-Phase Synchronous Step-Down DC/DC Controllers with 99% Duty Cycle Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V 38V, 0.8V 24V, I Q = 50µA LTC3858/LTC Low I Q, Dual Output 2-Phase Synchronous Step-Down DC/DC Controllers with 99% Duty Cycle Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V 38V, 0.8V 24V, I Q = 170µA LTC3868/LTC Low I Q, Dual Output 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V 24V, 0.8V 14V, I Q = 170µA LTC3834/LTC Low I Q, Single Output Synchronous Step-Down DC/DC Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V 36V, Controller with 99% Duty Cycle 0.8V 10V, I Q = 30µA LTC3835/LTC Low I Q, Single Output Synchronous Step-Down DC/DC Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V 36V, Controller with 99% Duty Cycle 0.8V 10V, I Q = 80µA LT3845A 60V, Low I Q, Single Output Synchronous Step-Down DC/DC Controller Adjustable Fixed Frequency 100kHz to 500kHz, 4V 60V, 1.23V 36V, I Q = 120µA LTC3859 Low I Q, Triple Output Buck/Buck/Boost Synchronous DC/DC Controller Outputs 4V Remain in Regulation Through Cold Crank, 2.5V 38V, (BUCKS) Up to 24V, (BOOST) Up to 60V, I Q = 55µA LTC3824 Low I Q, Single Output Step-Down Controller, 100% Duty Cycle Fixed 200kHz to 600kHz, 4V 60V, 0.8V, I Q = 40µA, MSOP-10E 32 LT 1012 REV A PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA (408) FAX: (408) LINEAR TECHNOLOGY CORPORATION 2010