Personal Systems Reference Intel PC Processors
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- Joella Lane
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1 Personal s Reference PC Processors May Version 357 Visit for the latest version
2 [tebook] Celeron M Processor 5xx Celeron M processor for mobile systems Battery Hyper- Threading nology Execute Disable Bit Enhanced nology 64 Ultra Low Voltage Celeron M Processor N/A 1MB 533 Single Yes Yes Sep 2007 Standard Voltage Celeron M Processor GHz N/A 1MB 533 Single Yes Yes Jan 2007 Celeron M Processor GHz N/A 1MB 533 Single Yes Yes Apr 2007 MMX / Streaming SIMD SSE2 SSE3 64 nology 1 nology L1 data L1 instruction - size - data path L3 Execution units Merom Celeron M Processor Single-core t part of the Centrino Processor nology or Centrino with vpro Processor nology MMX (57 new instructions), Streaming SIMD Extensions (70 new instructions) Streaming SIMD Extensions 2 (144 new instructions) Streaming SIMD Extensions 3 (13 new instructions) ne One thread (one cores with no support provides one logical processor) ne ne 256-bit data path, full speed 32KB data, integrated 32KB instruction, integrated 1MB, full speed 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated, unifi ed (on die) ne 533 (transfers data 4 times per clock), address transfers at 2 times per clock 65nm or 0.065u Ultra Low Voltage: 5 watts; Standard Voltage: 30 watts All: Socket M 520/530: Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket (mpga479m socket) 523: Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball) Mobile 945 Express Chipset family; other compatible chipsets (M5C) September 2007
3 [tebook] Celeron Processor 5xx, 7xx Celeron mobile processor Battery Thermal Design Power Hyper- Threading nology Enhanced nology 64 Celeron Processor GHz N/A 1MB 533 Single 31W Yes Sep 2007 Celeron Processor GHz N/A 1MB 533 Single 31W Yes Jun 2007 Celeron Processor GHz N/A 1MB 533 Single 31W Yes Jun 2007 Celeron Processor GHz N/A 1MB 533 Single 31W Yes Jan 2008 Celeron Processor GHz N/A 1MB 533 Single 31W Yes Apr 2008 Celeron Processor GHz N/A 1MB 667 Single 31W Yes Aug 2008 Celeron Processor GHz N/A 1MB 667 Single 31W Yes Aug 2008 Celeron Processor GHz N/A 1MB 800 Single 10W Yes Aug 2008 MMX / Streaming SIMD SSE2 SSE3 64 nology 1 nology L1 data L1 instruction - size - data path L3 Execution units 5xx: Merom; 7xx: Penryn Celeron mobile processor Single-core t part of the Centrino Processor nology or Centrino with vpro Processor nology MMX (57 new instructions), Streaming SIMD Extensions (70 new instructions) Streaming SIMD Extensions 2 (144 new instructions) Streaming SIMD Extensions 3 (13 new instructions) ne One thread (one cores with no support provides one logical processor) ne ne 256-bit data path, full speed 32KB data, integrated 32KB instruction, integrated 1MB, full speed 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated, unifi ed (on die) ne 533, 667, or 800 (transfers data 4 times per clock), address transfers at 2 times per clock 65nm or 0.065u 5xx: volts 7xx: 10 watts (Ultra Low Voltage) 5xx: Socket P / Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket (mpga479m socket) 7xx: Socket P / Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball) 5xx: Mobile 965 Express Chipset family; other compatible chipsets 7xx: Mobile 4 Series Express Chipset family; other compatible chipsets (CEL5) September 2008
4 [tebook] Celeron Processor Celeron mobile processor HD Boost Execute Disable Bit Enhanced nology 64 Trusted Execution Celeron processor T GHz 1MB 667 Dual Yes Yes Yes Oct 2008 Celeron processor T GHz 1MB 667 Dual Yes Yes Yes Oct 2008 Montevina Celeron mobile processor Dual-core Value or essential mobile processor Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost 64 nology 1 nology Trusted Execution nology Enhanced technology (EIST) 64 nology (an extension to the IA-32 instruction set which adds 64 bit extensions to the x86 architecture) L1 data L1 instruction - size - data path Execution units 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data / integrated 2x32KB instruction / integrated 1MB / full speed / shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes) / 64 byte line size / 8-way set associative / integrated / unifi ed (on die) 667 (transfers data 4 times per clock) / address transfers at 2 times per clock 64GB memory addressability (but limited by chipset) / 36-bit addressing 65nm or 0.065u 35 watts Socket P / Micro Flip-Chip Ball Grid Array (Micro-FCBGA) Mobile 4 Series Chipset family; other compatible chipsets (DCELM) January 2009
5 [tebook] Pentium Processor Pentium Processor Hyper- Threading nology Execute Disable Bit Enhanced nology 64 Trusted Execution Dynamic Acceleration Pentium Processor T GHz 1MB 533 Dual Yes Yes Jan 2007 Pentium Processor T GHz 1MB 533 Dual Yes Yes Jan 2007 Pentium Processor T GHz 1MB 533 Dual Yes Yes Oct 2007 Pentium Processor T GHz 1MB 533 Dual Yes Yes Yes July 2007 Pentium Processor T GHz 1MB 533 Dual Yes Yes Yes July 2007 Pentium Processor T GHz 1MB 533 Dual Yes Yes Yes Jan 2008 Pentium Processor T GHz 1MB 533 Dual Yes Yes Yes Jan 2008 Pentium Processor T GHz 1MB 667 Dual Yes Yes Yes v 2008 Pentium Processor T GHz 1MB 667 Dual Yes Yes Yes v 2008 Pentium Processor T GHz 1MB 800 Dual Yes Yes Yes T2060/T2080/T2130: Yonah; T2310/T2330/T2370/T2390/T3200/T3400: Merom; T2310: Penryn Pentium Processor Dual-core Value or essential mobile processor Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost 64 nology 1 nology Trusted Execution nology Dynamic Accerlation ; Enhanced technology Two threads (two cores with no support provide two logical processors) Some: 64 nology (an extension to the IA-32 instruction set which adds 64 bit extensions to the x86 architecture) L1 data L1 instruction - size - data path L3 Execution units 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data / integrated 2x32KB instruction / integrated 1MB / full speed, shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated, unifi ed (on die) ne 533, 667 or 800 (transfers data 4 times per clock), address transfers at 2 times per clock 64GB memory addressability (but limited by chipset) / 36-bit addressing T2xxx/T3xxx: 65nm; T4xxx: 45nm T2060/T2080/T2130: Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket (mpga479m socket) or Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball) T2310/T2330/T2370/T2390/T3200/T3400/T4200: Socket P / Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket (mpga479m socket) or Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball) (P2) May 2009
6 [tebook] 2 Solo Processor 2 Solo processor for mobile systems Hyper- Threading nology 64 Ultra Low Voltage 2 Solo processor U GHz 1MB 533 Single Yes Yes Sep Solo processor U GHz 1MB 533 Single Yes Yes Sep Solo processor SU GHz 3MB 800 Single Yes Yes Yes Yes Aug Solo processor SU GHz 3MB 800 Single Yes Yes Yes Yes Aug 2008 HD Boost Trusted Dynamic Execution Acceleration (TXT) Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost HD Boost Power management technology Dynamic Power Coordination Dynamic Bus Parking Enhanced Deeper Sleep with Dynamic Cache Sizing 64 nology 1 nology Dynamic Acceleration Trusted Execution (TXT) Uxxxx: Merom (Napa Refresh); SUxxxx: Penryn (Montevina) 2 Solo mobile processor Single-core Some: Streaming SIMD Extensions 4 (SSE4) and faster Super Shuffl e Engine Enhanced SpeedStep technology Coordinates Enhanced SpeedStep nology and idle power-management state transitions independently per core to help save power Enables platform power savings and improved battery life by allowing the chipset to power down with the processor in low-frequency mode Saves power by fl ushing data to system memory during periods of inactivity to lower CPU voltage 64 nology (an extension to the IA-32 instruction set which adds 64-bit extensions to the x86 architecture) nology ne Some: Provides a more secure platform from software-based attacks with TXT-enabled OS or appl L1 data L1 instruction - size - data path L3 Execution units per core 64KB per core split between data (32KB) and instuction (32KB) 32KB data / integrated 32KB instruction / integrated 1MB or 3MB / full speed 256-bit data path (32 bytes) / 64 byte line size / 8-way set associative / integrated / unifi ed (on die) ne 533 or 800 (transfers data 4 times per clock) / address transfers at 2 times per clock 64GB memory addressability (but limited by chipset) / 36-bit addressing Uxxxx: 65nm; SUxxxx: 45nm 5.5 watts Uxxxx: Socket M / Micro Flip-Chip Ball Grid Array (Micro-FCBGA) SUxxxx: Socket P / Micro Flip-Chip Ball Grid Array (Micro-FCBGA) Uxxxx: Mobile 945GM and 945GMS Express Chipset; other compatible chipsets SUxxxx: Mobile 4 Series Express Chipset; other compatible chipsets (C2S) September 2008
7 [tebook] 2 Duo Processor (Socket M) 2 Duo processor for mobile systems Battery 2 Duo processor U GHz 800 2MB 533 Dual Yes Yes Yes Yes Apr Duo processor U GHz 800 2MB 533 Dual Yes Yes Yes Yes Apr Duo processor U GHz 800 2MB 533 Dual Yes Yes Yes Yes Jun Duo processor L GHz 1.0GHz 4MB 667 Dual Yes Yes Yes Yes Jan Duo processor L GHz 1.0GHz 4MB 667 Dual Yes Yes Yes Yes Jan Duo processor T GHz 1.0GHz 2MB 533 Dual Yes Yes Yes Jan Duo processor T GHz 1.0GHz 2MB 533 Dual Yes Yes Yes Oct Duo processor T GHz 1.0GHz 2MB 667 Dual Yes Yes Yes July Duo processor T GHz 1.0GHz 2MB 667 Dual Yes Yes Yes Yes July Duo processor T GHz 1.0GHz 4MB 667 Dual Yes Yes Yes Yes July Duo processor T GHz 1.0GHz 4MB 667 Dual Yes Yes Yes Yes July Duo processor T GHz 1.0GHz 4MB 667 Dual Yes Yes Yes Yes July 2006 U (Ultra Low Voltage)=<14 watts; L (Low Voltage)=15-24 watts; T (Standard Voltage)=25-49 watts; E=>50 watts Dynamic Acceleration Hyper- Threading nology Execute Disable Bit Enhanced nology 64 Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost Power management technology Dynamic Power Coordination Dynamic Bus Parking Enhanced Deeper Sleep with Dynamic Cache Sizing 64 nology 1 nology Dynamic Accerlation Merom 2 Duo mobile processor Dual-core Enhanced SpeedStep technology Coordinates Enhanced SpeedStep nology and idle power-management state transitions independently per core to help save power Enables platform power savings and improved battery life by allowing the chipset to power down with the processor in low-frequency mode Saves power by fl ushing data to system memory during periods of inactivity to lower CPU voltage Two threads (two cores with no support provide two logical processors) 64 nology (an extension to the IA-32 instruction set which adds 64-bit extensions to the x86 architecture) Some: nology Some: Dynamic Acceleration (IDA) allows one core to deliver extra performance when other core is idle L1 data L1 instruction - size - data path L3 Execution units per core 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data / integrated 2x32KB instruction / integrated 2MB or 4MB / full speed / shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes) / 64 byte line size / 8-way set associative / integrated / unifi ed (on die) ne 533, 667, or 800 (transfers data 4 times per clock) / address transfers at 2 times per clock 64GB memory addressability (but limited by chipset) / 36-bit addressing 65nm or 0.065u U7xxx: 10 watts; L7xxx: 17 watts; Txxxx: 34 watts Socket M / Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket (mpga479m socket) or Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball) Mobile 945 Express Chipset family; other compatible chipsets (C2DT) September 2008
8 [tebook] 2 Duo Processor (Socket P) 2 Duo processor for mobile systems 2 Duo processor U GHz 800 2MB 533 Dual Yes Yes Yes Yes Yes Jun Duo processor U GHz 800 2MB 533 Dual Yes Yes Yes Yes Yes Jun Duo processor U GHz 800 2MB 533 Dual Yes Yes Yes Yes Yes Jan Duo processor SL GHz 800 4MB 800 Dual Yes Yes Yes Yes Yes Feb Duo processor L GHz 800 4MB 800 Dual Yes Yes Yes Yes Yes May Duo processor L GHz 800 4MB 800 Dual Yes Yes Yes Yes Yes May Duo processor L GHz 800 4MB 800 Dual Yes Yes Yes Yes Yes Sep Duo processor T GHz 667 2MB 667 Dual Yes Yes Yes July Duo processor T GHz 1.0GHz 2MB 800 Dual Yes Yes Yes Yes Aug Duo processor T GHz 667 2MB 667 Dual Yes Yes Yes July Duo processor T GHz 1.0GHz 2MB 800 Dual Yes Yes Yes Yes Aug Duo processor T GHz 667 2MB 667 Dual Yes Yes Yes July Duo processor T GHz 800 2MB 800 Dual Yes Yes Yes Yes July Duo processor T GHz 667 2MB 667 Dual Yes Yes Yes Feb Duo processor T GHz 667 2MB 667 Dual Yes Yes Yes Feb Duo processor T GHz 800 2MB 800 Dual Yes Yes Yes Yes Oct Duo processor T GHz 800 2MB 800 Dual Yes Yes Yes Yes Yes May Duo processor T GHz 800 2MB 800 Dual Yes Yes Yes Yes Yes Sep Duo processor T GHz 800 4MB 800 Dual Yes Yes Yes Yes Yes May Duo processor T GHz 800 4MB 800 Dual Yes Yes Yes Yes Yes May Duo processor T GHz 800 4MB 800 Dual Yes Yes Yes Yes Yes May Duo processor T GHz 800 4MB 800 Dual Yes Yes Yes Yes Yes Sep 2007 U (Ultra Low Voltage)=<14 watts; L (Low Voltage)=15-24 watts; T (Standard Voltage)=25-49 watts; E=>50 watts Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost Power management technology Dynamic Power Coordination Dynamic Bus Parking Enhanced Deeper Sleep with Dynamic Cache Sizing Dynamic Front Side Bus Frequency Switching 64 nology 1 nology Dynamic Accerlation L1 data L1 instruction - size - data path (front side ) Execution units per core Battery Execute Disable Bit Enhanced nology 64 Dynamic Acceleration Merom 2 Duo mobile processor Dual-core Enhanced SpeedStep technology Coordinates Enhanced SpeedStep nology and idle power-management state transitions independently per core to help save power Enables platform power savings and improved battery life by allowing the chipset to power down with the processor in low-frequency mode Saves power by fl ushing data to system memory during periods of inactivity to lower CPU voltage Some (not T5xxx): Changes the clock frequency allowing a reduction in core voltage enabling a lower power active state called super LFM 64 nology (an extension to the IA-32 instruction set which adds 64-bit extensions to the x86 architecture) Some: nology (VT) Some: Dynamic Acceleration (IDA) allows one core to deliver extra performance when other core is idle 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data, integrated 2x32KB instruction, integrated 2MB or 4MB, full speed, shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated, unifi ed (on die) 533, 667, or 800 (transfers data 4 times per clock) / address transfers at 2 times per clock 64GB memory addressability (but limited by chipset), 36-bit addressing 65nm or 0.065u U7xxx: 10 watts; L7xxx: 17 watts; Txxxx: 35 watts Socket P / Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket (mpga479m socket) or Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball) Mobile 965 Express Chipset family; other compatible chipsets (C2DP) vember 2008
9 [tebook] 2 Duo Processor (Penryn) 2 Duo processor for notebook systems 2 Duo processor T GHz 2MB 800 Dual 35W Yes Yes Yes Jan Duo processor T GHz 2MB 800 Dual 35W Yes Yes Yes 2 Duo processor T GHz 2MB 800 Dual 35W Yes Yes Yes Jan Duo processor T GHz 3MB 800 Dual 35W Yes Yes Yes Jan Duo processor T GHz 3MB 800 Dual 35W Yes Yes Yes Jan Duo processor T GHz 6MB 800 Dual 35W Yes Yes Yes Jan Duo processor T GHz 6MB 800 Dual 35W Yes Yes Yes Jan Duo processor P GHz 3MB 1066 Dual 25W Yes Yes Yes Yes Sep Duo processor P GHz 3MB 1066 Dual 25W Yes Yes Yes Yes Jan Duo processor P GHz 3MB 1066 Dual 25W Yes Yes Yes Yes July Duo processor P GHz 3MB 1066 Dual 25W Yes Yes Yes Yes July Duo processor P GHz 3MB 1066 Dual 25W Yes Yes Yes Yes Dec Duo processor P GHz 6MB 1066 Dual 25W Yes Yes Yes Yes July Duo processor P GHz 6MB 1066 Dual 25W Yes Yes Yes Yes Dec Duo processor T GHz 6MB 1066 Dual 35W Yes Yes Yes Yes July Duo processor T GHz 6MB 1066 Dual 35W Yes Yes Yes Yes Dec Duo processor T GHz 6MB 1066 Dual 35W Yes Yes Yes Yes July Duo processor T GHz 6MB 1066 Dual 35W Yes Yes Yes Yes Dec 2008 U (Ultra Low Voltage)=<12 watts; L (Low Voltage)=12-19 watts; P =20-29 watts; T (Standard Voltage)=30-39 watts; X or QX=>40 watts Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost HD Boost Power management technology Dynamic Power Coordination Deep Power Down nology 64 nology 1 nology Dynamic Accerelation Trusted Execution (TXT) L1 data L1 instruction - size - data path (front side ) Execution units per core Thermal Design Power T8100/T8300/T9300/T9500: Penryn (Santa Rosa Refresh); Others: Penryn (Montevina) 2 Duo mobile processor Dual-core Supports Centrino 2 Processor nology or Centrino 2 with vpro Processor nology when hardware and software requirements met Streaming SIMD Extensions 4 (SSE4) and faster Super Shuffl e Engine Enhanced SpeedStep technology Coordinates Enhanced nology and idle power-management state transitions independently per core to help save power Low-power state that allows both cores and to be powered down when processor idle Two threads (two cores with no support provide two logical processors) 64 nology (an extension to the IA-32 instruction set which adds 64-bit extensions to the x86 architecture) nology (VT) Dynamic Acceleration (IDA) allows one core to deliver extra performance when other core is idle Provides a more secure platform with protection from software-based attacks with TXT-enabled OS or appl 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data, integrated 2x32KB instruction, integrated 2MB, 3MB, or 6MB, full speed, shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated, unifi ed (on die) 800 or 1066 (transfers data 4 times per clock), address transfers at 2 times per clock 64GB memory addressability (but limited by chipset), 36-bit addressing 64 Trusted Dynamic Execution Acceleration (TXT) 45nm Pxxxx: 25 watts; Txxxx: 35 watts Socket P / Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket (mpga479m socket) or Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball) Mobile 965 Express Chipset family; Mobile 4 Series Chipset family; other compatible chipsets (PENRYN) May 2009
10 [tebook] 2 Duo Processor (SFF) 2 Duo processor Small Form Factor (SFF) for notebook systems Thermal Design Power HD Boost 64 Trusted Dynamic Execution Acceleration (TXT) 2 Duo processor SU GHz 3MB 800 Dual 10W Yes Yes Yes Yes Aug Duo processor SU GHz 3MB 800 Dual 10W Yes Yes Yes Yes Aug Duo processor SU GHz 3MB 800 Dual 10W Yes Yes Yes Yes 2 Duo processor SL GHz 6MB 1066 Dual 17W Yes Yes Yes Yes Aug Duo processor SL GHz 6MB 1066 Dual 17W Yes Yes Yes Yes Aug Duo processor SL GHz 6MB 1066 Dual 17W Yes Yes Yes Yes 2 Duo processor SP GHz 6MB 1066 Dual 25W Yes Yes Yes Yes Aug Duo processor SP GHz 6MB 1066 Dual 25W Yes Yes Yes Yes Aug 2008 Small Form Factor (SFF) notebook processors - SUxxxx = Ultra Low Voltage - SLxxxx = Low Voltage - SPxxxx = Power Optimized ormance Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost HD Boost Power management technology Dynamic Power Coordination Dynamic Bus Parking Enhanced Deeper Sleep with Dynamic Cache Sizing Deep Power Down nology 64 nology 1 nology Dynamic Acceleration Trusted Execution (TXT) Penryn (Montevina) 2 Duo mobile processor Dual-core Supports Centrino 2 Processor nology or Centrino 2 with vpro Processor nology when hardware and software requirements met Streaming SIMD Extensions 4 (SSE4) and faster Super Shuffl e Engine Enhanced SpeedStep technology Coordinates Enhanced nology and idle power-management state transitions independently per core to help save power Enables platform power savings and improved battery life by allowing the chipset to power down with the processor in low-frequency mode Saves power by fl ushing data to system memory during periods of inactivity to lower CPU voltage Low-power state that allows both cores and to be powered down when processor idle Two threads (two cores with no support provide two logical processors) 64 nology (an extension to the IA-32 instruction set which adds 64-bit extensions to the x86 architecture) nology (VT) Dynamic Acceleration (IDA) allows one core to deliver extra performance when other core is idle Provides a more secure platform with protection from software-based attacks with TXT-enabled OS or appl L1 data L1 instruction - size - data path L3 (front side ) Execution units per core 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data, integrated 2x32KB instruction, integrated 3MB or 6MB, full speed, shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated, unifi ed (on die) ne 800 or 1066 (transfers data 4 times per clock), address transfers at 2 times per clock 64GB memory addressability (but limited by chipset), 36-bit addressing 45nm SUxxxx: 10 watts; SLxxxx: 17 watts; SPxxxx: 25 watts Socket P / Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball) Mobile 4 Series Chipset family; other compatible chipsets (PENSFF) May 2009
11 [tebook] 2 Quad Processor 2 Quad processor for notebook systems Thermal Design Power 64 Trusted Dynamic Execution Acceleration (TXT) 2 Quad processor Q GHz 6MB 1066 Quad 45W Yes Yes Yes Dec Quad processor Q GHz 12MB 1066 Quad 45W Yes Yes Yes Aug 2008 Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost HD Boost Power management technology Dynamic Power Coordination Dynamic Bus Parking Enhanced Deeper Sleep with Dynamic Cache Sizing Deep Power Down nology 64 nology 1 nology Dynamic Accerelation Trusted Execution (TXT) L1 data L1 instruction - size - data path L3 Penryn (Montevina) 2 Quad mobile processor Quad-core Supports Centrino 2 Processor nology or Centrino 2 with vpro Processor nology when hardware and software requirements met micro-architecture Streaming SIMD Extensions 4 (SSE4) and faster Super Shuffl e Engine Enhanced SpeedStep technology Coordinates Enhanced nology and idle power-management state transitions independently per core to help save power Enables platform power savings and improved battery life by allowing the chipset to power down with the processor in low-frequency mode Saves power by fl ushing data to system memory during periods of inactivity to lower CPU voltage Low-power state that allows both cores and to be powered down when processor idle Two threads (two cores with no support provide two logical processors) 64 nology (an extension to the IA-32 instruction set which adds 64-bit extensions to the x86 architecture) nology (VT) Dynamic Acceleration (IDA) allows one core to deliver extra performance when other core is idle Provides a more secure platform with protection from software-based attacks with TXT-enabled OS or appl 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data, integrated 2x32KB instruction, integrated 6MB or 12MB, full speed, shared between cores ( Advanced Smart Cache) 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated, unifi ed (on die) ne (front side ) Execution units per core 1066 (transfers data 4 times per clock), address transfers at 2 times per clock 64GB memory addressability (but limited by chipset), 36-bit addressing 45nm 45 watts Socket P / Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket (mpga479m socket) or Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball) Mobile 4 Series Chipset family; other compatible chipsets (C2QUAD) December 2008
12 [tebook] 2 Extreme Processor 2 Extreme processor for notebook systems HD Boost Enhanced nology 64 Dynamic Acceleration Trusted Execution (TXT) 2 Extreme processor X GHz 4MB 800 Dual Yes Yes Yes July Extreme processor X GHz 4MB 800 Dual Yes Yes Yes Aug Extreme processor X GHz 6MB 800 Dual Yes Yes Yes Yes Yes Jan Extreme processor X GHz 6MB 1066 Dual Yes Yes Yes Yes Yes July Extreme processor QX GHz 12MB 1066 Quad Yes Yes Yes Yes Yes Aug 2008 (s) X7800/X7900: Merom (Santa Rosa); X9000/X9100: Penryn (Santa Rosa Refresh); QX9300: Penryn 2 Extreme processor Dual-core or quad-core 's highest performance brand for processors Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost HD Boost 64 nology 1 nology Dynamic Accerlation Trusted Execution (TXT) micro-architecture X9000/X9100/QX9300: Streaming SIMD Extensions 4 (SSE4) and faster Super Shuffl e Engine Enhanced technology Two threads (two cores with no support provide two logical processors) 64 nology (an extension to the IA-32 instruction set which adds 64 bit extensions to the x86 architecture) nology Some: Dynamic Acceleration (IDA) allows one core to deliver extra performance when other core is idle Some: Provides a more secure platform from software-based attacks with TXT-enabled OS or appl L1 data L1 instruction - size - data path L3 Execution units per core 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data, integrated 2x32KB instruction, integrated 4MB, 6MB, or 12MB, full speed, shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated, unifi ed (on die) ne 800 or 1066 (transfers data 4 times per clock), address transfers at 2 times per clock 64GB memory addressability (but limited by chipset), 36-bit addressing X7800/X7900: 65nm; X9000/X9100/QS9300: 45nm 44 or 45 watts Socket P / Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket (mpga479m socket) or Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball) Mobile 965 Express Chipset family; other compatible chipsets (XM) August 2008
13 [Desktop] Celeron Processor 4xx Celeron Processor Hyper- Threading nology Total threads (logical) Execute Disable Bit Enhanced nology 64 Trusted Execution Celeron Processor GHz 512KB 800 Single 1 Yes Yes Jun 2007 Celeron Processor GHz 512KB 800 Single 1 Yes Yes Jun 2007 Celeron Processor GHz 512KB 800 Single 1 Yes Yes Jun 2007 Celeron Processor GHz 512KB 800 Single 1 Yes Yes Aug 2008 Conroe-L Celeron Processor Single-core Value or essential desktop processor Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost 64 nology 1 nology Trusted Execution nology ; Enhanced technology One thread 64 nology (an extension to the IA-32 instruction set which adds 64 bit extensions to the x86 architecture) L1 data L1 instruction - size - data path L3 Execution units 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data / integrated 2x32KB instruction / integrated 512KB / full speed 256-bit data path (32 bytes) / 64 byte line size / 8-way set associative / integrated / unifi ed (on die) ne 800 (transfers data 4 times per clock) / address transfers at 2 times per clock 64GB memory addressability (but limited by chipset) / 36-bit addressing 65nm or 0.065u 65 watts 775-land Flip-Chip Land Grid Array (FC-LGA6) package requires LGA775 socket (socket also called Socket T) 3 Series Express Chipset family; 945 and 965 Express Chipset family; other compatible chipsets (CEL4) September 2008
14 [Desktop] Celeron Processor Celeron Processor HD Boost Execute Disable Bit Enhanced nology 64 Trusted Execution Celeron Processor E GHz 512KB 800 Dual Yes Yes Yes Jan 2008 Celeron Processor E GHz 512KB 800 Dual Yes Yes Yes Apr 2008 Celeron Processor E GHz 512KB 800 Dual Yes Yes Yes Dec 2008 Conroe Celeron Processor Dual-core Value or essential desktop processor Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost 64 nology 1 nology Trusted Execution nology ; Enhanced technology (EIST) 64 nology (an extension to the IA-32 instruction set which adds 64 bit extensions to the x86 architecture) L1 data L1 instruction - size - data path Execution units 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data / integrated 2x32KB instruction / integrated 512KB / full speed / shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes) / 64 byte line size / 8-way set associative / integrated / unifi ed (on die) 800 (transfers data 4 times per clock) / address transfers at 2 times per clock 64GB memory addressability (but limited by chipset) / 36-bit addressing 65nm or 0.065u 65 watts 775-land Flip-Chip Land Grid Array (FC-LGA6) package requires LGA775 socket (socket also called Socket T) G31 Express Chipset families; other compatible chipsets (DCEL) January 2009
15 [Desktop] Pentium Processor Pentium Processor Hyper- Threading nology Total threads (logical) Execute Disable Bit Enhanced nology 64 Trusted Execution Pentium Processor E GHz 1MB 800 Dual 2 Yes Yes Yes Jun 2007 Pentium Processor E GHz 1MB 800 Dual 2 Yes Yes Yes Jun 2007 Pentium Processor E GHz 1MB 800 Dual 2 Yes Yes Yes Aug 2007 Pentium Processor E GHz 1MB 800 Dual 2 Yes Yes Yes Dec 2007 Pentium Processor E GHz 1MB 800 Dual 2 Yes Yes Yes Mar 2008 Pentium Processor E GHz 2MB 800 Dual 2 Yes Yes Yes Aug 2008 Pentium Processor E GHz 2MB 800 Dual 2 Yes Yes Yes Dec 2008 E2xxx: Conroe; E5xxx: Wolfdale Pentium Processor Dual-core Value or essential desktop processor Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost 64 nology 1 nology Trusted Execution nology ; Enhanced technology Two threads (two cores with no support provide two logical processors) 64 nology (an extension to the IA-32 instruction set which adds 64 bit extensions to the x86 architecture) L1 data L1 instruction - size - data path L3 Execution units 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data / integrated 2x32KB instruction / integrated 1MB or 2MB / full speed / shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes) / 64 byte line size / 8-way set associative / integrated / unifi ed (on die) ne 800 (transfers data 4 times per clock) / address transfers at 2 times per clock 64GB memory addressability (but limited by chipset) / 36-bit addressing E2xxx: 65nm; E5xxx: 45nm 65 watts 775-land Flip-Chip Land Grid Array (FC-LGA6) package requires LGA775 socket (socket also called Socket T) G31 Express Chipset; 4 Series Express Chipset family; other compatible chipsets (E2) January 2009
16 [Desktop] 2 Duo Processor 2 Duo processor for desktop systems Hyper- Threading nology Execute Disable Bit Enhanced nology 64 Trusted Execution 2 Duo processor E GHz 2MB 800 Dual Yes Yes Yes Jan Duo processor E GHz 2MB 800 Dual Yes Yes Yes Apr Duo processor E GHz 2MB 800 Dual Yes Yes Yes July Duo processor E GHz 2MB 800 Dual Yes Yes Yes Oct Duo processor E GHz 2MB 800 Dual Yes Yes Yes Mar Duo processor E GHz 2MB 1066 Dual Yes Yes Yes Yes July Duo processor E GHz 4MB 1066 Dual Yes Yes Yes Yes Apr Duo processor E GHz 2MB 1066 Dual Yes Yes Yes Yes July Duo processor E GHz 4MB 1066 Dual Yes Yes Yes Yes Apr Duo processor E GHz 4MB 1333 Dual Yes Yes Yes Yes July Duo processor E GHz 4MB 1333 Dual Yes Yes Yes Yes Yes July Duo processor E GHz 4MB 1066 Dual Yes Yes Yes Yes July Duo processor E GHz 4MB 1066 Dual Yes Yes Yes Yes July Duo processor E GHz 4MB 1333 Dual Yes Yes Yes Yes Yes July Duo processor E GHz 4MB 1333 Dual Yes Yes Yes Yes Yes July 2007 Conroe 2 Duo desktop processor Dual-core Part of the Viiv technology for the home and vpro technology for iness Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost 64 nology 1 nology Trusted Execution nology Dynamic Acceleration Enhanced technology Two threads (two cores with no support provide two logical processors) 64 nology (an extension to the IA-32 instruction set which adds 64 bit extensions to the x86 architecture) Some: nology Some: enables more secure platforms from software-based attacks with appropriate software L1 data L1 instruction - size - data path L3 Execution units 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data, integrated 2x32KB instruction, integrated 2MB or 4MB, full speed, shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated, unifi ed (on die) ne 800, 1066, or 1333 (transfers data 4 times per clock) / address transfers at 2 times per clock 64GB memory addressability (but limited by chipset), 36-bit addressing 65nm 65 watts 775-land Flip-Chip Land Grid Array (FC-LGA6) package requires LGA775 socket (socket also called Socket T) Q963, Q965, G965, P965, 946, 975X Express Chipset families; other compatible chipsets (C2DE) March 2008
17 [Desktop] 2 Duo Processor (Wolfdale) 2 Duo processor for desktop systems Execute Disable Bit Enhanced nology 64 Trusted Execution Dynamic Acceleration 2 Duo processor E GHz 3MB 1066 Dual Yes Yes Yes Apr Duo processor E GHz 3MB 1066 Dual Yes Yes Yes Aug Duo processor E GHz 3MB 1066 Dual Yes Yes Yes Oct Duo processor E GHz 3MB 1066 Dual Yes Yes Yes Jan Duo processor E GHz 6MB 1333 Dual Yes Yes Yes Jan Duo processor E GHz 6MB 1333 Dual Yes Yes Yes Yes Yes Jan Duo processor E GHz 6MB 1333 Dual Yes Yes Yes Yes Yes Apr Duo processor E GHz 6MB 1333 Dual Yes Yes Yes Yes Yes Jan Duo processor E GHz 6MB 1333 Dual Yes Yes Yes Yes Yes Jan Duo processor E GHz 6MB 1333 Dual Yes Yes Yes Yes Yes May 2008 Wolfdale 2 Duo desktop processor Dual-core Supports 2 Processor with Viiv technology and 2 Processor with vpro technology when hardware and software requirements met Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost HD Boost 64 nology 1 nology Trusted Execution nology Dynamic Acceleration Streaming SIMD Extensions 4 (SSE4) and faster Super Shuffl e Engine Enhanced technology Two threads (two cores with no support provide two logical processors) 64 nology (an extension to the IA-32 instruction set which adds 64 bit extensions to the x86 architecture) Some: nology Some: Enables more secure platforms from software-based attacks with appropriate software ne L1 data L1 instruction - size - data path L3 (front side ) Execution units 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data, integrated 2x32KB instruction, integrated 3MB or 6MB, full speed, shared between both cores ( Advanced Smart Cache) 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated, unifi ed (on die) ne 1066 or 1333 (transfers data 4 times per clock), address transfers at 2 times per clock 64GB memory addressability (but limited by chipset), 36-bit addressing 45nm 65 watts 775-land Flip-Chip Land Grid Array (FC-LGA8) package requires LGA775 socket (socket also called Socket T) 3 Series and 4 Series Express Chipset families; other compatible chipsets (WOLF) January 2009
18 [Desktop] 2 Extreme Processor 2 Extreme processor for desktop systems Thermal Design Power 2 Extreme processor X GHz 4MB 1066 Dual 75W LGA775 Yes Yes Yes Yes July Extreme processor QX GHz 8MB 1066 Quad 75W LGA775 Yes Yes Yes Yes Apr Extreme processor QX GHz 8MB 1066 Quad 75W LGA775 Yes Yes Yes Yes Apr Extreme processor QX GHz 8MB 1333 Quad 75W LGA775 Yes Yes Yes Yes July Extreme processor QX GHz 12MB 1333 Quad 130W LGA775 Yes Yes Yes Yes v Extreme processor QX GHz 12MB 1600 Quad 136W LGA775 Yes Yes Yes Yes v Extreme processor QX GHz 12MB 1600 Quad 150W LGA771 Yes Yes Yes Yes Feb 2008 Socket Execute Disable Bit Enhanced nology 64 Conroe (X6800) or Kentsfield (QX6xxx) or Yorkfield-XE (QX9xxx) 2 Extreme processor Dual-core or quad-core Part of the Viiv technology for the home and vpro processor technology for iness Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost HD Boost 64 nology 1 nology micro-architecture ; QX9xxx: Streaming SIMD Extensions 4 (SSE4) and faster Super Shuffl e Engine Enhanced technology Two or four threads (two or four cores with no ) 64 nology (an extension to the IA-32 instruction set which adds 64 bit extensions to the x86 architecture) nology L1 data L1 instruction - size - data path L3 Execution units per core 64KB per core split between data (32KB) and instuction (32KB) 2x32KB data / integrated 2x32KB instruction / integrated X6800: 4MB / full speed / shared between both cores ( Advanced Smart Cache) QX6xxx: 8MB / full speed / 2 x 4MB shared on each die [dual-die] ( Advanced Smart Cache) QX9xxx: 12MB / full speed / 2 x 6MB shared on each die [dual-die] ( Advanced Smart Cache) 256-bit data path (32 bytes) / 64 byte line size / 8-way set associative / integrated / unifi ed (on die) ne 1066 or 1333 (transfers data 4 times per clock) / address transfers at 2 times per clock 64GB memory addressability (but limited by chipset) / 36-bit addressing Others: 65nm or 0.065u QX9xxx: 45nm or 0.045u 775-land Flip-Chip Land Grid Array (FC-LGA6) package requires LGA771 or LGA775 socket (also called Socket T) Q963, Q965, G965, P965, 975X Express Chipset families; 3 Series; other compatible chipsets (C2DX) February 2008
19 [Desktop] 2 Quad Processor 2 Quad processor for desktop systems s Hyper- Threading nology Total threads (logical) Enhanced nology 64 Trusted Execution 2 Quad processor Q GHz 8MB 1066 Quad 4 Yes Yes Yes Jan Quad processor Q GHz 8MB 1066 Quad 4 Yes Yes Yes July Quad processor Q GHz 4MB 1333 Quad 4 Yes Yes Aug Quad processor Q GHz 4MB 1333 Quad 4 Yes Yes Dec Quad processor Q GHz 6MB 1333 Quad 4 Yes Yes Yes Yes Mar Quad processor Q GHz 6MB 1333 Quad 4 Yes Yes Yes Yes Aug Quad processor Q GHz 12MB 1333 Quad 4 Yes Yes Yes Yes Mar Quad processor Q GHz 12MB 1333 Quad 4 Yes Yes Yes Yes Mar Quad processor Q GHz 12MB 1333 Quad 4 Yes Yes Yes Yes Aug 2008 Kentsfield (Q6xxx) or Yorkfield (Q8xxx, Q9xxx) 2 Quad desktop processor Quad-core (dual-core on dual-die so essentially two 2 Duo processors joined together) Supports 2 Processor with Viiv technology and 2 Processor with vpro technology when hardware and software requirements met Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost HD Boost 64 nology 1 nology Trusted Execution nology Dynamic Acceleration ; Q8xxx/Q9xxx: Streaming SIMD Extensions 4 (SSE4) and faster Super Shuffl e Engine Enhanced technology Two threads (two cores with no support provide two logical processors) 64 nology (an extension to the IA-32 instruction set which adds 64 bit extensions to the x86 architecture) Some: nology Some: Enables more secure platforms from software-based attacks with appropriate software - size - data path L3 Execution units per core Four 32KB per core, integrated 4MB, 6MB, 8MB, or 12MB / full speed, 2 x 3MB/4MB/6MB shared on each die [dual-die] ( Advanced Smart Cache) 256-bit data path (32 bytes), 64 byte line size, 8-way set associative, integrated ne 1066 or 1333 (transfers data 4 times per clock), address transfers at 2 times per clock 64GB memory addressability (but limited by chipset), 36-bit addressing Q6xxx: 65nm; Q8xxx/9xxx: 45nm Q6xxx: 65 watts; Q8xxx/9xxx: 95 watts Q6xxx: 775-land Flip-Chip Land Grid Array (FC-LGA6) package requires LGA775 socket (socket also called Socket T) Q8xxx/9xxx: 775-land Flip-Chip Land Grid Array (FC-LGA8) package requires LGA775 socket (socket also called Socket T) 3 Series and 4 Series desktop chipset; other compatible chipsets (C2Q) December 2008
20 [Desktop] i7 Processor i7 processor for desktops speed L3 Quick Path Interconnect i7-920 Processor 2.66GHz 8MB 4.8GT/s Quad Yes Yes Yes Yes Jan 2009 i7-940 Processor 2.93GHz 8MB 4.8GT/s Quad Yes Yes Yes Yes Jan 2009 Hyper- Threading 64 Turbo Boost Bloomfield (Nehalem) i7 processor Quad-core Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost HD Boost Execute Disable Bit 64 nology 1 nology Trusted Execution nology Dynamic Acceleration Turbo Boost Streaming SIMD Extensions (SSE2, SSE3) Streaming SIMD Extensions 4 (SSE4), Super Shuffl e Engine, SSE4.2 Enhanced technology, power management capabilities, multiple low-power states nology 2 Eight threads (four cores with support provide eight threads) 64 nology (extension to IA-32 instruction set adding 64-bit extensions) nology ne ne Turbo Boost nology 3 (scales processor frequency higher) L3 Memory controller Memory support (front side ) QuickPath Interconnect 64KB per core, split between data (32KB) and instuction (32KB), 8-way set associative 256KB per core, unifi ed, 8-way set associative 8MB shared among all cores ( Smart Cache), 16-way set associative Integrated memory controller DDR3, three channels max, two DIMMs per channel max, 24GB max, 800/1066 ne QuickPath Interconnect, point-to-point link between processor and chipset, 4.8GT/sec max 45nm 130 watts 1366-land Flip-Chip Land Grid Array (FC-LGA8) package requires LGA1366 socket X58 Express Chipset families; other compatible chipsets (I7) December 2008
21 [Desktop] i7 Processor Extreme Edition i7 processor Extreme Edition Quick Threading Turbo able Hyper- Avail- L3 Path for desktops and workstations speed Interconnect 64 Boost i7-965 Processor Extreme Edtion 3.2GHz 8MB 6.4GT/s Quad Yes Yes Yes Yes Jan 2009 Bloomfield (Nehalem) i7 processor Extreme Edition Quad-core Wide Dynamic Execution Smart Memory Access Advanced Digital Media Boost HD Boost Execute Disable Bit 64 nology 1 nology Trusted Execution nology Dynamic Acceleration Turbo Boost Streaming SIMD Extensions (SSE2, SSE3) Streaming SIMD Extensions 4 (SSE4), Super Shuffl e Engine, SSE4.2 Enhanced technology, power management capabilities, multiple low-power states nology 2 Eight threads (four cores with support provide eight threads) 64 nology (extension to IA-32 instruction set adding 64-bit extensions) nology ne ne Turbo Boost nology 3 (scales processor frequency higher) L3 Memory controller Memory support (front side ) QuickPath Interconnect 64KB per core, split between data (32KB) and instuction (32KB), 8-way set associative 256KB per core, unifi ed, 8-way set associative 8MB shared among all cores ( Smart Cache), 16-way set associative Integrated memory controller DDR3, three channels max, two DIMMs per channel max, 24GB max, 800/1066 ne QuickPath Interconnect, point-to-point link between processor and chipset, 6.4GT/sec max 45nm 130 watts 1366-land Flip-Chip Land Grid Array (FC-LGA8) package requires LGA1366 socket X58 Express Chipset families; other compatible chipsets (I7E) December 2008
22 This publication could include technical inaccuracies or typographical errors. References herein to Lenovo products and services do not imply that Lenovo intends to make them available in other countries. LENOVO PROVIDES THIS PUBLICATION AS IS WITHOUT WAR- RANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABIL- ITY OR FITNESS FOR A PARTICULAR PURPOSE. Some jurisdictions do not allow disclaimer of express of implied warranties; therefore this disclaimer may not apply to you nology (formerly EM64T): 64 nology (formerly EM64T) requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for 64 nology. Processor will not operate (including 32-bit operation) without an 64 nology-enabled BIOS. ormance will vary depending on your hardware and software configurations. 2 nology (HT nology): nology requires a computer system with a processor supporting HT nology and an HT nology-enabled chipset, BIOS, and operating system. ormance will vary depending on the specific hardware and software you use. For more information, including details on which processors support HT nology, see 3 Turbo Boost nology: Turbo Boost nology requires a PC with a processor with Turbo Boost nology capability. Turbo Boost nology performance varies depending on hardware, software, and overall system configuration. Check with your PC manufacturer on whether your system delivers Turbo Boost nology. See for more information. Trademarks: Lenovo, the Lenovo logo, New World. New Thinking., Access Connections, Rescue and Recovery, Think- Centre, ThinkPad, ThinkStation, ThinkVantage, and ThinkVision are trademarks of Lenovo. logo, Inside logo, and Inside, Pentium, Celeron and SpeedStep are trademarks or registered trademarks of Corporation or its subsidiaries in the United States and other countries. Other company, product and service names may be trademarks or service marks of others. Visit periodically for the latest information on safe and effective computing. Visit for the latest version of Personal s Reference., All rights reserved. Lenovo 1009 Think Place Morrisville, NC U.S.A. May 2009 tecbook.pdf
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