LT k. Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION

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1 FEATURES n 2A Internal Power Switch n Adjustable Switching Frequency n Single Feedback Resistor Sets n Synchronizable to External Clock n High Gain SHDN Pin Accepts Slowly Varying Input Signals n Wide Input Voltage Range: 2.5V to 32V n Low V CESAT Switch: 3mV at.5a (Typical) n Integrated Soft-Start Function n Easily Configurable as a Boost or Inverting Converter n User Configurable Undervoltage Lockout (UVLO) n Tiny 8-Lead 3mm 3mm DFN and 8-Lead MSOP Packages APPLICATIONS n VFD Bias Supplies n TFT-LCD Bias Supplies n GPS Receivers n DSL Modems n Local Power Supply DESCRIPTION LT358 Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization The LT 358 is a PWM DC/DC converter containing an internal 2A, 42V switch. The LT358 can be configured as either a boost, SEPIC or inverting converter. Capable of generating 2V at 55mA or 2V at 35mA from a 5V input, the LT358 is ideal for many local power supply designs. The LT358 has an adjustable oscillator, set by a resistor from the pin to ground. Additionally, the LT358 can be synchronized to an external clock. The free running or synchronized switching frequency range of the part can be set between 2kHz and 2.5MHz. The LT358 also features innovative SHDN pin circuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. Additional features such as frequency foldback and soft-start are integrated. The LT358 is available in tiny 3mm 3mm 8-lead DFN and 8-lead MSOP packages. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION.2MHz, 5V to 2V Boost Converter Achieves Over 88% Efficiency Efficiency and Power Loss 5V 2.2μF 4.2μH SW SHDN GND LT358 3k SYNC SS 75k.μF k nf μf 358 TA 2V 55mA EFFICIENCY (%) POWER LOSS (mw) LOAD CURRENT (ma) 358 TAb

2 LT358 ABSOLUTE MAXIMUM RATINGS (Note ) Voltage....3V to 32V SW Voltage....4V to 42V Voltage....3V to 5V SS and Voltage....3V to 2.5V Voltage....3V to 2V SHDN Voltage....3V to 32V SYNC Voltage....3V to 5.5V Operating Junction Temperature Range LT358E (Notes 2, 5)... 4 C to 25 C LT358I (Notes 2, 5)... 4 C to 25 C LT358H (Notes 2, 5)... 4 C to 5 C LT358MP (Notes 2, 5) C to 25 C Storage Temperature Range C to 5 C PIN CONFIGURATION TOP VIEW SW GND DD PACKAGE 8-LEAD (3mm 3mm) PLASTIC DFN T JMAX = 25 C, θ JA = 43 C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB SYNC SS SHDN SW TOP VIEW 9 GND 8 SYNC 7 SS 6 5 SHDN MS8E PACKAGE 8-LEAD PLASTIC MSOP θ JA = 35 C/W TO 4 C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PA MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT358EDD#PBF LT358EDD#TRPBF LCXY 8-Lead (3mm 3mm) Plastic DFN 4 C to 25 C LT358IDD#PBF LT358IDD#TRPBF LCXY 8-Lead (3mm 3mm) Plastic DFN 4 C to 25 C LT358EMS8E#PBF LT358EMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP 4 C to 25 C LT358IMS8E#PBF LT358IMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP 4 C to 25 C LT358HMS8E#PBF LT358HMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP 4 C to 5 C LT358MPMS8E#PBF LT358MPMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP 55 C to 25 C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: For more information on tape and reel specifications, go to: 2

3 Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT358E is guaranteed to meet performance specifications from C to 25 C junction temperature. Specifications over the 4 C to 25 C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT358I is guaranteed over the full 4 C to 25 C operating junction temperature range. The LT358H is guaranteed over the full 4 C to LT358 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. = 5V, V SHDN = unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Voltage Range l V Positive Feedback Voltage l V Negative Feedback Voltage l 5 2 mv Positive Pin Bias Current V = Positive Feedback Voltage, Current Into Pin l μa Negative Pin Bias Current V = Negative Feedback Voltage, Current Out of Pin (LT358E, LT358I, LT358MP) (LT358H) l l μa μa Error Amplifier Transconductance 23 μmhos Error Amplifier Voltage Gain 7 V/V Quiescent Current V SHDN = 2.5V, Not Switching.5 ma Quiescent Current in Shutdown V SHDN = V μa Reference Line Regulation 2.5V 32V..5 %/V Switching Frequency, f OSC R T = 45.3k (LT358E, LT358I, LT358H) R T = 45.3k (LT358MP) R T = 464k (LT358E, LT358I, LT358H) R T = 464k (LT358MP) Switching Frequency in Foldback Compared to Normal f OSC /4 Ratio Switching Frequency Set Range SYNCing or Free Running l 2 25 khz SYNC High Level for Synchronization l.3 V SYNC Low Level for Synchronization l.4 V SYNC Clock Pulse Duty Cycle V SYNC = V to 2V % Recommended Minimum SYNC Ratio f SYNC /f OSC 3/4 Minimum Off-Time 6 ns Minimum On-Time ns Switch Current Limit Minimum Duty Cycle (Note3) (LT358E, LT358I, LT358H) Minimum Duty Cycle (Note3) (LT358MP) Maximum Duty Cycle (Notes 3, 4) (LT358E, LT358I, LT358MP) Maximum Duty Cycle (Notes 3, 4) (LT358H) l l l l A A A A Switch V CESAT I SW =.5A 3 mv Switch Leakage Current V SW = 5V. μa Soft-Start Charging Current V SS =.5V l μa SHDN Minimum Input Voltage High Active Mode, SHDN Rising (LT358E, LT358I) Active Mode, SHDN Rising (LT358H, LT358MP) Active Mode, SHDN Falling (LT358E, LT358I) Active Mode, SHDN Falling (LT358H, LT358MP) SHDN Input Voltage Low Shutdown Mode l.3 V SHDN Pin Bias Current V SHDN = 3V 4 6 μa V SHDN =.3V V SHDN = V μa μa l l l l l l l l MHz MHz khz khz 5 C operating junction temperature range. The LT358MP is guaranteed over the full 55 C to 25 C operating junction temperature range. Operating lifetime is derated at junction temperatures greater than 25 C. Note 3: Current limit guaranteed by design and/or correlation to static test. Note 4: Current limit measured at equivalent switching frequency of 2.5MHz. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 5 C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. V V V V 3

4 LT358 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C unless otherwise specified Switch Current Limit at MHz Switch Saturation Voltage Switch Current Limit at Minimum Duty Cycle SWITCH CURRENT LIMIT (A) SATURATION VOLTAGE (mv) SWITCH CURRENT (A) DUTY CYCLE (%).5.5 SWITCH CURRENT (A) SS VOLTAGE (mv) G 358 G2 358 G3 SWITCH CURRENT LIMIT (A) Switch Current Limit at Minimum Duty Cycle 5 5 TEMPERATURE ( C) 358 G4 VOLTAGE (V) Positive Feedback Voltage TEMPERATURE ( C) 358 G5 5mV/DIV AC COUPLED V SW V/DIV I L.5A/DIV Switching Waveforms for Figure 4 Circuit 2ns/DIV 358 G6 FREQUENCY (MHz) Oscillator Frequency 2.7 R T = 35.7k R T = 75k. 5 5 TEMPERATURE ( C) NORMALIZED OSCILLATOR FREQUENCY (F/F NOM ) /2 /3 /4 Oscillator Frequency During Soft-Start T A = 35 C INVEING CONFIGURATIONS T A = C T A = 25 C VOLTAGE (V) BOOSTING CONFIGURATIONS..2 VOLTAGE (V) Internal UVLO 5 TEMPERATURE ( C) 358 G7 358 G8 358 G9 4

5 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C unless otherwise specified LT358 SHDN PIN CURRENT (μa) SHDN Pin Current SHDN Pin Current Active/Lockout Threshold C 2 C 5 C SHDN VOLTAGE (V) 358 G SHDN PIN CURRENT (μa) C 2 C C SHDN VOLTAGE (V) 358 G SHDN VOLTAGE (V) SHDN RISING SHDN FALLING 5 TEMPERATURE ( C) 358 G2 PIN FUNCTIONS (Pin ): Positive and Negative Feedback Pin. For a boost or inverting converter, tie a resistor from the pin to according to the following equations: ( ) R = ; Boost or SEPIC Converter ( R = 5mV ) ; Inverting Converter (Pin 2): Error Amplifier Output Pin. Tie external compensation network to this pin. (Pin 3): Input Supply Pin. Must be locally bypassed. SW (Pin 4): Switch Pin. This is the collector of the internal NPN Power switch. Minimize the metal trace area connected to this pin to minimize EMI. SHDN (Pin 5): Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. Drive below.24v (LT358E, LT358I) or.22v (LT358H, LT358MP) to disable the chip. Drive above.38v (LT358E, LT358I) or.4v (LT358H, LT358MP) to activate chip and restart the soft-start sequence. Do not float this pin. (Pin 6): Timing Resistor Pin. Adjusts the switching frequency. Place a resistor from this pin to ground to set the frequency to a fixed free running level. Do not float this pin. SS (Pin 7): Soft-Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged by a (nominally) 275k resistor to about 2.2V. SYNC (Pin 8): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed.3v, and the low level should be less.4v. Drive this pin to less than.4v to revert to the internal free running clock. See the Applications Information section for more information. GND (Exposed Pad Pin 9): Ground. Exposed pad must be soldered directly to local ground plane. 5

6 LT358 BLOCK DIAGRAM R C C SS C C C IN SHDN 5 3.3V UVLO.25V REFERENCE 4.6k 4.6k DISCHARGE DETECT A A2 SR2 R S Q 7 Q2 SS 275k SOFT- STA FREQUENCY FOLDBACK I LIMIT N 2 RAMP GENERATOR ADJUSTABLE OSCILLATOR SYNC BLOCK A3 COMPARATOR R SR S Q DRIVER A4 SW 4 Q.Ω GND 9 L D C R SYNC 8 6 R T 358 BD OPERATION The LT358 uses a constant-frequency, current mode control scheme to provide excellent line and load regulation. Refer to the Block Diagram which shows the LT358 in a boost configuration. At the start of each oscillator cycle, the SR latch (SR) is set, which turns on the power switch, Q. The switch current flows through the internal current sense resistor generating a voltage proportional to the switch current. This voltage (amplified by A4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator A3. When this voltage exceeds the level at the negative input of A3, the SR latch is reset, turning off the power switch. The level at the negative input of A3 ( pin) is set by the error amplifier A (or A2) and is simply an amplified version of the difference between the feedback voltage ( pin) and the reference 6 voltage (.25V or 5mV depending on the configuration). In this manner, the error amplifier sets the correct peak current level to keep the output in regulation. The LT358 has a novel pin architecture that can be used for either boost or inverting configurations. When configured as a boost converter, the pin is pulled up to the internal bias voltage of.25v by the R resistor connected from to. Comparator A2 becomes inactive and comparator A performs the inverting amplification from to. When the LT358 is in an inverting configuration, the pin is pulled down to 5mV by the R resistor connected from to. Comparator A becomes inactive and comparator A2 performs the noninverting amplification from to.

7 OPERATION SEPIC Topology The LT358 can be configured as a SEPIC (single-ended primary inductance converter). This topology allows for the input to be higher, equal, or lower then the desired output voltage. Output disconnect is inherently built into the SEPIC topology, meaning no DC path exists between the input and output. This is useful for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. Inverting Topology The LT358 can also work in a dual inductor inverting topology. The part s unique feedback pin allows for the inverting topology to be built by simply changing the connection of external components. This solution results in very low output voltage ripple due to inductor L2 in series with the output. Abrupt changes in output capacitor current are eliminated because the output inductor delivers current to the output during both the off-time and the on-time of the LT358 switch. Start-Up Operation Several functions are provided to enable a very clean start-up for the LT358. First, the SHDN pin voltage is monitored by an internal voltage reference to give a precise turn-on voltage level. An external resistor (or resistor divider) can be connected from the input power supply to the SHDN pin to provide a user-programmable undervoltage lockout function. LT358 Second, the soft-start circuitry provides for a gradual ramp-up of the switch current. When the part is brought out of shutdown, the external SS capacitor is first discharged (providing protection against SHDN pin glitches and slow ramping), then an integrated 275k resistor pulls the SS pin up to ~2.2V. By connecting an external capacitor to the SS pin, the voltage ramp rate on the pin can be set. Typical values for the soft-start capacitor range from nf to μf. Finally, the frequency foldback circuit reduces the switching frequency when the pin is in a nominal range of 35mV to 9mV. This feature reduces the minimum duty cycle that the part can achieve thus allowing better control of the switch current during start-up. When the voltage is pulled outside of this range, the switching frequency returns to normal. Current Limit and Thermal Shutdown Operation The LT358 has a current limit circuit not shown in the Block Diagram. The switch current is consistently monitored and not allowed to exceed the maximum switch current at a given duty cycle (see the Electrical Characteristics table). If the switch current reaches this value, the SR latch (SR) is reset regardless of the state of the comparator (A/A2). Also not shown in the Block Diagram is the thermal shutdown circuit. If the temperature of the part exceeds approximately 65 C, the SR2 latch is set regardless of the state of the comparator (A/A2). A full soft-start cycle will then be initiated. The current limit and thermal shutdown circuits protect the power switch as well as the external components connected to the LT358. > OR = OR < SHUTDOWN C L SW LT358 SHDN C2 L2 D R SHUTDOWN C L C2 SW D LT358 SHDN L2 R VOUT SYNC GND SS C SS RC CC C3 SYNC GND SS C SS RC CC C3 358 F 358 F2 Figure. SEPIC Topology Allows for the Input to Span the Output Voltage. Coupled or Uncoupled Inductors Can Be Used. Follow Noted Phasing if Coupled Figure 2. Dual Inductor Inverting Topology Results in Low Output Ripple. Coupled or Uncoupled Inductors Can Be Used. Follow Noted Phasing if Coupled 7

8 LT358 APPLICATIONS INFORMATION Setting Output Voltage The output voltage is set by connecting a resistor (R ) from to the pin. R is determined from the following equation: R = V 83.3µA where V is.25v (typical) for non-inverting topologies (i.e., boost and SEPIC regulators) and 5mV (typical) for inverting topologies (see the Electrical Characteristics). Power Switch Duty Cycle In order to maintain loop stability and deliver adequate current to the load, the power NPN (Q in the Block Diagram) cannot remain on for % of each clock cycle. The maximum allowable duty cycle is given by: DC MAX = (T P MinOff Time) T P % where T P is the clock period and Min Off Time (found in the Electrical Characteristics) is typically 6ns. The application should be designed so that the operating duty cycle does not exceed DC MAX. Duty cycle equations for several common topologies are given below, where V D is the diode forward voltage drop and V CESAT is typically 3mV at.5a. For the boost topology: DC V D V D V CESAT For the SEPIC or dual inductor inverting topology (see Figures and 2): V DC D V D V CESAT The LT358 can be used in configurations where the duty cycle is higher than DC MAX, but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. Inductor Selection General Guidelines: The high frequency operation of the LT358 allows for the use of small surface mount inductors. For high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. To improve efficiency, choose inductors with more volume for a given inductance. The inductor should have low DCR (copper wire resistance) to reduce I 2 R losses, and must be able to handle the peak inductor current without saturating. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology, where each inductor only carries a fraction of the total switch current. Molded chokes or chip inductors usually do not have enough core area to support peak inductor currents in the 2A to 3A range. To minimize radiated noise, use a toroidal or shielded inductor. Note that the inductance of shielded types will drop more as current increases, and will saturate more easily. See Table for a list of inductor manufacturers. Thorough lab evaluation is recommended to verify that the following guidelines properly suit the final application. Table.Inductor Manufacturers Coilcraft DO336P, MSS734 and LPS48 Series Coiltronics DR, LD and CD Series Murata LQH55D and LQH66S Series Sumida CDRH5D8B/HP, CDR6D23MN, CDRH6D26/HP, CDRH6D28, CDR7D28MN and CDRH5R Series TDK RLF73 and VLCF42 Series Würth WE-PD and WE-PD2 Series Minimum Inductance: Although there can be a tradeoff with efficiency, it is often desirable to minimize board space by choosing smaller inductors. When choosing an inductor, there are two conditions that limit the minimum inductance; () providing adequate load current, and (2) avoidance of subharmonic oscillation. Choose an inductance that is high enough to meet both of these requirements. Adequate Load Current : Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be 8

9 APPLICATIONS INFORMATION provided to a load (I OUT ). In order to provide adequate load current, L should be at least: DC V L > IN 2(f) I LIM I OUT η for boost, topologies, or: DC V L > IN 2(f) I LIM I OUT I OUT η for the SEPIC and inverting topologies. where: L = L L2 for uncoupled dual inductor topologies DC = switch duty cycle (see previous section) I LIM = switch current limit, typically about 2.4A at 5% duty cycle (see the Typical Performance Characteristics section). η = power conversion efficiency (typically 88% for boost and 75% for dual inductor topologies at high currents). f = switching frequency Negative values of L indicate that the output load current I OUT exceeds the switch current limit capability of the LT358. Avoiding Subharmonic Oscillations: The LT358 s internal slope compensation circuit will prevent subharmonic oscillations that can occur when the duty cycle is greater than 5%, provided that the inductance exceeds a minimum value. In applications that operate with duty cycles greater than 5%, the inductance must be at least: ( ) L > 2 DC ( DC) (f) for boost, coupled inductor SEPIC, and coupled inductor inverting topologies, or: ( ) L L2> 2 DC ( DC) (f) LT358 for the uncoupled inductor SEPIC and uncoupled inductor inverting topologies. Maximum Inductance: Excessive inductance can reduce current ripple to levels that are difficult for the current comparator (A3 in the Block Diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: L MAX = V CESAT I MIN RIPPLE DC f where L MAX is L L2 for uncoupled dual inductor topologies and I MIN-RIPPLE is typically 95mA. Current Rating: Finally, the inductor(s) must have a rating greater than its peak operating current to prevent inductor saturation resulting in efficiency loss. In steady state, the peak input inductor current (continuous conduction mode only) is given by: I L PEAK = I OUT η DC 2 L f for the boost, uncoupled inductor SEPIC and uncoupled inductor inverting topologies. For uncoupled dual inductor topologies, the peak output inductor current is given by: I L2 PEAK =I OUT DC ( ) 2 L2 f For the coupled inductor topologies: I OUT V OUT DC η 2 L f Note: Inductor current can be higher during load transients. It can also be higher during start-up if inadequate soft-start capacitance is used. Capacitor Selection Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice, as they have an extremely low ESR and are available in very small packages. X5R or X7R dielectrics are preferred, as 9

10 LT358 APPLICATIONS INFORMATION these materials retain their capacitance over wider voltage and temperature ranges. A 4.7μF to 2μF output capacitor is sufficient for most applications, but systems with very low output currents may need only a μf or 2.2μF output capacitor. Always use a capacitor with a sufficient voltage rating. Many capacitors rated at 2.2μF to 2μF, particularly 85 or 63 case sizes, have greatly reduced capacitance at the desired output voltage. Solid tantalum or OS-CON capacitors can be used, but they will occupy more board area than a ceramic and will have a higher ESR with greater output ripple. Ceramic capacitors also make a good choice for the input decoupling capacitor, which should be placed as closely as possible to the LT358. A 2.2μF to 4.7μF input capacitor is sufficient for most applications. Table 2 shows a list of several ceramic capacitor manufacturers. Consult the manufacturers for detailed information on their entire selection of ceramic parts. Table 2. Ceramic Capacitor Manufacturers Kemet Murata Taiyo Yuden Compensation Adjustment To compensate the feedback loop of the LT358, a series resistor-capacitor network in parallel with a single capacitor should be connected from the pin to GND. For most applications, the series capacitor should be in the range of 47pF to 2.2nF with nf being a good starting value. The parallel capacitor should range in value from pf to pf with 47pF a good starting value. The compensation resistor, R C, is usually in the range of 5k to 5k. A good technique to compensate a new application is to use a kω potentiometer in place of series resistor R C. With the series capacitor and parallel capacitor at nf and 47pF respectively, adjust the potentiometer while observing the transient response and the optimum value for R C can be found. Figures 3a to 3c illustrate this process for the circuit of Figure 4 with a load current stepped between 4mA and 5mA. Figure 3a shows the transient response with R C equal to k. The phase margin is poor, as evidenced by the excessive ringing in the output voltage and inductor current. In Figure 3b, the value of R C is increased to 3k, which results in a more damped response. Figure 3c shows the results when R C is increased further to k. The transient response is nicely damped and the compensation procedure is complete. 2mV/DIV AC COUPLED 2mV/DIV AC COUPLED I L.5A/DIV I L.5A/DIV R C = k 2μs/DIV 358 F3a R C = 3k 2μs/DIV 358 F3b Figure 3a. Transient Response Shows Excessive Ringing Figure 3b. Transient Response Is Better 2mV/DIV AC COUPLED I L.5A/DIV R C = k 2μs/DIV 358 F3c Figure 3c. Transient Response Is Well Damped

11 APPLICATIONS INFORMATION Compensation Theory Like all other current mode switching regulators, the LT358 needs to be compensated for stable and efficient operation. Two feedback loops are used in the LT358 a fast current loop which does not require compensation, and a slower voltage loop which does. Standard bode plot analysis can be used to understand and adjust the voltage feedback loop. As with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. Figure 4 shows the key equivalent elements of a boost converter. Because of the fast current control loop, the power stage of the IC, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier g mp and the current controlled current source (which converts I VIN to η / I VIN ). g mp acts as a current source where the peak input current, I VIN, is proportional to the voltage. η is the efficiency of the switching regulator, and is typically about 88%. Note that the maximum output currents of g mp and g ma are finite. The limits for g mp are in the Electrical Characteristics section (switch current limit), and g ma is nominally limited to about ±2μA. LT358 From Figure 4, the DC gain, poles and zeros can be calculated as follows: 2 Output Pole: P= 2 π R L C OUT Error Amp Pole: P2 = 2 π R O R C C C Error Amp Zero: Z= 2 π R C C C DC Gain: (Breaking Loop at Pin) A DC = A OL () = V C I VIN V V C I VIN V = ( g ma R ) g mp η R L 2.5R2 R.5R2 ESR Zero: Z2 = 2 π R ESR C OUT RHP Zero: Z3 = 2 R L 2 π 2 L C F V C g ma R2 R C R O C C g mp IVIN.25V REFERENCE C C : COMPENSATION CAPACITOR C OUT : OUTPUT CAPACITOR C PL : PHASE LEAD CAPACITOR C F : HIGH FREQUENCY FILTER CAPACITOR g ma : TRANSCONDUCTANCE AMPLIFIER INSIDE IC g mp : POWER STAGE TRANSCONDUCTANCE AMPLIFIER R C : COMPENSATION RESISTOR R L : OUTPUT RESISTANCE DEFINED AS DIVIDED BY I LOAD(MAX) R O : OUTPUT RESISTANCE OF g ma R, R2: FEEDBACK RESISTOR DIVIDER NETWORK R ESR : OUTPUT CAPACITOR ESR Figure 4. Boost Converter Equivalent Model R2 I VIN C PL R 358 F4 R ESR C OUT R L High Frequency Pole: P3 > f S 3 Phase Lead Zero: Z4 = 2 π R C PL Phase Lead Pole: P4 = R R2 2 π 2 R R2 2 Error Amp Filter Pole: C P5 = 2 π R C R,C F < C O C R C R F O C PL The current mode zero (Z3) is a right-half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection.

12 LT358 APPLICATIONS INFORMATION Using the circuit in Figure 4 as an example, Table 3 shows the parameters used to generate the bode plot shown in Figure 5. Table 3. Bode Plot Parameters PARAMETER VALUE UNITS COMMENT R L 2.8 Ω Application Specific C OUT μf Application Specific R ESR mω Application Specific R O 35 kω Not Adjustable C C pf Adjustable C F pf Optional/Adjustable C PL pf Optional/Adjustable R C kω Adjustable R 3 kω Adjustable R2 4.6 kω Not Adjustable 2 V Application Specific 5 V Application Specific g ma 23 μmho Not Adjustable g mp 7 mho Not Adjustable L 4.2 μh Application Specific f S.2 MHz Adjustable In Figure 5, the phase is 4 when the gain reaches db giving a phase margin of 4. The crossover frequency is khz, which is more than three times lower than the frequency of the RHP zero to achieve adequate phase margin. GAIN (db) GAIN PHASE 4 AT khz 2 k k k M FREQUENCY (Hz) 358 F5 Figure 5. Bode Plot for Example Boost Converter PHASE (DEG) Diode Selection Schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the LT358. The Microsemi UPS2 is a very good choice. Where the input-to-output voltage differential exceeds 2V, use the UPS4 (a 4V diode). These diodes are rated to handle an average forward current of A. Oscillator The operating frequency of the LT358 can be set by the internal free-running oscillator. When the SYNC pin is driven low (<.4V), the frequency of operation is set by a resistor from R T to ground. An internally trimmed timing capacitor resides inside the IC. The oscillator frequency is calculated using the following formula: f OSC = 9.9 (R T ) where f OSC is in MHz and R T is in kω. Conversely, R T (in kω) can be calculated from the desired frequency (in MHz) using: R T = 9.9 f OSC Clock Synchronization The operating frequency of the LT358 can be synchronized to an external clock source. To synchronize to the external source, simply provide a digital clock signal into the SYNC pin. The LT358 will operate at the SYNC clock frequency. The LT358 will revert to the internal free-running oscillator clock after SYNC is driven low for a few free-running clock periods. Driving SYNC high for an extended period of time effectively stops the operating clock and prevents latch SR from becoming set (see the Block Diagram). As a result, the switching operation of the LT358 will stop. The duty cycle of the SYNC signal must be between 35% and 65% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: 2

13 LT358 APPLICATIONS INFORMATION () SYNC may not toggle outside the frequency range of 2kHz to 2.5MHz unless it is stopped low to enable the free-running oscillator. (2) The SYNC frequency can always be higher than the free-running oscillator frequency, f OSC, but should not be less than 25% below f OSC. Operating Frequency Selection There are several considerations in selecting the operating frequency of the converter. The first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. For example, in products incorporating RF communications, the 455kHz IF frequency is sensitive to any noise, therefore switching above 6kHz is desired. Some communications have sensitivity to.mhz, and in that case, a.5mhz switching converter frequency may be employed. The second consideration is the physical size of the converter. As the operating frequency goes up, the inductor and filter capacitors go down in value and size. The tradeoff is efficiency, since the switching losses due to NPN base charge (see Thermal Calculations), Schottky diode charge, and other capacitive loss terms increase proportionally with frequency. Soft-Start The LT358 contains a soft-start circuit to limit peak switch currents during start-up. High start-up current is inherent in switching regulators in general since the feedback loop is saturated due to being far from its final value. The regulator tries to charge the output capacitor as quickly as possible, which results in large peak currents. The start-up current can be limited by connecting an external capacitor (typically nf to μf) to the SS pin. This capacitor is slowly charged to ~2.2V by an internal 275k resistor once the part is activated. SS pin voltages below ~.V reduce the internal current limit. Thus, the gradual ramping of the SS voltage also gradually increases the current limit as the capacitor charges. This, in turn, allows the output capacitor to charge gradually toward its final value while limiting the start-up current. In the event of a commanded shutdown or lockout (SHDN pin), internal undervoltage lockout (UVLO) or a thermal lockout, the soft-start capacitor is automatically discharged to ~2mV before charging resumes, thus assuring that the soft-start occurs after every reactivation of the chip. Shutdown The SHDN pin is used to enable or disable the chip. For most applications, SHDN can be driven by a digital logic source. Voltages above.38v enable normal active operation. Voltages below 3mV will shutdown the chip, resulting in extremely low quiescent current. While the SHDN voltage transitions through the lockout voltage range (.3V to.24v) the power switch is disabled and the SR2 latch is set (see the Block Diagram). This causes the soft-start capacitor to begin discharging, which continues until the capacitor is discharged and active operation is enabled. Although the power switch is disabled, SHDN voltages in the lockout range do not necessarily reduce quiescent current until the SHDN voltage is near or below the shutdown threshold. Also note that SHDN can be driven above or as long as the SHDN voltage is limited to less than 32V..38V.24V SHDN (V).3V.V ACTIVE (NORMAL OPERATION) (HYSTERESIS AND TOLERANCE) LOCKOUT (POWER SWITCH OFF, SS CAPACITOR DISCHARGED) SHUTDOWN (LOW QUIESCENT CURRENT) 358 F6 Figure 6. Chip States vs SHDN Voltage Configurable Undervoltage Lockout Figure 7 shows how to configure an undervoltage lockout (UVLO) for the LT358. Typically, UVLO is used in situations where the input supply is current-limited, has a relatively high source resistance, or ramps up/down slowly. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current-limit or latch low under low 3

14 LT358 APPLICATIONS INFORMATION R UVLO R UVLO2 (OPTIONAL) SHDN GND Figure 7. Configurable UVLO source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur. The shutdown pin comparator has voltage hysteresis with typical thresholds of.32v (rising) and.29v (falling). Resistor R UVLO2 is optional. R UVLO2 can be included to reduce the overall UVLO voltage variation caused by variations in SHDN pin current (see the Electrical Characteristics). A good choice for R UVLO2 is k ±%. After choosing a value for R UVLO2, R UVLO can be determined from either of the following: V R UVLO = IN.32V.32V.6μA R UVLO2 or V R UVLO = IN.29V.29V.6μA R UVLO2.6μA AT.3V where V IN and V IN are the voltages when rising or falling respectively. For example, to disable the LT358 for voltages below 3.5V using the single resistor configuration, choose:.3v 3.5V.29V R UVLO = =9.5k.29V.6μA ACTIVE/ LOCKOUT 358 F7 To activate the LT358 for voltage greater than 4.5V using the double resistor configuration, choose R UVLO2 = k and: 4.5V.32V R UVLO = =22.k.32V.6μA k Internal Undervoltage Lockout The LT358 monitors the supply voltage in case drops below a minimum operating level (typically about 2.3V). When is detected low, the power switch is deactivated, and while sufficient voltage persists, the soft-start capacitor is discharged. After is detected high, the power switch will be reactivated and the soft-start capacitor will begin charging. Thermal Considerations For the LT358 to deliver its full output power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. This is accomplished by taking advantage of the thermal pad on the underside of the IC. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into a copper plane with as much area as possible. Thermal Lockout If the die temperature reaches approximately 65 C, the part will go into thermal lockout, the power switch will be turned off and the soft-start capacitor will be discharged. The part will be enabled again when the die temperature has dropped by ~5 C (nominal). Thermal Calculations Power dissipation in the LT358 chip comes from four primary sources: switch I 2 R loss, NPN base drive (AC), NPN base drive (DC), and additional input current. The following formulas can be used to approximate the power losses. These formulas assume continuous mode operation, 4

15 LT358 APPLICATIONS INFORMATION so they should not be used for calculating efficiency in discontinuous mode or at light load currents. Average Input Current: I IN = I OUT η Switch I 2 R Loss: P SW = (DC)(I IN ) 2 (R SW ) Base Drive Loss (AC): P BAC =3n(I IN )( )(f) Base Drive Loss (DC): P BDC = ( )(I IN )(DC) 5 Input Power Loss: P INP =7mA( ) where: R SW = switch resistance (typically 2mΩ at.5a) DC = duty cycle (see the Power Switch Duty Cycle section for formulas) η = power conversion efficiency (typically 88% at high currents) Example: boost configuration, = 5V, = 2V, I OUT =.5A, f =.25MHz, V D =.5V: I IN =.36A DC = 6.5% P SW = 228mW P BAC = 27mW P BDC = 84mW P INP = 35mW Total LT358 power dissipation (P TOT ) = 67mW Thermal resistance for the LT358 is influenced by the presence of internal, topside or backside planes. To calculate die temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: T J = T A θ JA P TOT where T J = junction temperature, T A = ambient temperature, θ JA = 43 C/W for the 3mm 3mm DFN package and 35 C/W to 4 C/W for the MSOP Exposed Pad package. P TOT is calculated above. Ramp Rate While initially powering a switching converter application, the ramp rate should be limited. High ramp rates can cause excessive inrush currents in the passive components of the converter. This can lead to current and/or voltage overstress and may damage the passive components or the chip. Ramp rates less than 5mV/μs, depending on component parameters, will generally prevent these issues. Also, be careful to avoid hot-plugging. Hot-plugging occurs when an active voltage supply is instantly connected or switched to the input of the converter. Hot-plugging results in very fast input ramp rates and is not recommended. Finally, for more information, refer to Linear application note AN88, which discusses voltage overstress that can occur when an inductive source impedance is hot-plugged to an input pin bypassed by ceramic capacitors. Layout Hints As with all high frequency switchers, when considering layout, care must be taken to achieve optimal electrical, thermal and noise performance. One will not get advertised performance with a careless layout. For maximum efficiency, switch rise and fall times are typically in the 5ns to ns range. To prevent noise, both radiated and conducted, the high speed switching current path, shown in Figure 8, must be kept as short as possible. This is implemented in the suggested layout of a boost configuration in Figure 9. Shortening this path will also reduce the parasitic trace inductance. At switch-off, this parasitic inductance produces a flyback spike across the LT358 switch. When operating at higher currents and output voltages, with poor layout, this spike can generate voltages across the LT358 that may exceed its absolute maximum rating. A ground plane should also be used under the switcher circuitry to prevent interplane coupling and overall noise. The and components should be kept as far away as practical from the switch node. The ground for these components should be separated from the switch current path. Failure to do so can result in poor stability or subharmonic oscillation. 5

16 LT358 APPLICATIONS INFORMATION Board layout also has a significant effect on thermal resistance. The exposed package ground pad is the copper plate that runs under the LT358 die. This is a good thermal path for heat out of the package. Soldering the pad onto the board reduces die temperature and increases the power capability of the LT358. Provide as much copper area as possible around this pad. Adding multiple feedthroughs around the pad to the ground plane will also help. Figures 9 and show the recommended component placement for the boost and SEPIC configurations, respectively. Layout Hints for Inverting Topology Figure shows recommended component placement for the dual inductor inverting topology. Input bypass capacitor, C, should be placed close to the LT358, as shown. The load should connect directly to the output capacitor, C2, for best load regulation. You can tie the local ground into the system ground plane at the C3 ground terminal. The cut ground copper at D s cathode is essential to obtain low noise. This important layout issue arises due to the chopped nature of the currents flowing in Q and D. If they are both tied directly to the ground plane before being combined, switching noise will be introduced into the ground plane. It is almost impossible to get rid of this noise, once present in the ground plane. The solution is to tie D s cathode to the ground pin of the LT358 before the combined currents are dumped in the ground plane as drawn in Figure 2, Figure 2 and Figure 3. This single layout technique can virtually eliminate high frequency spike noise, so often present on switching regulator outputs. L C D SW LT358 HIGH FREQUENCY SWITCHING PATH C2 LOAD GND 358 F8 Figure 8. High Speed Chopped Switching Path for Boost Topology 6

17 LT358 APPLICATIONS INFORMATION GND C 2 GND SYNC C SYNC 5 L SHDN L SW 4 SHDN SW L2 C2 D C2 358 F9 VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE D C3 VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE 358 F Figure 9. Suggested Component Placement for Boost Topology (Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed Pad) Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance Figure. Suggested Component Placement for Sepic Topology (Both DFN And MSOP Packages. Not to Scale). Pin 9 (Exposed Pad) Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance GND C L SW 3 SYNC SHDN L2 C2 D C3 VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE 358 F Figure. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale). Note Cut in Ground Copper at Diode s Cathode. Pin 9 (Exposed Pad) Must be Soldered Directly to Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance 7

18 LT358 APPLICATIONS INFORMATION V CESAT ( ) L SW C2 SWX L2 Q D C C3 R LOAD 358 F2 Figure 2. Switch-On Phase of an Inverting Converter. L and L2 Have Positive di/dt V D V D L SW C2 SWX L2 Q D C C3 R LOAD 358 F3 Figure 3. Switch-Off Phase of an Inverting Converter. L and L2 Currents Have Negative di/dt 5V C 2.2μF 75k L 4.2μH D SW SHDN GND LT358 3k SYNC SS.μF k nf 2V C2 55mA μf C: 2.2μF, 25V, X5R, 26 C2: μf, 25V, X5R, 26 D: MICROSEMI UPS2 L: SUMIDA CDR6D23MN-4R2 358 F4 Figure 4..2MHz, 5V to 2V Boost Converter 8

19 TYPICAL APPLICATIONS 75kHz, 5V to 4V, 5mA Boost Converter LT358 5V C 2.2μF 2k L 47μH D SW SHDN GND LT k SYNC SS.μF k 4.7nF 47pF 4V C2 5mA 2.2μF 358 TA2 C: 2.2μF, 25V, X5R, 26 C2: 2.2μF, 5V, X5R, 26 D: MICROSEMI UPS4 L: SUMIDA CDRH5R-47 Wide Input Range SEPIC Converter with 5V Output Switches at 2.5MHz 2.6V TO 2V OPERATING 2V TO 32V TRANSIENT C 2.2μF 35.7k L 4.7μH C3 μf SW SHDN GND LT k SYNC SS.μF D L2 4.7μH k nf 22pF C2 μf 5V, 6mA ( = 5V OR HIGHER) 5mA ( = 4V) 4mA ( = 3V) 3mA ( = 2.6V) 358 TA3a C: 2.2μF, 35V, X5R, 26 C2: μf, V, X5R, 26 C3: μf, 5V, X5R, 85 D: MICROSEMI UPS4 L, L2: TDK VLCF42T-4R7NR2 Transient Response with 4mA to 5mA Output Load Step mv/div AC COUPLED I L I L2.5A/DIV = 2V μs/div 358 TA3b 9

20 LT358 TYPICAL APPLICATIONS VFD (Vacuum Flourescent Display) Power Supply Switches at 2MHz to Avoid AM Band Danger High Voltage! Operation by High Voltage Trained Personnel Only R2 Ω D D2 C5 μf 2 95V 8mA 9V TO 6V 3.3V L μh C7 μf R Ω D3 D4 C4 μf 64V 4mA SW C6 μf D5 C2 4.7μF C 4.7μF SHDN LT358 GND SYNC SS 45.3k.μF k 2.2nF 383k 47pF C3 μf C, C2: 4.7μF, 25V, X5R, 26 C3-C7: μf, 5V, X5R, 85 D-D4: ON SEMICONDUCTOR MBR54 D5: MICROSEMI UPS4 L: SUMIDA CDR6D28MNNP- R, R2:.5W 358 TA4 2

21 LT358 TYPICAL APPLICATIONS High Voltage Positive Power Supply Uses Tiny 5.8mm 5.8mm 3mm Transformer and Switches at 2kHz Danger High Voltage! Operation by High Voltage Trained Personnel Only 3.3V TO 5V T :.4 7, 8 4.7μH 5, 6 4 D2 D C2 68nF 35V 4.5mA ( = 5V) 2.5mA ( = 3.3V) C 2.2μF 464k SW SHDN GND LT358 SYNC SS.47μF R 4.22M* k nf C: 2.2μF, 25V, X5R, 26 C2: TDK C3225X7R2J683M D: VISHAY GSD24S DUAL DIODE CONNECTED IN SERIES D2: ON SEMICONDUCTOR MBR54 T: TDK LDT56563T-4 pf 358 TA5a FOR ANY BETWEEN 5V TO 35V, CHOOSE R ACCORDING TO.25 R = 83.3μA FOR 5PUT, KEEP MAXIMUM OUTPUT POWER AT.58W FOR 3.3PUT, KEEP MAXIMUM OUTPUT POWER AT.88W *MAY REQUIRE MULTIPLE SERIES RESISTORS TO COMPLY WITH MAXIMUM VOLTAGE RATINGS Start-Up Waveforms I PRIMARY A/DIV 5V/DIV 5PUT NO LOAD 2ms/DIV 358 TA5b Switching Waveforms 2V/DIV AC COUPLED I PRIMARY A/DIV 5PUT 4.5mA LOAD 2μs/DIV 358 TA5c 2

22 LT358 TYPICAL APPLICATIONS High Voltage Negative Power Supply Uses Tiny 5.8mm 5.8mm 3mm Transformer and Switches at 2kHz Danger High Voltage! Operation by High Voltage Trained Personnel Only 3.3V TO 5V 7, 8 4.7μH 5, 6 T :.4 4 D C2 68nF D2 FOR ANY BETWEEN 5V TO 35V, CHOOSE R ACCORDING TO C 2.2μF SW SHDN GND LT358 R 4.22M* SYNC SS k 464k.47μF nf pf 35V 4.5mA ( = 5V) 2.5mA ( = 3.3V) V R OUT = 83.3μA FOR 5PUT, KEEP MAXIMUM OUTPUT POWER AT.58W FOR 3.3PUT, KEEP MAXIMUM OUTPUT POWER AT.88W *MAY REQUIRE MULTIPLE SERIES RESISTORS TO COMPLY WITH MAXIMUM VOLTAGE RATINGS C: 2.2μF, 25V, X5R, 26 C2: TDK C3225X7R2J683M D: VISHAY GSD24S DUAL DIODE CONNECTED IN SERIES D2: ON SEMICONDUCTOR MBR54 T: TDK LDT56563T TA6 22

23 LT358 TYPICAL APPLICATIONS 5V to 2V Boost Converter Switches at 2.5MHz and Uses a Tiny 4mm 4mm.7mm Inductor 5V C 4.7μF 35.7k L 3.3μH D SW SHDN GND LT358 3k SYNC SS.μF k 2.2nF 47pF 2V C2 5mA 4.7μF 358 TA7a C, C2: 4.7μF, 25V, X5R, 26 D: MICROSEMI UPS2 L: COILCRAFT LPS48-332ML Efficiency and Power Loss vs Load Current 95 4 EFFICIENCY (%) POWER LOSS (W) LOAD CURRENT (ma) 358 TA7b Transient Response with 4mA to 5mA to 4mA Output Load Step Start-Up Waveforms.5V/DIV AC COUPLED I L.5A/DIV 5V/DIV I L A/DIV V SHDN V/DIV μs/div 358 TA7c 5mA LOAD 2ms/DIV 358 TA7d 23

24 LT358 TYPICAL APPLICATIONS 5V Output Inverting Converter Switches at 2.5MHz and Accepts Inputs Between 3.3V to 2V 3.3V TO 2V C 2.2μF L 4.7μH C3 μf SW SHDN GND LT358 SYNC SS 35.7k.μF D L2 4.7μH 6.4k k pf 2.2nF 5V 8mA ( = 2V) C2 62mA ( = 5V) μf 45mA ( = 3.3V) C: 2.2μF, 25V, X5R, 26 C2: μf, 25V, X5R, 26 C3: μf, 5V, X5R, 85 D: CENTRAL SEMI CMMSH-4 L, L2: COILCRAFT LSP48-472ML 358 TA8a Efficiency and Power Loss vs Load Current = 5V 2 EFFICIENCY (%) POWER LOSS (W) LOAD CURRENT (ma) 358 TA8b 24

25 PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm 3mm) (Reference LTC DWG # Rev C) LT (2 SIDES) PACKAGE OUTLINE BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R =.25 TYP PIN TOP MARK (NOTE 6).2 REF 3.. (4 SIDES) (2 SIDES) BOTTOM VIEW EXPOSED PAD.5 BSC (DD8) DFN 59 REV C NOTE:. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M-229 VARIATION OF (WEED-) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.5mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON TOP AND BOTTOM OF PACKAGE 25

26 LT358 PACKAGE DESCRIPTION MS8E Package 8-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # Rev F).88.2 (.74.4) (.35.5) BOTTOM VIEW OF EXPOSED PAD OPTION.88 (.74).68 (.66).29 REF 5.23 (.26) MIN (.65.5) TYP (.66.4) (.26.36).65 (.256) BSC 3..2 (.8.4) (NOTE 3) DETAIL B.52 (.25) REF.5 REF DETAIL B CORNER TAIL IS PA OF THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE RECOMMENDED SOLDER PAD LAYOUT GAUGE PLANE.8 (.7).254 (.) DETAIL A DETAIL A NOTE:. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 6 TYP (.2.6) SEATING PLANE (.93.6). (.43) MAX (.9.5) TYP.65 (.256) BSC DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED.52mm (.6") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED.52mm (.6") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.2mm (.4") MAX 6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED.254mm (.") PER SIDE (.8.4) (NOTE 4).86 (.34) REF.6.58 (.4.2) MSOP (MS8E) 2 REV F 26

27 LT358 REVISION HISTORY (Revision history begins at Rev F) REV DATE DESCRIPTION PAGE NUMBER F 6/ Added GND to the Pin Configuration section. Revised Note 2 in the Electrical Characteristics section. Revised Graph G8 in the Typical Performance Characteristics section. Revised the Applications Information section. Revised Table 3 in the Applications Information section. Revised Figure 3 in the Applications Information section. Updated drawing TAa in the Typical Applications section. Updated Related Parts table G 9/ Added H- and MP-Grade information to Absolute Maximum Ratings, Order Information, Electrical Characteristics and Pin Functions sections. Added text at end of General Guidelines and revised equations under Avoiding Subharmonic Oscillations in Applications Information section. 2, 3, 5 8, 9 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27

28 LT358 TYPICAL APPLICATION 5V TO 2V 2MHz Inverting Converter Generates 2V from a 5V to 2V Input C 2.2μF L μh C3 μf SW SHDN GND LT358 SYNC SS 45.3k.μF C: 2.2μF, 25V, X5R, 26 C2: μf, 25V, X5R, 26 C3: μf, 5V, X5R, 85 D: CENTRAL SEMI CMMSH-4 L: SUMIDA CDRH6D28NP-NC L2: SUMIDA CDRH3D28NP-22NC L2 22μH D 47k k 2.2nF 47pF 358 TA9a 2V 5mA ( = 2V) C2 35mA ( = 5V) μf EFFICIENCY (%) Efficiency and Power Loss vs Load Current = 5V LOAD CURRENT (ma) 358 TA9b POWER LOSS (mw) RELATED PAS PA NUMBER DESCRIPTION COMMENTS LT3 2A (I SW ), 4V,.2MHz High Efficiency Step-Up DC/DC Converter : 2.3V to 6V, (MAX) = 4V, I Q = 3mA, I SD < μa, ThinSOT Package LT63 55mA (I SW ),.4MHz High Efficiency Step-Up DC/DC Converter :.9V to V, (MAX) = 34V, I Q = 3mA, I SD < μa, ThinSOT Package LT68.5A (I SW ),.25MHz High Efficiency Step-Up DC/DC Converter :.6V to 8V, (MAX) = 35V, I Q =.8mA, I SD < μa, MS Package LT93/LT93A A (I SW ),.2MHz/2.2MHz High Efficiency Step-Up DC/DC Converter : 2.6V to 6V, (MAX) = 34V, I Q = 4.2mA/5.5mA, I SD < μa, ThinSOT Package LT93/LT93A A (I SW ),.2MHz/2.2MHz High Efficiency Inverting DC/DC Converter : 2.6V to 6V, (MAX) = 34V, I Q = 4.2mA/5.5mA, I SD < μa, ThinSOT Package LT935 2A (I SW ), 4V,.2MHz High Efficiency Step-Up DC/DC Converter : 2.3V to 6V, (MAX) = 4V, I Q = 3mA, I SD < μa, ThinSOT Package LT944/LT944- (Dual) LT945 (Dual) LT946/LT946A Dual Output 35mA (I SW ), Constant Off-Time, High Efficiency Step-Up DC/DC Converter Dual Output Pos/Neg 35mA (I SW ), Constant Off-Time, High Efficiency Step-Up DC/DC Converter.5A (I SW ),.2MHz/2.7MHz High Efficiency Step-Up DC/DC Converter :.2V to 5V, (MAX) = 34V, I Q = 2μA, I SD < μa, MS Package :.2V to 5V, (MAX) = ±34V, I Q = 2μA, I SD < μa, MS Package : 2.6V to 6V, (MAX) = 34V, I Q = 3.2mA, I SD < μa, MS8E Package LT96.5A (I SW ),.25MHz High Efficiency Step-Up DC/DC Converter : 3V to 25V, (MAX) = 35V, I Q =.9mA, I SD < 6μA, MS8E Package LT3436 3A (I SW ), 8kHz, 34V Step-Up DC/DC Converter : 3V to 25V, (MAX) = 34V, I Q =.9mA, I SD < 6μA, TSSOP6E Package LT3467.A (I SW ),.3MHz High Efficiency Step-Up DC/DC Converter : 2.6V to 6V, (MAX) = 4V, I Q =.2mA, I SD < μa, ThinSOT, 2mm 3mm DFN Packages LT V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED Driver : 2.5V to 25V, (MAX) = 4V, Analog/PWM, I SD < μa, QFN, TSSOP2E Packages LT3479 3A Full-Featured DC/DC Converter with Soft-Start and Inrush Current Protection : 2.5V to 24V, (MAX) = 4V, Analog/PWM, I SD < μa, DFN, TSSOP Packages 28 LT 9 REV G PRINTED IN USA Linear Technology Corporation 63 McCarthy Blvd., Milpitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 27