White Paper Amy Chong Yew Ee Online Sales Account Manager APAC Online Sales Center Intel Corporation. BOM Cost Reduction by Removing S3 State

Transcription

1 White Paper Amy Chong Yew Ee Online Sales Account Manager APAC Online Sales Center Intel Corporation BOM Cost Reduction by Removing S3 State May

2 Executive Summary In today s embedded design, designers are increasingly concerned with reducing system power. When systems experience extended periods of idle time, power can be greatly reduced when a processor transits into System Sleeping Power States (S-States). With the additional S-States to support, this means additional power rails need to be supplied by the platform and incur extra components such as voltage regulator, switches, etc. In reality, there are applications that do not require extra sleep states due to performance demand and its usage environment. Having extra sleep states translates into extra components and increased BOM cost. With the understanding that Intel Atom Processor E6xx can be positioned in multiple segments, this idea of removing additional power rails can be adopted in segments such as industry control and In-Vehicle-Infotainment (IVI). This document presents an overview of system power states in the Intel Atom Processor E6xx, and shows the remaining power rails after removal of the S3 power state. The estimated BOM cost savings is also shown to highlight the benefits of removing the S3 power state. The Intel Embedded Design Center provides qualified developers with web-based access to technical resources. Access Intel Confidential design materials, step-by step guidance, application reference solutions, training, Intel s tool loaner program, and connect with an e-help desk and the embedded community. Design Fast. Design Smart. Get started today. 2

3 Contents Background... 4 Supported System Power States... 5 Implementation... 7 Platform Power Rail... 7 Power Rail Definition... 8 Result... 9 Estimated BOM Cost Saving... 9 Conclusion

4 Background Many embedded system users expect the systems to work perfectly the first time and every time. From life-saving emergency communications to missioncritical financial systems, society has become more dependent upon highavailability systems. The cost of downtime is staggering and unacceptable in many cases. IA based products in new factory automations such as robots, human interface interfaces, programmable logic controllers (PLC) and vision systems must be able to respond rapidly to development errors in production in order to minimize adverse impacts on business. Therefore, these automation systems are required to always remain in full power, and always in S0. One of the key design goals of the IVI platforms with Intel Architecture is a fast boot in the order of seconds. Typically, any resumption from Suspend/Hibernate back to active state involves restoring the previous state. In an automobile environment with multiple users of the same vehicle, it is challenging to resume from suspend, as the users might change across these transitions and one user s context could get inadvertently restored from another users context. This makes the fast boot with a fresh state on every power on a key requirement for the platform so that each user starts with a new context. In addition, long duration S3 states may drain battery power if not handled properly. Table 1 describes the overall power states in an automobile and its usage. Table 1: Intel-based IVI platform power state usage Description System CPU Usage Fully On S0 C0-C6 Ignition On Low On/User Idle S1 Thermal Management Standby/System Idle S2 Thermal Management Sleep/Suspend to RAM Hibernate/Suspend to NVM or Soft Off S3 Power Off Not Used S4/S5 Power off Not Used As shown above, removal of the unused power state S3, is the recommended solution. This will save a number of voltage regulators, which translates to a reduction in BOM costs. In addition, the reduced component also increases board real estate and gives room for critical signal routing. 4

5 Supported System Power States The ACPI specification defines sleep state as a computer hardware state that draws significantly less power than the fully operational state of the computer (defined as S0). Figure 1: Power State Transition in Intel Atom Processor E6xx The Intel Atom Processor E6xx supports the S3, S4, and S5 sleep states. S4 and S5 states are identical from a hardware perspective. The processor is returned to the S0 state from S3, S4, and S5 through wake events. S0-System Working State The S0 state is called the system working state. This is the normal operating state of the system; it is not a sleeping state. In this state, the CPU is able to fetch and execute code. The processor is free to move into various processor C-States. S3-Suspend to RAM The S3 sleeping state is called the Suspend-to-RAM (STR) state and is often called Standby. The S3 state is targeted as a low-latency, low power state. In this state all core power is shut down to the processor. Only resume power, memory controller, I/O power, and DRAM power should remain. Before entering the S3 state, the main memory is placed in self-refresh. 5

6 S4-Suspend to Disk The S4 state is commonly called Suspend to Disk, or hibernate. In this state, the operating system writes the contents of its memory to a hard disk drive (or any non-volatile storage). This allows the user to resume work from the point when Suspend to Disk was initiated. From a hardware perspective, the S4 and S5 states look identical. That is, all power rails are turned off except for the RTC well. A full boot is required to return to S0. S5-Soft Off The S5 state is the Soft Off state. In this state, all power rails are turned off in the system; only the RTC well has power. From a hardware perspective this state is identical to S4. No OS context is saved to permanent storage. A full boot is required to return to S0. 6

7 Implementation Platform Power Rail Table 2 shows the original power rails from the Little Bay Customer Reference Board (CRB) and the remaining power rails after removal of the S3 power state. The reduced VRs are a result of combining the power rail: VR for V1P05 Load switch for V3P3_S Load switch for V1P8_S Table 2: Power rail before and after S3 removal Power Rails (Original) VCC_S VNN_S V0P9_S Power Rails (After S3 Removal) VCC_S VNN_S V0P9_S V1P8 V1P8_S V1P8_S V3P3 V3P3_RTC V3P3_A V3P3_S V3P3_RTC V3P3_A V3P3_S V1P05 V1P05_S V1P5_S V1P05_S V1P5_S 7

8 Power Rail Definition Below are the power rail definitions. Core Rails (VCC_S, VNN_S) The Core supplies are an output of the Intel MVP-6 voltage regulators and supply power to the core rails of the Intel Atom Processor E6xx Series V Rail (V1P05, V1P05_S) The 1.05 V rail supplies many core parts of the Intel Atom Processor E6xx Series. It is also used for the processor signals of the ITP-XDP debug port (if used). 1.5 V Rail (V1P5_S) The Intel Atom Processor E6xx Series requires this power source (known as VCCA) to run the PLL clock generators on the silicon. DDR Rails (V1P8, V0P9) The Intel Atom Processor E6xx Series supports DDR2 memory technology, which requires 1.8 V for V1P8 and 0.9 V for V0P9 (VREF). 3.3 V Rails (V3P3, V3P3_A, V3P3_S) The 3.3 V rail is the most prolific rail on the platform. Most circuits on the platform use it, including the Intel Atom Processor E6xx Series. There are three versions of the 3.3 V rail that are generated by the voltage regulator: Main rail (V3P3), Always version (V3P3A) Sleep version (V3P3S). 5 V Rails (V5_A, V5_S) There are two versions of 5 V rails: The V5_A rail, an Always version is supplied by carrier board through COM Express* connector. This rail can be used to generate 3.3 V and DDR rails. 8

9 The Sleep version rail, V5_S is a switched rail and is enabled in S0 only. 12 V Rail (V12_S) The 12 V rail is supplied by carrier board through COM Express* connector. Most of the power rails can be derived from V12_S using an on board voltage regulator. Result Estimated BOM Cost Saving Table 3 shows the components that are not required when S3 is removed. It also shows the estimated BOM cost savings with this implementation. Table 3: Components not required when S3 is removed Component Description Price Load Switch TPS22922YZPR $0.26 Load Switch TPS22922YZPR $0.26 VR AS1371 $0.43 Total: $0.95 Cost savings is $0.95 per board 1000 boards translates to a $950 savings Power architecture is the backbone of any electronics system. As in any design implementation, verification is required to ensure the original power sequence remains intact and no bugs are introduced. We powered up the Little Bay CRB to verify the design implementation. During preliminary testing, it was booted in Windows XP SP3* and run for a period of 24 hours. Board vendors are encouraged to follow this approach to further validate this implementation. 9

10 Conclusion This white paper gives an overview of System Sleeping Power States (S- States). It provides background understanding on why extra sleep states are not required in certain applications, such as industry control and In-Vehicle- Infotainment (IVI). By removing the S3 state from the boot up sequence, developers can remove unnecessary components from the system, saving money and board real estate. Board vendors are encouraged to follow this approach. This ensures reliability before implementing the new system on their embedded system. 10

11 The Intel Embedded Design Center provides qualified developers with webbased access to technical resources. Access Intel Confidential design materials, step-by step guidance, application reference solutions, training, Intel s tool loaner program, and connect with an e-help desk and the embedded community. Design Fast. Design Smart. Get started today. Author Amy Chong Yew Ee is an Online Sales Account Manager with the APAC Online Sales Center at Intel Corporation. Acronyms S-States C-States IVI PLC ACPI RTC CRB PLL MVP-6 VR System Sleeping Power States Processor Power States In-Vehicle-Infotainment Programmable Logic Controller Advanced Configuration and Power Interface Real Time Clock Customer Reference Board Phase-locked loop Mobile Voltage Positioning-6 Voltage Regulator 11

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