Flexible VDSL2 datapath IP for SOC designs provides ready access to the VDSL2 chip market

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1 An UpZide White Paper Flexible datapath IP for SOC designs provides ready access to the chip market The fundamentals of the ITU-T G recommendation was accepted by the ITU in mid 2005 and the rush to announce ICs for this burgeoning market started even before the standard s acceptance was announced. According to some estimates, this market will be locked up by 2008 when research firm In-Stat estimates that chip shipments will reach nearly 70 million ports per year. Multiple estimates place the annual sales of chips at roughly $500 million by Early IC market entries based on existing ADSL2 and ADSL2+ designs are already on offer, but these early chips will not be the final market leaders due to a variety of limitations and incompatibilities created by the rush to bring a chip, any chip, to market. Consequently, semiconductor vendors that act now, quickly and decisively, still have time to deeply penetrate and attain leadership this market but the clock is ticking. An insatiable global appetite for bandwidth Global consumers have developed an insatiable appetite for bandwidth to access the 21 st - century s triple play of information services: High definition, digital television Digital telephony (voice over IP or VoIP) Broadband Internet data services Due to their older installed plants, the Telcos have severely lagged cable-tv service providers in their ability to deliver high-bandwidth, digital information services. They ve watched helplessly as the cable companies evolved from fully differentiated providers of analog video content to fiercely competitive, broad-based providers of high-definition digital video, broadband Internet, and finally VoIP services. This last development invaded the Telcos once-protected domain: voice traffic. VoIP services have been gobbling up large chunks of the residential voice market and cable-services providers continue to hold a 2:1 lead over Telco-based DSL services for broadband delivery. These developments have drained the Telcos revenue base.

2 Consequently, Telcos are extremely anxious to find a way to use their installed wire infrastructure to successfully compete with cable-based triple-play service delivery and they currently view as the most likely path to these new revenue streams. The need is so urgent that several Telcos and DSL providers including AT&T (former SBC) and BellSouth in the United States and BT, DT, B2, Swisscom and France Telecom in Europe and have jumped into testing and trials using early equipment. The Telcos fear of continued revenue loss to the cable-services providers supplies the motivation for rapid and widespread adoption. Existing DSL providers see clearly that their existing sub-10mbit/second services will be as attractive to consumers in 2008 as dial-up modem services are today, which is to say not at all attractive and becoming uglier by the day. The motivation for adoption is therefore both compelling and simple: higher ARPU (average revenue per user) and larger profits for the Telcos versus a financial death spiral and growing technological irrelevance. The standard enables these highly desired outcomes without the need to route optical fiber to every user. delivers symmetrical, aggregate data rates of as much as 200Mbits/sec (100Mbits/sec in both the upstream and downstream directions), which results in a savings to the Telcos of some $200 to $500 per home as estimated by Dave Burstein, editor of the online industry newsletter DSL Prime. These installation savings directly set a relatively high value on the hundreds of millions of chips embedded in CPE and CO equipment that the Telcos and DSL providers will be purchasing over the next several years. s complexity means short-term chaos The recommendation that the ITU accepted in June of 2005 is 221 pages long. According to DSL Prime s Dave Burstein, the specification is so complex that all the chip makers claiming they currently have standard compliant chips [on the market] are engaging in puffery. In their desire to rush products to market, the Telcos and DSL providers are currently ignoring or circumventing issues such as performance limitations and compatibility issues by offering services at bit rates below the full capabilities (using ADSL2+ equipment) and by buying equipment from single vendors (to sidestep compatibility problems). These incompatibilities and shortcomings will be ironed out over the next 12 to 36 months as the industry gains experience with installations and develops a growing collection of best practices. The ITU s published standard assures the eventual emergence of interoperability among the industry s chip offerings. The large size of the market ensures that multiple semiconductor vendors will be competing for the business. Two types of chips are expected to emerge:

3 - High-speed chips that operate at symmetric speeds of up to 100Mbits/sec in both the upstream and downstream directions. These chips will be limited to maximum line lengths of 350 meters (1148 feet). - Long-range chips operating at Mbits/sec, with much longer maximum line lengths of meters ( feet). The recommendation even target an operational range up to 2500 meters. chips achieve these high transmission rates by using varying amounts of signal bandwidth on the twisted-pair lines linking central offices to customer premises. Highspeed chips use up to 30 MHz of bandwidth and long-range chips can use either 12 MHz (in the US) or 17 MHz (in Europe). Line attenuation increases rapidly with line length and frequency, which causes a drop in transmission rate as line length increases. has an adaptive ability to adjust bit rate to line conditions using a DMT (discrete multi-tone) based duplex scheme called Zipper DMT, which parcels the bandwidth into a minimum of 2048 and a maximum of 4096 subcarrier bands spaced either 4 or 8 KHz apart and distributes data to be transmitted across these bands (see Figure 1). Figure 1: spectrum usage and comparison with ADSL and ADSL2+ Zipper DMT deviates from older DMT modulation schemes in that it can allocate adjacent subcarriers to the upstream or downstream direction, adapting and adjusting the upstream and downstream transmission rates to whatever the application requires through subcarrier allocation. By conforming to ADSL definitions of upstream and downstream bands, becomes interoperable with ADSL installations. The standard also defines eight different profiles to suit a variety of different applications (see Table 1 and Figure 2).

4 Profile 8a 8b 8c 8d 12a 12b 17a 30a Bandwidth (MHz) # of Tones Tone Spacing (KHz) Line Power (dbm) Table 1: Profiles Transmit Power 20.5 dbm Profile 8b 17.5 dbm 14.5 dbm A D S L A D S L 2 + Profile 8a 11.5 dbm Profile 8d Profile 8c Profile 12a, 12b Profile 17a Profile 30a Analog Bandwidth (MHz) # of Tones Figure 2: profiles versus ADSL and ADSL2+ Introduction to UpZide Labs a leader in design The preceding, very brief overview merely hints at the complexity of the ITU-T G standard. Because of the standard s complexity, it takes a substantial amount of development work and expertise to produce fully compatible, interoperable ICs based on this standard. UpZide Labs has that expertise. UpZide s mission is to develop future generations of advanced wire-line broadband communication systems. With its team of world-class DSL engineers, UpZide has extensive experience in copper network environments, advanced signal-processing and algorithm design, runtime software development, and system architecture definition.

5 UpZide is a spin-off of Telia Research AB, a subsidiary of Sweden s largest network operator Telia AB. UpZide was founded in 2001 by the key individuals who invented and developed the Zipper DMT modulation scheme, which forms the bedrock foundation of the specification. Since 1995, these individuals have developed numerous designs in a variety of implementation technologies including FPGAs, ASICs, and DSPs. Using this experience and expertise, UpZide Labs has developed an extremely flexible IP block that implements a standard-compliant transceiver datapath. This IP block is ready for integration into SOC designs. UpZide s datapath embodies all of the company s extensive VDSL technical knowledge. Significantly, this datapath incorporates multiple configurable microprocessor cores to execute the various functions required of the transceiver datapath. Consequently, UpZide s datapath core is highly programmable, which means that it can be readily adapted to changes in the evolving standard simply by changing the embedded firmware. Moreover, the same configurable processors are also used for the control plane which eliminates the need for additional third party system controller. This programmability allows UpZide s datapath to easily accommodate functional changes mandated by interoperability requirements or by regulatory changes, even when these requirements conflict among service providers in one or more countries. If needed, the embedded processors in UpZide s datapath can also run additional firmware that executes proprietary, customer-specific protocols with no increase in hardware cost beyond ROM storage for the additional customer code. Figure 3 shows a simplified, high-level block diagram of UpZide s transceiver datapath. Note that there are a number of sequential algorithmic operations to be performed on the incoming and outgoing data. RISC processor and DSP cores with fixed instruction sets are either too slow to perform these tasks at data rates or, if the conventional processors and DSPs can achieve the desired processing rates, they only do so at excessively high clock rates.

6 Figure 3: Block diagram of UpZide s firmware-programmable datapath datapath implementations that employ conventional processor cores running at high clock rates must be fabricated in more expensive SOC process technologies and they dissipate substantial amounts of power, which is a serious problem for both CPE designs where no cooling fan will be present and multiport CO chip designs, where per-port power dissipation is extremely important because of the large number of colocated ports. Many if not all of the datapath functions shown in Figure 3 are often implemented in hand-designed, manually verified RTL hardware because of these issues. However, this RTL-centric design approach sacrifices substantially all of a design s flexibility, which is essential to market success at this early stage in s adoption. Consequently, UpZide has partnered with Tensilica, Inc. and has used that company s Xtensa configurable-processor technology to implement large portions of its datapath. Tensilica s Xtensa processor cores have been used for years in a wide variety of communications SOCs developed by leading companies such as Broadcom, Cisco, Ikanos, Marvell Technology Group, and TranSwitch. Together, UpZide and Tensilica have optimized the microprocessor cores used in UpZide s datapath so that they efficiently implement the various algorithms at greatly reduced clock rates and power levels. This design approach results in substantial system-level savings because it reduces the size and cost of power supplies and cooling components. Xtensa configurable processors implement application-specific functions in extended execution units that resemble the RTL logic present in manually designed datapaths. However, the execution units in the Xtensa processors are machine generated, which means that they are correct by construction and automatically verified. These execution units are controlled by firmware running on the configurable processor. Consequently, the control algorithms can be modified easily without a silicon respin. Taken together, these advantages greatly reduce design risk and greatly enhance the datapath s design flexibility, at a gate count that is comparable to RTL design.

7 In addition, the Xtensa processor generator automatically adds extensive clock gating to the configurable processor, which further reduces dynamic power dissipation. Xtensa processor cores can contain hundreds of automatically generated, fine-grained, gatedclock regions to reduce dynamic power dissipation, a far larger number than is practical in hand-designed RTL blocks. Because Tensilica has been developing application-specific reference configurations of the Xtensa processor for several years, sets of instruction extensions for many of the functions listed in Figure 3 already existed. Table 2 lists some published statistics for these instruction extensions, taken from conference papers and Tensilica application notes. Published improvements range from 80x to 263x and were all achieved without increasing the processor s clock rate. Task Initial Cycle Count Final Cycle Count Approximate Acceleration Factor Reed-Solomon Encoder x Reed-Solomon Decoder x Trellis Decoding Butterfly x 1024-point FFT x Table 2: functions and acceleration factors achieved by processor configuration Working together, UpZide and Tensilica have achieved even greater cycle-time improvements for these and other critical algorithms. The magnitude of these performance improvements is far beyond the reach of conventional processor cores (RISC or DSP), which can only be accelerated through assembly-language coding or clock-rate increases. The resulting datapath design based on multiple Xtensa processor cores is highly programmable (for flexibility) and runs at relatively low clock rates (for low power dissipation) while still achieving performance goals. Taking one example, a crucial part of a design is the FFT / IFFT unit. A previous evaluation done at UpZide Labs, using a top-of-the line standard DSP, has shown that each transform (4K) would need approximately 370 us to execute at 200 MHz clock frequency, even with a highly optimized code. This is not feasible regarding the requirements. Using Tensilica's technology, these 4K algorithms have been implemented by UpZide Labs. Presently, each transform needs less than 80 us to execute at 200 MHz. Thus, both transforms can be executed by a single processor core, well inside the requirements. UpZide s datapath IP also makes use of the Xtensa LX processor s unique, highbandwidth, configurable-port technology to greatly accelerate inter-processor communications within the datapath IP block, which further improves performance and reduces power dissipation. These configurable ports prevent communications hot spots and bottlenecks in the datapath s design by separating high-speed data transfers from the memory-reference and instruction-fetch traffic on the processors buses.

8 Supplied as RTL UpZide s datapath is supplied as a block of pre-verified, ready-to-use RTL with tested, fully operational firmware. The datapath is fully synthesizable, so the resulting overall chip design can be fabricated using industry-standard cell libraries and nearly any semiconductor process technology offered by the world s leading IC foundries. UpZide s datapath IP can be used in both single-port CPE designs and multiport SOC designs intended for CO equipment. Extensive embedded firmware control future-proofs UpZide s datapath IP design, and your SOC. Changes made to track amendments to the standard, to follow new regulatory guidelines in varying international venues, or to adapt the datapath for special customer-specific requirements such as the addition of encryption for virtual private networks can be handled in firmware instead of requiring logic redesign. This design approach: Makes UpZide s datapath IP far more flexible and adaptable than fixedlogic datapath designs. Reduces the likelihood of an SOC silicon respin. Dramatically shortens time to market. Greatly reduces overall design risk. UpZide offers long-term support, maintenance, and upgrades for its datapath IP. The company will react swiftly to changes in standards and customization requests, made easier by the multiprocessor design approach used for the datapath IP block. You can also partner with UpZide and draw on the company s deep expertise in applications to help your SOC design team develop software and reference hardware designs for your chips. Companion analog front end UpZide has licensed a analog front end (AFE) from Xignal Technologies AG to offer as a companion to the datapath IP. Xignal s AFE provides a complete analog front end that runs at one-third the operating power of previous solutions and requires fewer external discrete components, which greatly simplifies the BOM for CO and CPE designs. The AFE includes a complete integrated hybrid and line driver and requires only a few additional external passive components to create a fully functional AFE.

9 Contact information If you re contemplating the design of an SOC for applications, contact and consult with the experts at UpZide Labs before you make any irreversible decisions about your design. UpZide Labs AB Aurorum 2 SE Luleå, Sweden Phone: Fax: info@upzide.com