PCI Express Basics Richard Solomon LSI Corporation
|
|
- Alaina Robertson
- 7 years ago
- Views:
Transcription
1 PCI Express Basics Richard Solomon LSI Corporation Copyright 2012, PCI-SIG, All Rights Reserved 1
2 Acknowledgements I would like to acknowledge the contributions of Ravi Budruk, Mindshare, Inc. PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 2
3 PCI Express Introduction PCI Express architecture is a high performance, IO interconnect for peripherals in computing/communication platforms Evolved from PCI TM and PCI-X TM architectures Yet PCI Express architecture is significantly different from its predecessors PCI and PCI-X PCI Express is a serial point-to-point interconnect between two devices Implements packet based protocol for information transfer Scalable performance based on number of signal Lanes implemented on the PCI Express interconnect PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 3
4 PCI Express Terminology PCI Express Device A Signal Link Wire Lane PCI Express Device B PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 4
5 PCI Express Throughput Link Width x1 x2 x4 x8 x12 x16 x32 PCIe 1.x BW (GB/s) PCIe 2.x BW (GB/s) PCIe 3.0 BW (GB/s) Derivation of these numbers: 2.5 GT/s (PCIe 1.x), 5.0 GT/s (PCIe 2.x), or 8GT/s (PCIe 3.0) signaling in each direction 20% overhead due to 8b/10b encoding in 1.x and 2.x Aggregate bandwidth, implying traffic in both directions PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 5
6 PCI Express Features Point-to-point connection Serial bus means fewer pins Scalable: x1, x2, x4, x8, x12, x16, x32 Dual Simplex connection 2.5, 5.0 and 8.0 GT/s transfer/direction/s Packet based transaction protocol PCIe Device A Packet Link (x1, x2, x4, x8, x12, x16 or x32) Packet PCIe Device B PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 6
7 Differential Signaling Electrical characteristics of PCI Express signal Differential signaling Transmitter Differential Peak voltage = V Transmitter Common mode voltage = V D- V cm V Diffp D+ Two devices at opposite ends of a Link may support different DC common mode voltages PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 7
8 Additional Features Switches used to interconnect multiple devices Packet based protocol Bandwidth and clocking Same memory, IO and configuration address space as PCI Similar transaction types as PCI with additional message transaction PCI Express Transactions include: memory read/write, memory read lock, IO read/write, configuration read/write, message requests Split transaction model for non-posted PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 8
9 Additional Features Data Integrity and Error Handling RAS capable (Reliable, Available, Serviceable) Data integrity at: 1) Link level, 2) end-to-end Virtual channels (VCs) and traffic classes (TCs) to support differentiated traffic or Quality of Service (QoS) The ability to define levels of performance for packets of different TCs 8 TC s and 8 VC s available PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 9
10 Additional Features Flow Control No retry as in PCI MSI style interrupt handling Also supports legacy PCI interrupt handling in-band Advanced power management Active State PM PCI compatible PM PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 10
11 Additional Features Hot Plug and Hot Swap support Native No sideband signals PCI compatible software model PCI configuration and enumeration software can be used to enumerate PCI Express hardware PCI Express system will boot existing OS PCI Express supports existing device drivers New additional configuration address space requires OS and driver update PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 11
12 PCI Express Topology CPU Root Complex Bus 0 (Internal) Memory PCIe 1 PCIe 6 PCIe 7 PCIe Endpoint PCIe 3 PCIe Endpoint Switch PCIe 4 PCIe 5 Legacy Endpoint PCIe Endpoint PCIe Bridge To PCI/PCI - X PCI/PCI - X Bus 8 Switch Virtual PCI Bridge Virtual PCI Bridge Virtual PCI Bridge Bus 2 Virtual PCI Bridge Legend PCI Express Device Downstream Port PCI Express Device Upstream Port PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 12
13 PCI Express System Processor PCI Express GFX GFX FSB Root Complex DDR SDRAM HDD Serial ATA PCI Express PCI Slots USB 2.0 LPC IO Controller Hub (ICH) IEEE 1394 S IO Slot COM1 COM2 GB Ethernet Add-In Add-In Add-In PCI Express Link PCI Express PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 13
14 Transaction Types, Address Spaces Request are translated to one of four transaction types by the Transaction Layer: 1. Memory Read or Memory Write. Used to transfer data from or to a memory mapped location The protocol also supports a locked memory read transaction variant. 2. I/O Read or I/O Write. Used to transfer data from or to an I/O location These transactions are restricted to supporting legacy endpoint devices. 3. Configuration Read or Configuration Write. Used to discover device capabilities, program features, and check status in the 4KB PCI Express configuration space. 4. Messages. Handled like posted writes. Used for event signaling and general purpose messaging. PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 14
15 PCI Express TLP Types Memory Read Request Description Abbreviated Name MRd Memory Read Request Locked Access Memory Write Request IO Read Request IO Write Request Configuration Read Request Type 0 and Type 1 Configuration Write Request Type 0 and Type 1 Message Request without Data Payload Message Request with Data Payload Completion without Data (used for IO, configuration write completions and read completion with error completion status) Completion with Data (used for memory, IO and configuration read completions) Completion for Locked Memory Read without Data (used for error status) Completion for Locked Memory Read with Data MRdLk MWr IORd IOWr CfgRd0, CfgRd1 CfgWr0, CfgWr1 Msg MsgD Cpl CplD CplLk CplDLk PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 15
16 Three Methods For Packet Routing Each request or completion header is tagged as to its type, and each of the packet types is routed based on one of three schemes: Address Routing ID Routing Implicit Routing Memory and IO requests use address routing. Completions and Configuration cycles use ID routing. Message requests have selectable routing based on a 3-bit code in the message routing sub-field of the header type field. PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 16
17 Programmed I/O Transaction Processor Processor Requester: -Step 1: Root Complex (requester) initiates Memory Read Request (MRd) -Step 4: Root Complex receives CplD MRd MRd Root Complex CplD FSB DDR SDRAM MRd Switch A CplD Switch C Switch B Endpoint Endpoint Endpoint Endpoint MRd Endpoint CplD Completer: -Step 2: Endpoint (completer) receives MRd -Step 3: Endpoint returns Completion with data (CplD) PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 17
18 DMA Transaction Processor Processor Completer: -Step 2: Root Complex (completer) receives MRd -Step 3: Root Complex returns Completion with data (CplD) CplD Root Complex MRd FSB DDR SDRAM CplD Switch A MRd Switch C Switch B Endpoint Endpoint Endpoint Endpoint CplD Endpoint MRd Requester: -Step 1: Endpoint (requester) initiates Memory Read Request (MRd) -Step 4: Endpoint receives CplD PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 18
19 Peer-to-Peer Transaction Processor Processor FSB CplD Root Complex MRd MRd CplD DDR SDRAM CplD Switch A Switch C MRd MRd CplD Switch B Endpoint Endpoint Endpoint Completer: -Step 2: Endpoint (completer) receives MRd CplD MRd -Step 3: Endpoint returns Endpoint Endpoint Completion with data (CplD) Requester: -Step 1: Endpoint (requester) initiates Memory Read Request (MRd) -Step 4: Endpoint receives CplD PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 19
20 PCI Express Device Layers PCI Express Device A Device Core PCI Express Device B Device Core PCI Express Core Logic Interface TX RX Transaction Layer PCI Express Core Logic Interface TX RX Transaction Layer Data Link Layer Data Link Layer Physical Layer Physical Layer Link PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 20
21 TLP Origin and Destination PCI Express Device A PCI Express Device B Device Core Device Core PCI Express Core PCI Express Core Logic Interface Logic Interface TX RX TX RX TLP Transmitted Transaction Layer Data Link Layer Transaction Layer Data Link Layer TLP Received Physical Layer Physical Layer Link PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 21
22 TLP Structure Information in core section of TLP comes from Software Layer / Device Core Bit transmit direction Start Sequence Header Data Payload ECRC LCRC End 1B 2B 3-4 DW DW 1DW 1DW 1B Created by Transaction Layer Appended by Data Link Layer Appended by Physical Layer *Slightly different at 8GT/s* PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 22
23 DLLP Origin and Destination PCI Express Device A PCI Express Device B Device Core Device Core PCI Express Core PCI Express Core Logic Interface Logic Interface TX RX TX RX Transaction Layer Transaction Layer DLLP Transmitted Data Link Layer Data Link Layer DLLP Received Physical Layer Physical Layer Link PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 23
24 DLLP Structure Bit transmit direction Start DLLP CRC End 1B 4B 2B 1B Data Link Layer Appended by Physical Layer *Slightly different at 8GT/s* ACK / NAK Packets Flow Control Packets Power Management Packets Vendor Defined Packets PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 24
25 Ordered-Set Origin and Destination PCI Express Device A PCI Express Device B Device Core Device Core PCI Express Core PCI Express Core Logic Interface Logic Interface TX RX TX RX Transaction Layer Transaction Layer Data Link Layer Data Link Layer Ordered-Set Transmitted Physical Layer Physical Layer Ordered-Set Received Link PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 25
26 Ordered-Set Structure in 2.5GT/s and 5GT/s modes COM Identifier Identifier Identifier Training Sequence One (TS1) 16 character set: 1 COM, 15 TS1 data characters Training Sequence Two (TS2) 16 character set: 1 COM, 15 TS2 data characters SKIP 4 character set: 1 COM followed by 3 SKP identifiers Fast Training Sequence (FTS) 4 characters: 1 COM followed by 3 FTS identifiers Electrical Idle (IDLE) 4 characters: 1 COM followed by 3 IDL identifiers Electrical Idle Exit (EIEOS) (new to 2.0 spec) 16 characters PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 26
27 Quality of Service Processor Processor PCI Express GFX GFX Endpoint Root Complex DDR SDRAM InfiniBand Switch Out-of-Box InfiniBand Endpoint Add-In Switch Switch 10Gb Ethernet Endpoint 10Gb Ethernet Endpoint Switch PCI Express to-pci Endpoint SCSI Endpoint Fiber Channel RAID Disk array Slot PCI PCI Express Link Video Camera SCSI Endpoint COM1 COM2 S IO IEEE 1394 Slots PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 27
28 PCI Express Flow Control Credit-based flow control is point-to-point based, not end-to-end TLP Buffer space available VC Buffer Transmitter Receiver Flow Control DLLP (FCx) Receiver sends Flow Control Packets (FCP) which are a type of DLLP (Data Link Layer Packet) to provide the transmitter with credits so that it can transmit packets to the receiver PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 28
29 ACK/NAK Protocol Overview Transmit Device A Receiver Device B From Transaction Layer Tx TLP Sequence TLP LCRC Data Link Layer DLLP ACK / NAK DLLP ACK / NAK To Transaction Layer Rx Data Link Layer TLP Sequence TLP LCRC Replay Buffer De-mux De-mux Mux Mux Error Check Tx Rx Tx Rx DLLP ACK / NAK Link TLP Sequence TLP LCRC PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 29
30 ACK/NAK Protocol: Point-to-Point 1a. Request 2a. Request 4b. ACK 3b. ACK Requester Switch 1b. ACK 2b. ACK 4a. Completion 3a. Completion Completer ACK returned for good reception of Request or Completion NAK returned for error reception of Request or Completion PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 30
31 Interrupt Model: Three Methods PCI Express supports three interrupt reporting mechanisms: 1. Message Signaled Interrupts (MSI) Legacy endpoints are required to support MSI (or MSI-X) with 32- or 64-bit MSI capability register implementation Native PCI Express endpoints are required to support MSI with 64-bit MSI capability register implementation 2. Message Signaled Interrupts - X (MSI-X) Legacy and native endpoints are required to support MSI-X (or MSI) and implement the associated MSI-X capability register 3. INTx Emulation. Native and Legacy endpoints are required to support Legacy INTx Emulation PCI Express defines in-band messages which emulate the four physical interrupt signals (INTA-INTD) routed between PCI devices and the system interrupt controller Forwarding support required by switches PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 31
32 Native and Legacy Interrupts x PCIe - PCIe PCIe PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 32
33 PCI Express Configuration Space PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 33
34 Thank you for attending the PCI-SIG Developers Conference 2012 For more information please go to PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 34
PCI Express Basics Ravi Budruk Senior Staff Engineer and Partner MindShare, Inc.
PCI Express Basics Ravi Budruk Senior Staff Engineer and Partner MindShare, Inc. Copyright 2007, PCI-SIG, All Rights Reserved 1 PCI Express Introduction PCI Express architecture is a high performance,
More information3 Address Spaces & Transaction Routing. The Previous Chapter. This Chapter. The Next Chapter
PCIEX.book Page 105 Tuesday, August 5, 2003 4:22 PM 3 Address Spaces & Transaction Routing The Previous Chapter The previous chapter introduced the PCI Express data transfer protocol. It described the
More informationPCI Express Overview. And, by the way, they need to do it in less time.
PCI Express Overview Introduction This paper is intended to introduce design engineers, system architects and business managers to the PCI Express protocol and how this interconnect technology fits into
More informationAn Introduction to PCI Express
by Ravi Budruk Abstract The Peripheral Component Interconnect - Express (PCI Express) architecture is a thirdgeneration, high-performance I/O bus used to interconnect peripheral devices in applications
More informationPCI Express Gen 2 Deep Dive on Power Architecture Based Products
June, 2010 PCI Express Gen 2 Deep Dive on Power Architecture Based Products FTF-NET-F0685 Richard Nie Sr. Systems and Application Engineer, NMG, NSD and VortiQa are trademarks of Freescale Semiconductor,
More informationPCI Express IO Virtualization Overview
Ron Emerick, Oracle Corporation Author: Ron Emerick, Oracle Corporation SNIA Legal Notice The material contained in this tutorial is copyrighted by the SNIA unless otherwise noted. Member companies and
More informationPCI Express Impact on Storage Architectures and Future Data Centers. Ron Emerick, Oracle Corporation
PCI Express Impact on Storage Architectures and Future Data Centers Ron Emerick, Oracle Corporation SNIA Legal Notice The material contained in this tutorial is copyrighted by the SNIA. Member companies
More informationPCI Express Impact on Storage Architectures. Ron Emerick, Sun Microsystems
PCI Express Impact on Storage Architectures Ron Emerick, Sun Microsystems SNIA Legal Notice The material contained in this tutorial is copyrighted by the SNIA. Member companies and individual members may
More informationMSC8156 and MSC8157 PCI Express Performance
Freescale Semiconductor Application Note Document Number: AN3935 Rev. 1, 11/2011 MSC8156 and MSC8157 PCI Express Performance This application note presents performance measurements of the MSC8156 and MSC8157
More informationPCI Express Base Specification Revision 1.0
PCI Express Base Specification Revision 1.0 April 29, 2002 REVISION REVISION HISTORY DATE 1.0 Initial release. 4/29/02 PCI-SIG disclaims all warranties and liability for the use of this document and the
More informationAppendix A. by Gordon Getty, Agilent Technologies
Appendix A Test, Debug and Verification of PCI Express Designs by Gordon Getty, Agilent Technologies Scope The need for greater I/O bandwidth in the computer industry has caused designers to shift from
More informationPCI Express and Storage. Ron Emerick, Sun Microsystems
Ron Emerick, Sun Microsystems SNIA Legal Notice The material contained in this tutorial is copyrighted by the SNIA. Member companies and individuals may use this material in presentations and literature
More informationPCI Express Impact on Storage Architectures and Future Data Centers
PCI Express Impact on Storage Architectures and Future Data Centers Ron Emerick, Oracle Corporation Author: Ron Emerick, Oracle Corporation SNIA Legal Notice The material contained in this tutorial is
More information2. THE PCI EXPRESS BUS
1 2. THE PCI EXPRESS BUS This laboratory work presents the serial variant of the PCI bus, referred to as PCI Express. After an overview of the PCI Express bus, details about its architecture are presented,
More informationHow to build a high speed PCI Express bus expansion system using the Max Express product family 1
Applications The Anatomy of Max Express Cable Expansion How to build a high speed PCI Express bus expansion system using the Max Express product family 1 By: Jim Ison Product Marketing Manager One Stop
More informationEDUCATION. PCI Express, InfiniBand and Storage Ron Emerick, Sun Microsystems Paul Millard, Xyratex Corporation
PCI Express, InfiniBand and Storage Ron Emerick, Sun Microsystems Paul Millard, Xyratex Corporation SNIA Legal Notice The material contained in this tutorial is copyrighted by the SNIA. Member companies
More informationHardware Level IO Benchmarking of PCI Express*
White Paper James Coleman Performance Engineer Perry Taylor Performance Engineer Intel Corporation Hardware Level IO Benchmarking of PCI Express* December, 2008 321071 Executive Summary Understanding the
More informationPCI Express Impact on Storage Architectures and Future Data Centers. Ron Emerick, Oracle Corporation
PCI Express Impact on Storage Architectures and Future Data Centers Ron Emerick, Oracle Corporation SNIA Legal Notice The material contained in this tutorial is copyrighted by the SNIA. Member companies
More informationPEX 8748, PCI Express Gen 3 Switch, 48 Lanes, 12 Ports
, PCI Express Gen 3 Switch, 48 Lanes, 12 Ports Highlights General Features o 48-lane, 12-port PCIe Gen 3 switch - Integrate d 8.0 GT/s SerDes o 27 x 27mm 2, 676-pin BGA package o Typical Power: 8.0 Watts
More informationStorage Architectures. Ron Emerick, Oracle Corporation
PCI Express PRESENTATION and Its TITLE Interfaces GOES HERE to Flash Storage Architectures Ron Emerick, Oracle Corporation SNIA Legal Notice The material contained in this tutorial is copyrighted by the
More informationCreating a PCI Express Interconnect AJAY V. BHATT, TECHNOLOGY AND RESEARCH LABS, INTEL CORPORATION
White Paper Creating a Interconnect AJAY V. BHATT, TECHNOLOGY AND RESEARCH LABS, INTEL CORPORATION SUMMARY This paper looks at the success of the widely adopted bus and describes a higher performance Express
More informationPCI Express* Ethernet Networking
White Paper Intel PRO Network Adapters Network Performance Network Connectivity Express* Ethernet Networking Express*, a new third-generation input/output (I/O) standard, allows enhanced Ethernet network
More informationPCI EXPRESS TECHNOLOGY. Jim Brewer, Dell Business and Technology Development Joe Sekel, Dell Server Architecture and Technology
WHITE PAPER February 2004 PCI EXPRESS TECHNOLOGY Jim Brewer, Dell Business and Technology Development Joe Sekel, Dell Server Architecture and Technology Formerly known as 3GIO, PCI Express is the open
More informationUnderstanding PCI Bus, PCI-Express and In finiband Architecture
White Paper Understanding PCI Bus, PCI-Express and In finiband Architecture 1.0 Overview There is some confusion in the market place concerning the replacement of the PCI Bus (Peripheral Components Interface)
More informationPCI Express: Interconnect of the future
PCI Express: Interconnect of the future There are many recent technologies that have signalled a shift in the way data is sent within a desktop computer in order to increase speed and efficiency. Universal
More informationIntroduction to PCI Express Positioning Information
Introduction to PCI Express Positioning Information Main PCI Express is the latest development in PCI to support adapters and devices. The technology is aimed at multiple market segments, meaning that
More informationComputer Systems Structure Input/Output
Computer Systems Structure Input/Output Peripherals Computer Central Processing Unit Main Memory Computer Systems Interconnection Communication lines Input Output Ward 1 Ward 2 Examples of I/O Devices
More informationIntel PCI and PCI Express*
Intel PCI and PCI Express* PCI Express* keeps in step with an evolving industry The technology vision for PCI and PCI Express* From the first Peripheral Component Interconnect (PCI) specification through
More informationPCI Express High Performance Reference Design
2015.10.13 AN-456-2.4 Subscribe The PCI Express High-Performance Reference Design highlights the performance of the Altera s PCI Express products. The design includes a high-performance chaining direct
More informationThe Bus (PCI and PCI-Express)
4 Jan, 2008 The Bus (PCI and PCI-Express) The CPU, memory, disks, and all the other devices in a computer have to be able to communicate and exchange data. The technology that connects them is called the
More informationChapter 6. 6.1 Introduction. Storage and Other I/O Topics. p. 570( 頁 585) Fig. 6.1. I/O devices can be characterized by. I/O bus connections
Chapter 6 Storage and Other I/O Topics 6.1 Introduction I/O devices can be characterized by Behavior: input, output, storage Partner: human or machine Data rate: bytes/sec, transfers/sec I/O bus connections
More informationSerial ATA technology
Serial ATA technology Technology brief, 4 th edition Introduction... 2 SATA devices and interoperability with SAS devices... 2 Initiators... 2 Expanders... 3 Targets and their recommended uses... 3 Entry
More informationThe changes in each specification and how they compare is shown in the table below. Following the table is a discussion of each of these changes.
Introduction There are many interconnect technologies connect components in a system and an embedded designer is faced with an array of standards and technologies choose from. This paper explores the latest
More informationProject 4: Pseudo USB Simulation Introduction to UNIVERSAL SERIAL BUS (USB) STANDARD
Project 4: Pseudo USB Simulation Introduction to UNIVERSAL SERIAL BUS (USB) STANDARD The Universal Serial Bus is a fast, bi-directional, low cost, dynamically attachable serial interface. The motivation
More informationHot and Surprise Plug Recommendations for Enterprise PCIe Switches in the Data Center (Short Form)
. White Paper Hot and Surprise Plug Recommendations for Enterprise PCIe Switches in the Data Center (Short Form) Preliminary May, 2016 Abstract This short form white paper describes the software and hardware
More informationPCI EXPRESS: AN OVERVIEW OF PCI EXPRESS, CABLED PCI EXPRESS, AND PXI EXPRESS
10th ICALEPCS Int. Conf. on Accelerator & Large Expt. Physics Control Systems. Geneva, 10-14 Oct 2005, WE1.1-4I (2005) PCI EXPRESS: AN OVERVIEW OF PCI EXPRESS, CABLED PCI EXPRESS, AND PXI EXPRESS T. Fountain,
More informationUsing PCI Express Technology in High-Performance Computing Clusters
Using Technology in High-Performance Computing Clusters Peripheral Component Interconnect (PCI) Express is a scalable, standards-based, high-bandwidth I/O interconnect technology. Dell HPC clusters use
More informationHow PCI Express Works (by Tracy V. Wilson)
1 How PCI Express Works (by Tracy V. Wilson) http://computer.howstuffworks.com/pci-express.htm Peripheral Component Interconnect (PCI) slots are such an integral part of a computer's architecture that
More informationArria 10 Avalon-MM DMA Interface for PCIe Solutions
Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.0 UG-01145_avmm_dma 101 Innovation Drive San Jose, CA 95134 www.altera.com Datasheet
More informationThe proliferation of the raw processing
TECHNOLOGY CONNECTED Advances with System Area Network Speeds Data Transfer between Servers with A new network switch technology is targeted to answer the phenomenal demands on intercommunication transfer
More informationIntroduction to USB 3.0
By Donovan (Don) Anderson, Vice President, MindShare, Inc. This paper is a brief review of the USB 3.0 implementation, focusing on USB 2.0 backward compatibility and on the major features associated with
More informationPCI Express to 6Gb/s Serial Attached SCSI (SAS) Host Bus Adapters. User Guide
PCI Express to 6Gb/s Serial Attached SCSI (SAS) Host Bus Adapters User Guide September 2010 Revision History Version and Date September 2010 April 2010 March 2010 October 2009 July 2009 Description of
More informationSerial ATA and Serial Attached SCSI technologies
Serial ATA and Serial Attached SCSI technologies technology brief Abstract... 2 Introduction... 2 Serial architecture: the future of HDD technologies... 2 Parallel ATA technology... 2 Parallel SCSI...
More informationFibre Channel over Ethernet in the Data Center: An Introduction
Fibre Channel over Ethernet in the Data Center: An Introduction Introduction Fibre Channel over Ethernet (FCoE) is a newly proposed standard that is being developed by INCITS T11. The FCoE protocol specification
More informationBig Picture. IC220 Set #11: Storage and I/O I/O. Outline. Important but neglected
Big Picture Processor Interrupts IC220 Set #11: Storage and Cache Memory- bus Main memory 1 Graphics output Network 2 Outline Important but neglected The difficulties in assessing and designing systems
More informationIDE/ATA Interface. Objectives. IDE Interface. IDE Interface
Objectives IDE/ATA Interface In this part, you will -Learn about each of the ATA standards -Identify the ATA connector and cable -Learn how to set jumpers for master, slave and cable select configurations
More informationUsing FPGAs to Design Gigabit Serial Backplanes. April 17, 2002
Using FPGAs to Design Gigabit Serial Backplanes April 17, 2002 Outline System Design Trends Serial Backplanes Architectures Building Serial Backplanes with FPGAs A1-2 Key System Design Trends Need for.
More informationNVM Express TM Infrastructure - Exploring Data Center PCIe Topologies
Architected for Performance NVM Express TM Infrastructure - Exploring Data Center PCIe Topologies January 29, 2015 Jonmichael Hands Product Marketing Manager, Intel Non-Volatile Memory Solutions Group
More informationTechnology Note. PCI Express
Technology Note www.euresys.com info@euresys.com Copyright 2006 Euresys s.a. Belgium. Euresys is registred trademarks of Euresys s.a. Belgium. Other product and company names listed are trademarks or trade
More informationMaximizing Server Storage Performance with PCI Express and Serial Attached SCSI. Article for InfoStor November 2003 Paul Griffith Adaptec, Inc.
Filename: SAS - PCI Express Bandwidth - Infostor v5.doc Maximizing Server Storage Performance with PCI Express and Serial Attached SCSI Article for InfoStor November 2003 Paul Griffith Adaptec, Inc. Server
More informationChapter 13 Selected Storage Systems and Interface
Chapter 13 Selected Storage Systems and Interface Chapter 13 Objectives Appreciate the role of enterprise storage as a distinct architectural entity. Expand upon basic I/O concepts to include storage protocols.
More informationARM Ltd 110 Fulbourn Road, Cambridge, CB1 9NJ, UK. *peter.harrod@arm.com
Serial Wire Debug and the CoreSight TM Debug and Trace Architecture Eddie Ashfield, Ian Field, Peter Harrod *, Sean Houlihane, William Orme and Sheldon Woodhouse ARM Ltd 110 Fulbourn Road, Cambridge, CB1
More informationSuccessfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance
Successfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance Page 1 Agenda Introduction PCIe 2.0 changes from 1.0a/1.1 Spec 5GT/s Challenges Error Correction Techniques Test tool
More informationComputer Organization & Architecture Lecture #19
Computer Organization & Architecture Lecture #19 Input/Output The computer system s I/O architecture is its interface to the outside world. This architecture is designed to provide a systematic means of
More informationAn Analysis of Wireless Device Implementations on Universal Serial Bus
An Analysis of Wireless Device Implementations on Universal Serial Bus 6/3/97 Abstract Universal Serial Bus (USB) is a new personal computer (PC) interconnect that can support simultaneous attachment of
More informationErrata for the PCI Express Base Specification Revision 3.0
Errata for the PCI Express Base Specification Revision 3.0 October 23, 2014 PCIe_Base_r3_0_Errata_2014-10-23_clean.docx REVISION REVISION HISTORY DATE 1.0 Initial release of errata: A1-A12 and B1-B6. 10/20/2011
More informationComputer buses and interfaces
FYS3240 PC-based instrumentation and microcontrollers Computer buses and interfaces Spring 2011 Lecture #5 Bekkeng 15.1.2011 The most common data acquisition buses available today Internal computer buses
More informationPCI Express: The Evolution to 8.0 GT/s. Navraj Nandra, Director of Marketing Mixed-Signal and Analog IP, Synopsys
PCI Express: The Evolution to 8.0 GT/s Navraj Nandra, Director of Marketing Mixed-Signal and Analog IP, Synopsys PCIe Enterprise Computing Market Transition From Gen2 to Gen3 Total PCIe instances. 2009
More informationHigh Speed I/O Server Computing with InfiniBand
High Speed I/O Server Computing with InfiniBand José Luís Gonçalves Dep. Informática, Universidade do Minho 4710-057 Braga, Portugal zeluis@ipb.pt Abstract: High-speed server computing heavily relies on
More informationPCI-SIG SR-IOV Primer. An Introduction to SR-IOV Technology Intel LAN Access Division
PCI-SIG SR-IOV Primer An Introduction to SR-IOV Technology Intel LAN Access Division 321211-002 Revision 2.5 Legal NFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE,
More informationTransitioning to 6Gb/s SAS (Serial-Attached SCSI) A Dell White Paper
Transitioning to 6Gb/s SAS (Serial-Attached SCSI) A Dell White Paper December 2009 THIS WHITE PAPER IS FOR INFORMATIONAL PURPOSES ONLY, AND MAY CONTAIN TYPOGRAPHICAL ERRORS AND TECHNICAL INACCURACIES.
More informationPCIe Over Cable Provides Greater Performance for Less Cost for High Performance Computing (HPC) Clusters. from One Stop Systems (OSS)
PCIe Over Cable Provides Greater Performance for Less Cost for High Performance Computing (HPC) Clusters from One Stop Systems (OSS) PCIe Over Cable PCIe provides greater performance 8 7 6 5 GBytes/s 4
More informationAre your company s technical training needs being addressed in the most effective manner?
world-class technical training Are your company s technical training needs being addressed in the most effective manner? MindShare has over 25 years experience in conducting technical training on cutting-edge
More informationIntroduction to Infiniband. Hussein N. Harake, Performance U! Winter School
Introduction to Infiniband Hussein N. Harake, Performance U! Winter School Agenda Definition of Infiniband Features Hardware Facts Layers OFED Stack OpenSM Tools and Utilities Topologies Infiniband Roadmap
More informationTCIS007. PCI Express* 3.0 Technology: PHY Implementation Considerations for Intel Platforms
SF 2009 PCI Express* 3.0 Technology: PHY Implementation Considerations for Intel Platforms Debendra Das Sharma Principal Engineer Digital Enterprise Group Intel Corporation TCIS007 Agenda Problem Statement
More informationBuilding High-Performance iscsi SAN Configurations. An Alacritech and McDATA Technical Note
Building High-Performance iscsi SAN Configurations An Alacritech and McDATA Technical Note Building High-Performance iscsi SAN Configurations An Alacritech and McDATA Technical Note Internet SCSI (iscsi)
More informationIntel Ethernet Switch Load Balancing System Design Using Advanced Features in Intel Ethernet Switch Family
Intel Ethernet Switch Load Balancing System Design Using Advanced Features in Intel Ethernet Switch Family White Paper June, 2008 Legal INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
More informationWireshark in a Multi-Core Environment Using Hardware Acceleration Presenter: Pete Sanders, Napatech Inc. Sharkfest 2009 Stanford University
Wireshark in a Multi-Core Environment Using Hardware Acceleration Presenter: Pete Sanders, Napatech Inc. Sharkfest 2009 Stanford University Napatech - Sharkfest 2009 1 Presentation Overview About Napatech
More informationIntel architecture. Platform Basics. White Paper Todd Langley Systems Engineer/ Architect Intel Corporation. September 2010
White Paper Todd Langley Systems Engineer/ Architect Intel Corporation Intel architecture Platform Basics September 2010 324377 Executive Summary Creating an Intel architecture design encompasses some
More informationChapter 5 Cubix XP4 Blade Server
Chapter 5 Cubix XP4 Blade Server Introduction Cubix designed the XP4 Blade Server to fit inside a BladeStation enclosure. The Blade Server features one or two Intel Pentium 4 Xeon processors, the Intel
More informationOpenSPARC T1 Processor
OpenSPARC T1 Processor The OpenSPARC T1 processor is the first chip multiprocessor that fully implements the Sun Throughput Computing Initiative. Each of the eight SPARC processor cores has full hardware
More informationRapidIO Technology and PCI Express TM A Comparison
White Paper RapidIO Technology and PCI Express TM A Comparison The embedded system engineer, faced with development of a next generation system, has a desire to increase performance, improve efficiency,
More informationPCIeBPMC (PCI/PCI-X Bus Compatible) Bridge based PCIe and PMC Compatible Adapter Carrier Front View shown with 1 installed fans model # PCIeBPMC-FAN2
DE Store Home Company Search Design MadeInUSA White Papers PCIeBPMC PCIe [Express] to PMC Adapter / Carrier Shown with optional "Zero Slot Fans" in both positions. Fans available in either, both, or neither
More informationUMBC. ISA is the oldest of all these and today s computers still have a ISA bus interface. in form of an ISA slot (connection) on the main board.
Bus Interfaces Different types of buses: ISA (Industry Standard Architecture) EISA (Extended ISA) VESA (Video Electronics Standards Association, VL Bus) PCI (Periheral Component Interconnect) USB (Universal
More information85MIV2 / 85MIV2-L -- Components Locations
Chapter Specification 85MIV2 / 85MIV2-L -- Components Locations RJ45 LAN Connector for 85MIV2-L only PS/2 Peripheral Mouse (on top) Power PS/2 K/B(underside) RJ45 (on top) +2V Power USB0 (middle) USB(underside)
More informationPericom PCI Express 1.0 & PCI Express 2.0 Advanced Clock Solutions
Pericom PCI Express 1.0 & PCI Express 2.0 Advanced Clock Solutions PCI Express Bus In Today s Market PCI Express, or PCIe, is a relatively new serial pointto-point bus in PCs. It was introduced as an AGP
More informationOverview of Routing between Virtual LANs
Overview of Routing between Virtual LANs This chapter provides an overview of virtual LANs (VLANs). It describes the encapsulation protocols used for routing between VLANs and provides some basic information
More informationUsing Multipathing Technology to Achieve a High Availability Solution
Using Multipathing Technology to Achieve a High Availability Solution Table of Contents Introduction...3 Multipathing Technology...3 Multipathing I/O Implementations...5 Storage Redundancy...5 Infortrend
More informationLocal Area Networks transmission system private speedy and secure kilometres shared transmission medium hardware & software
Local Area What s a LAN? A transmission system, usually private owned, very speedy and secure, covering a geographical area in the range of kilometres, comprising a shared transmission medium and a set
More information12K Support Training 2001, Cisc 200 o S 1, Cisc 2, Cisc y tems, Inc. tems, In A l rights reserv s rese ed.
12K Support Training 2002, 2001, Cisco Systems, Inc. All rights reserved. 1 Agenda 12K Product Overview System Architecture Forwarding Architecture Services and Applications Troubleshooting 2001, 2002,
More informationKnut Omang Ifi/Oracle 19 Oct, 2015
Software and hardware support for Network Virtualization Knut Omang Ifi/Oracle 19 Oct, 2015 Motivation Goal: Introduction to challenges in providing fast networking to virtual machines Prerequisites: What
More informationPCI Express Technology
PCI Express Technology PCI Comprehensive Guide to Generations 1.x, 2.x and 3.0 EXPRESS TRAINING AT MindShare books are critical in the understanding of complex technical topics, such as PCI Express 3.0
More informationIntel Server Board S5000PALR Intel Server System SR1500ALR
Server WHQL Testing Services Enterprise Platforms and Services Division Intel Server Board S5000PALR Intel Server System SR1500ALR Intel Server System SR2500ALBRPR Server Test Submission (STS) Report For
More informationPCI Technology Overview
PCI Technology Overview February 2003 February 2003 Page 1 Agenda History and Industry Involvement Technology Information Conventional PCI PCI-X 1.0 2.0 PCI Express Other Digi Products in PCI/PCI-X environments
More informationIntroduction to PCI Express
Introduction to PCI Express A Hardware and Software Developer s Guide Adam H. Wilen Justin P. Schade Ron Thornburg Copyright 2003 Intel Corporation. All rights reserved. ISBN 0-9702846-9-1 No part of this
More informationPhoenix SecureCore TM Setup Utility
Phoenix SecureCore TM Setup Utility Important information: We continually strive to bring you the latest and proven features and technologies. As part of our drive to continually improve our products modifications
More informationPCI Express 2.0 SATA III RAID Controller Card with Internal Mini-SAS SFF-8087 Connector
PCI Express 2.0 SATA III RAID Controller Card with Internal Mini-SAS SFF-8087 Connector StarTech ID: PEXSAT34SFF The PEXSAT34SFF PCI Express SATA Controller Card enables 4 AHCI SATA III connections to
More informationSiS AMD Athlon TM 64FX/PCI-E Solution. Silicon Integrated Systems Corp. Integrated Product Division April. 2004
SiS AMD Athlon TM 64FX/PCI-E Solution Silicon Integrated Systems Corp. Integrated Product Division April. 2004 Agenda SiS AMD Athlon 64/ 64FX Product Roadmap SiS756 Architecture Advanced Feature of SiS756
More informationPCI Express Basic Info *This info also applies to Laptops
PCI Express Basic Info *This info also applies to Laptops PCI Express Laptops PCI Express Motherboards PCI Express Video Cards PCI Express CPU Motherboard Combo's PCI Express Barebone Systems PCI Express
More informationUniversal Flash Storage: Mobilize Your Data
White Paper Universal Flash Storage: Mobilize Your Data Executive Summary The explosive growth in portable devices over the past decade continues to challenge manufacturers wishing to add memory to their
More informationUniversal Serial Bus Implementers Forum EHCI and xhci High-speed Electrical Test Tool Setup Instruction
Universal Serial Bus Implementers Forum EHCI and xhci High-speed Electrical Test Tool Setup Instruction Revision 0.41 December 9, 2011 1 Revision History Rev Date Author(s) Comments 0.1 June 7, 2010 Martin
More informationI/O Virtualization Using Mellanox InfiniBand And Channel I/O Virtualization (CIOV) Technology
I/O Virtualization Using Mellanox InfiniBand And Channel I/O Virtualization (CIOV) Technology Reduce I/O cost and power by 40 50% Reduce I/O real estate needs in blade servers through consolidation Maintain
More informationMellanox Cloud and Database Acceleration Solution over Windows Server 2012 SMB Direct
Mellanox Cloud and Database Acceleration Solution over Windows Server 2012 Direct Increased Performance, Scaling and Resiliency July 2012 Motti Beck, Director, Enterprise Market Development Motti@mellanox.com
More informationA Comparison of NVMe and AHCI
A Comparison of NVMe and AHCI Enterprise Storage OCTO Primary Contacts: Don H Walker Version: 1.0 Date Created: 7/31/2012 Page 1 Page 2 Table of Contents NVME AND AHCI... 1 1 INTRODUCTION... 6 2 OVERVIEW...
More informationWhite Paper Abstract Disclaimer
White Paper Synopsis of the Data Streaming Logical Specification (Phase I) Based on: RapidIO Specification Part X: Data Streaming Logical Specification Rev. 1.2, 08/2004 Abstract The Data Streaming specification
More informationIntegrating PCI Express into the PXI Backplane
Integrating PCI Express into the PXI Backplane PCI Express Overview Serial interconnect at 2.5 Gbits/s PCI transactions are packetized and then serialized Low-voltage differential signaling, point-to-point,
More informationSerial ATA in Servers and Networked Storage
Serial ATA in Servers and Networked Storage Serial ATA (SATA) in Servers and Networked Storage Introduction Serial ATA (SATA) is a storage interface technology developed by a group of the industry s leading
More informationOptimizing Large Arrays with StoneFly Storage Concentrators
Optimizing Large Arrays with StoneFly Storage Concentrators All trademark names are the property of their respective companies. This publication contains opinions of which are subject to change from time
More informationXMC Modules. XMC-6260-CC 10-Gigabit Ethernet Interface Module with Dual XAUI Ports. Description. Key Features & Benefits
XMC-6260-CC 10-Gigabit Interface Module with Dual XAUI Ports XMC module with TCP/IP offload engine ASIC Dual XAUI 10GBASE-KX4 ports PCIe x8 Gen2 Description Acromag s XMC-6260-CC provides a 10-gigabit
More informationWhite Paper: M.2 SSDs: Aligned for Speed. Comparing SSD form factors, interfaces, and software support
White Paper: M.2 SSDs: Aligned for Speed Comparing SSD form factors, interfaces, and software support M.2 SSDs: Aligned for Speed A flurry of new standards activity has opened a wide range of choices for
More information