Errata for the PCI Express Base Specification Revision 3.0

Transcription

1 Errata for the PCI Express Base Specification Revision 3.0 October 23, 2014 PCIe_Base_r3_0_Errata_ _clean.docx

2 REVISION REVISION HISTORY DATE 1.0 Initial release of errata: A1-A12 and B1-B6. 10/20/ a Add Precision Time Mechanism ECN Revision 1.0a 03/31/ Added errata A6a, A13-A23, B7-B28 06/20/ Added errata A24-A27, B29-B34 11/07/ Added errata MA1, MA2, MB3-MB24, MC1-MC8 10/23/2014 PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of this specification. Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to: Membership Services administration@pcisig.com Phone: Fax: Technical Support techsupp@pcisig.com DISCLAIMER This PCI Express Base Specification Errata document is provided as is with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright PCI-SIG PCIe_Base_r3_0_Errata_ _clean.docx 2

3 Contents A1 Interoperability Criteria... 5 A2 Management of Link Speeds... 7 A3 Vendor_Defined Messages... 8 A4 Transmitter Equalization... 8 A5 Fast Training Sequence... 9 A6 Polling.Active Substate (obsolete; replaced by A6a) A6a Polling Active Substate (replacement for A6) A7 AtomicOp Request Rules A8 ST Table Size A9 Steering Tags in Interrupt Vector Mode A10 ST Table Location A11 Request Handling Rules A12 Rules for Data Poisoning A13 AT Field A14 D0uninitialized A15 Recovery A16 L1 Entry A17 Power Budgeting Data Select Register A18 Device and Multi-Function Device Terminology A19 Host Bridge, Root Complex, and Root Port Terminology A20 Hierarchy Domains Terminology A21 L1 PM Substates A22 PTM Timestamp Measurement A23 CLKREQ# Rules in L1 PM Substates ECN A24 Error Handling A25 128b/130b SKP OS Rules A26 SRIS Modified Compliance Pattern A27 Readiness Notification B1 Tx_L0s.FTS B2 Memory Base Address Registers B3 Error Logging B4 Message Request Rules B5 PCI Express Capabilities Register B6 TPH Requester Capability Register B7 TLP Prefix Blocked Error B8 Variant fields in TLP Header B9 Data Link Layer B10 Flow Control Units B11 Resizable BAR Control Register B12 Transmitter Coefficients B13 TS2 Ordered Set B14 Encoding of Presets B15 First Error Pointer B16 Data Link Control and Management State Machine B17 Clock Request Support B18 SIG-Defined VDMs B19 Interrupt Signaling PCIe_Base_r3_0_Errata_ _clean.docx 3

4 B20 DPC: Error Message Controls Pseudo-Logic Diagram B21 Downstream Port Containment: Error Listing and Rules B22 Error Message Controls Pseudo-Logic Diagram B23 Loopback.Entry B24 Training Sequences B25 Latency Tolerance Reporting B26 Secondary PCI Express Extended Capability 8.0GT/s support B27 Infinite FC Advertisement B28 Lane Based Error Clause B29 Slot Capabilities Register B30 LN Message B31 DPC Auto Slot Power Limit Disable B32 Egress Control Vector B33 Extended TPH B34 SRIS Rules C1 PCI-SIG Defined M-PCIe Errata: MA1 M-PCIe Entering HIBERN MA2 M-PCIe Asymmetric Loopback MB3 M-PCIe Detect.Quiet MB4 M-PCIe RX_PWM_Burst_Closure_Length_Capability MB5 M-PCIe LINK_MIN_SAVE_CONFIG_TIME MB6 M-PCIe TX and RX Min_SAVE_Config_Time_Capability MB9 M-PCIe Bandwidth Change MB11 M-PCIe Configuration.Software State MB15 M-PCIe 2K PPM Clock Compensation MB22 M-PCIe Lane Mode bits MB23 M-PCIe Burst Count MB24 M-PCIe Error Count MC1 M-PCIe RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY MC2 M-PCIe LINK_HSGEAR MC3 M-PCIe L0 to Recovery MC4 M-PCIe RPAT / CRPAT MC5 M-PCIe LINE-RESET and Fundamental Reset MC6 M-PCIe ACK_Latency MC7 M-PCIe Capability for M-PCIe Links Only MC8 M-PCIe and SRIS PCIe_Base_r3_0_Errata_ _clean.docx 4

5 A1 Interoperability Criteria In Section 4.3.2, page 323, line 15, make the following changes: Interoperability Criteria for 2.5, 5.0, and 8.0 GT/s Devices The PCI Express electrical specification is constructed to guarantee backwards compatibility among devices of all three speeds. Since all devices power up at 2.5 GT/s interoperability at that speed is guaranteed. Operation at 5.0 or 8.0 GT/s requires that the two devices negotiate to a higher data rate. Details of this process are defined in the protocol section. 8.0 GT/s root Port devices must support 2.5, 5.0, and 8.0 GT/s operation, because a downstream device could support any of these data rates. A downstream device must support 2.5 GT/s and may, support either 5.0 or 8.0 GT/s operation, or both. 5.0 GT/s devices must support 2.5 and 5.0 GT/s operation. See also Table 4-5 and Table 4-6. The Refclk is defined as part of the 3.0 electrical specification with the expectation that the characteristics which define a minimally compliant Refclk are approximately the same for all three data rates. In other words, operation at the higher data rates is not predicated upon improving the jitter characteristics of the Refclk. In Section , Table 7-26, page 659, make the following changes: Table 7-26: Link Capabilities 2 Register Bit Location Register Description Attributes 7:1 Supported Link Speeds Vector This field indicates the supported Link speed(s) of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported. See Section for further requirements. Bit definitions within this field are: Bit 0 Bit 1 Bit GT/s 5.0 GT/s 8.0 GT/s Bits 6:3 RsvdP Multi-Function devices associated with an Upstream Port must report the same value in this field for all Functions. RO PCIe_Base_r3_0_Errata_ _clean.docx 5

6 In Section , Table 7-60, page 716, make the following changes: Table 7-60: Root Complex Link Capabilities Register Bit Location Register Description Attributes 24:18 Supported Link Speeds Vector This field indicates the supported Link speed(s) of the associated Link. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported. See Section for further requirements. RO Bit definitions within this field are: Bit 0 Bit 1 Bit 2 Bits 6:3 2.5 GT/s 5.0 GT/s 8.0 GT/s RsvdP In Section , Table 4-5, page 229, make the following changes: Symbol Number Description 4 Data Rate Identifier Table 4-5: TS1 Ordered Set Bit 0 Reserved Bit GT/s Data Rate Supported. Must be set to 1b. Bit GT/s Data Rate Supported. Must be set to 1b if Bit 3 is 1b. See Section Bit GT/s Data Rate Supported. Bit 4:5 Reserved. Bit 6 Autonomous Change/Selectable De-emphasis. Downstream Ports: This bit is defined for use in the following LTSSM states: Polling.Active, Configuration.LinkWidth.Start, and Loopback.Entry. In all other LTSSM states, it is Reserved. Upstream Ports: This bit is defined for use in the following LTSSM states: Polling.Active, Configuration, Recovery, and Loopback.Entry. In all other LTSSM states, it is Reserved. Bit 7 speed_change. This bit can be set to 1b only in the Recovery.RcvrLock LTSSM state. In all other LTSSM states, it is Reserved. PCIe_Base_r3_0_Errata_ _clean.docx 6

7 In Section , Table 4-6, page 231, make the following changes: Symbol Number Description 4 Data Rate Identifier Table 4-6: TS2 Ordered Set Bit 0 Reserved Bit GT/s Data Rate Supported. Must be set to 1b. Bit GT/s Data Rate Supported. Must be set to 1b if Bit 3 is 1b. See Section Bit GT/s Data Rate Supported. Bit 4:5 Reserved. Bit 6 Autonomous Change/Selectable De-emphasis/Link Upconfigure Capability. This bit is defined for use in the following LTSSM states: Polling.Configuration, Configuration.Complete, and Recovery. In all other LTSSM states, it is Reserved. Bit 7 speed_change. This bit can be set to 1b only in the Recovery.RcvrCfg LTSSM state. In all other LTSSM states, it is Reserved. A2 Management of Link Speeds In Section , page 659, line 11, add the following implementation note: IMPLEMENTATION NOTE Software Management of Link Speeds With Future Hardware It is strongly encouraged that software primarily utilize the Supported Link Speeds Vector instead of the Max Link Speed field, so that software can determine the exact set of supported speeds on current and future hardware. This can avoid software being confused if a future specification defines Links that do not require support for all slower speeds. In Section , page 717, add the following implementation note before Section : IMPLEMENTATION NOTE Software Management of Link Speeds With Future Hardware It is strongly encouraged that software primarily utilize the Supported Link Speeds Vector instead of the Max Link Speed field, so that software can determine the exact set of supported speeds on current and future hardware. This can avoid software being confused if a future specification defines Links that do not require support for all slower speeds. PCIe_Base_r3_0_Errata_ _clean.docx 7

8 A3 Vendor_Defined Messages In Section , page 93, line 11, make the following changes: The Vendor_Defined Messages (see Table 2-25) use the header format shown in Figure The Requester ID is implementation specific. It is strongly recommended that the Requester ID field contain the value associated with the Requester. <footnote> If the Route by ID routing is used, bytes 8 and 9 form a 16-bit field for the destination ID otherwise these bytes are Reserved. Bytes 10 and 11 form a 16-bit field for the Vendor ID, as defined by PCI-SIG, of the vendor defining the Message. Bytes 12 through 15 are available for vendor definition. <footnote> ACS Source Validation (see Section ) checks the Requester ID on all Requests, including Vendor_Defined Messages. This validation depends on the Requester ID properly identifying the Requester. A4 Transmitter Equalization In Section , page 283, line 26, make the following changes: If two consecutive TS1 Ordered Sets are received with the Transmitter Preset field (for a preset request) or the Pre-cursor, Cursor, and Post-Cursor fields (for a coefficients request) identical to what was requested and the Reject Coefficient Values bit is set to 0b, then the requested setting was accepted and can be considered for evaluation. If two consecutive TS1 Ordered Sets are received with the Transmitter Preset field (for a preset request) or the Precursor, Cursor, and Post-Cursor fields (for a coefficients request) identical to what was requested and the Reject Coefficient Values bit is set to 1b, then the requested setting was rejected. It is recommended that the Downstream Port request a different preset or set of coefficients. However, the Downstream Port is permitted to exit this phase and not make any additional requests. The Downstream Port is responsible for setting the Reset EIEOS Interval Count bit in the TS1 Ordered Sets it transmits according to its evaluation criteria and requirements. The Use Preset bit of the received TS1 Ordered Sets must not be used to determine whether a request is accepted or rejected. In Section , page 286, line 26, make the following changes: If two consecutive TS1 Ordered Sets are received with the Transmitter Preset field (for a preset request) or the Pre-cursor, Cursor, and Post-Cursor fields (for a coefficients request) identical to what was requested and the Reject Coefficient Values bit is set to 0b, then the requested setting was accepted and can be considered for evaluation. If two consecutive TS1 Ordered Sets are received with the Transmitter Preset field (for a preset request) or the Pre- Cursor, Cursor, and Post-Cursor fields (for a coefficients request) identical to what was requested and the Reject Coefficient Values bit is set to 1b, then the requested setting was rejected. It is recommended that the Upstream Port request a different preset or set of coefficients. However, the Upstream Port is permitted to exit this phase and not make any additional requests. The Upstream Port is responsible for setting the Reset EIEOS Interval PCIe_Base_r3_0_Errata_ _clean.docx 8

9 Count bit in the TS1 Ordered Sets it transmits according to its evaluation criteria and requirements. The Use Preset bit of the received TS1 Ordered Sets must not be used to determine whether a request is accepted or rejected. A5 Fast Training Sequence In Section , page 238, line 22, make the following changes: Fast Training Sequence (FTS) Fast Training Sequence (FTS) is the mechanism that is used for bit and Symbol lock when transitioning from L0s to L0. The FTS is used by the Receiver to detect the exit from Electrical Idle and align the Receiver s bit and Symbol receive circuitry to the incoming data. Refer to Section for a description of L0 and L0s. At 2.5 GT/s and 5.0 GT/s data rates: A single FTS is comprised of one K28.5 (COM) Symbol followed by three K28.1 Symbols. The maximum number of FTSs (N_FTS) that a component can request is 255, providing a bit time lock of 4 * 255 * 10 * UI. If the data rate is 5.0 GT/s, four consecutive EIE Symbols are transmitted at valid signal levels prior to transmitting the first FTS. These Symbols will help the Receiver detect exit from Electrical Idle. An implementation that does not guarantee proper signaling levels for up to the allowable time on the Transmitter pins (see Table 4-18)since exiting Electrical Idle condition is required to prepend its first FTS by extra EIE Symbols so that the Receiver can receive at least four EIE Symbols at valid signal levels. Implementations must not transmit more than eight EIE Symbols prior to transmitting the first FTS. A component is permitted to advertise different N_FTS rates at different speeds. At 5.0 GT/s, a component may choose to advertise an appropriate N_FTS number considering that it will receive the four EIE Symbols FTSs must be sent when the Extended Synch bit is set in order to provide external Link monitoring tools with enough time to achieve bit and framing synchronization. SKP Ordered Sets must be scheduled and transmitted between FTSs as necessary to meet the definitions in Section with the exception that no SKP Ordered Sets can be transmitted during the first N_FTS FTSs. A single SKP Ordered Set is always sent after the last FTS is transmitted. It is permitted for this SKP Ordered Set to affect or not affect the scheduling of subsequent SKP Ordered Sets for Clock Tolerance Compensation by the Transmitter as described in Section Note that it is possible that two SKP Ordered Sets can be transmitted back to back (one SKP Ordered Set to signify the completion of the 4096 FTSs and one scheduled and transmitted to meet the definitions described in Section 4.2.7). PCIe_Base_r3_0_Errata_ _clean.docx 9

10 A6 Polling.Active Substate (obsolete; replaced by A6a) In Section , page 252, line 10, make the following changes: Otherwise, after a 24 ms timeout the next state is: Polling.Configuration if, i. Any Lane, which detected a Receiver during Detect, received eight consecutive training sequences (or their complement) satisfying any of the following conditions: TS1 with Lane and Link numbers set to PAD and the Compliance Receive bit (bit 4 of Symbol 5) is 0b. 2. TS1 with Lane and Link numbers set to PAD and the Loopback bit (bit 2 of Symbol 5) is 1b. 3. TS2 with Lane and Link numbers set to PAD. and a minimum of 1024 TS1 Ordered Sets are transmitted after receiving one TS1 or TS2 Ordered Set, or optionally after receiving one TS1 Ordered Set. And A6a Polling Active Substate (replacement for A6) In Section , page 252, line 10, make the following changes: Otherwise, after a 24 ms timeout the next state is: Polling.Configuration if, i. Any Lane, which detected a Receiver during Detect, received eight consecutive training sequences (or their complement) satisfying any of the following conditions: And TS1 with Lane and Link numbers set to PAD and the Compliance Receive bit (bit 4 of Symbol 5) is 0b. 2. TS1 with Lane and Link numbers set to PAD and the Loopback bit (bit 2 of Symbol 5) is 1b. 3. TS2 with Lane and Link numbers set to PAD. and a minimum of 1024 TS1 Ordered Sets are transmitted after receiving one TS1 or TS2 Ordered Set <footnote>. <footnote> Earlier versions of this specification required transmission of 1024 TS1 Ordered Sets after receiving one TS1 Ordered Set. This behavior is still permitted but the implementation will be more robust if it follows the behavior of transmitting 1024 TS1 Ordered Sets after receiving one TS1 or TS2 Ordered Set. PCIe_Base_r3_0_Errata_ _clean.docx 10

11 A7 AtomicOp Request Rules In Section 2.2.7, page 77, line 21, make the following changes: For AtomicOp Requests, architected operand sizes and their associated Length field values are specified in Table If a Completer supports AtomicOps, the following rules apply. The Completer must check the Length field value. If the value does not match an architected value, the Completer must handle the TLP as a Malformed TLP. Otherwise, if the value does not match an operand size that the Completer supports, the Completer must handle the TLP as an Unsupported Request (UR). This is a reported error associated with the Receiving Port (see Section 6.2). A8 ST Table Size In Section , page 773, Table 7-110, make the following changes: Table 7-110: TPH Requester Capability Register Bit Location Register Description Attributes 26:16 ST Table Size Value indicates the maximum number of ST Table entries the Function may use. Software reads this field to determine the ST Table Size N, which is encoded as N-1. For example, a returned value of b indicates a table size of four entries. There is an upper limit of 64 entries when the ST Table is located in the TPH Requester Capability structure. There is an upper limit of 2048 entries wwhen the ST Table is located in the MSI-X Table, this value is limited by the size of the MSI-X Table. This field is only applicable for Functions that implement an ST Table as indicated by the ST Table Location field. Otherwise, the value in this field is undefined. RO PCIe_Base_r3_0_Errata_ _clean.docx 11

12 A9 Steering Tags in Interrupt Vector Mode In Section , page 563, line 5 make the following changes: In the Interrupt Vector Mode of operation, Steering Tags are selected from the ST Table using MSI/MSI-X interrupt vector numbers. For Functions that have MSI enabled, the Function is required to select tags within the range specified by the Multiple Message Enable field in the MSI Capability structure. For Functions that have MSI-X enabled, the Function is required to select tags within the range of the MSI-X Table size. If the ST Table Size is smaller than the enabled range of interrupt vector numbers, the Function is permitted to either not use TPH for certain transactions, to use TPH with a Steering Tag of 0 or to use TPH with an implementation defined mechanism used to select a Steering Tag value from the ST Table. If the ST Table Size is larger than the enabled range of interrupt vector numbers, ST Table Entries corresponding to out of range interrupt vector numbers are ignored by the Function. In the Device Specific Mode of operation, the assignment of the Steering Tags to Requests is device specific. The number of Steering Tags used by the Function is permitted to be different than the number of interrupt vectors allocated for the Function, irrespective of the ST Table location, and Steering Tag values used in Requests are not required to come from the architected ST Table. A Function that is capable of generating TPH Requests is required to support the No ST Mode of operation. Support for other ST Modes of operation is optional. Only one ST Mode of operation can be selected at a time by programming ST Mode Select. A10 ST Table Location In Section , page 562, line 11, make the following changes: The choice of ST Table location is implementation specific and is discoverable by software. A Function that implements MSI-X is permitted to locate the ST Table in either location (see Section ). A Function that implements both MSI and MSI-X is permitted to combine the ST Table with the MSI-X Table and use it, even when MSI-X is disabled (i.e., when MSI is enabled). Each ST Table entry is 2 bytes. The size of the ST Table is indicated in the TPH Requester Capability structure. For some usage models the Steering Tags are not required or not provided, and in such cases a Function is permitted to use a value of all zeroes in the ST field to indicate no ST preference. The association of each Request with an ST Table entry is device specific and outside the scope of this specification. PCIe_Base_r3_0_Errata_ _clean.docx 12

13 A11 Request Handling Rules In Section 2.3.1, page 109, line 1, make the following changes: If the Request is a Message, and the Message Code, routing field, or Msg/MsgD indication corresponds to a combination specifies a value that is undefined, or that corresponds to a Message not supported by the device Function, (other than Vendor_Defined Type 1 which is not treated as an error see Section ), the Request is an Unsupported Request, and is reported according to Section 6.2 If the Message Code is a supported value, process the Message according to the corresponding Message processing rules; if the Message Code is an Ignored Message and the receiver is ignoring it, ignore the Message without reporting any error (see Section ) A12 Rules for Data Poisoning In Section , page 150, line 24, make the following changes: The following Requests with Poisoned data must not modify the value of the target location: Configuration Write Request Any of the following that target a control register or control structure in the Completer: I/O Write Request, Memory Write Request, or non-vendor-defined Message with data AtomicOp Request Unless there is a higher precedence error, a Completer must handle these Requests as a Poisoned TLP Received error, 35 and the Completer must also return a Completion with a Completion Status of Unsupported Request (UR) if the Request is Non-Posted (see Section , Section , and Section 6.2.5). Regardless of the severity of the reported error, the reported error must be handled as an uncorrectable error, not an Advisory Non-Fatal Error. In Section , page 471, footnote 64, make the following changes: 64 Certain other errors (e.g., ACS Violation) with a Non-Posted Request also result in the Completer sending a Completion with UR or CA Status. If the severity of the error (e.g., ACS Violation) is non-fatal, the Completer must also handle this case as an Advisory Non-Fatal Error. However, see Section regarding certain Requests with Poisoned data that must be handled as uncorrectable errors. In Section , page 472, line 5, make the following changes: When a poisoned TLP is received by its ultimate PCI Express destination, if the severity is non-fatal and the Receiver deals with the poisoned data in a manner that permits continued operation, the Receiver must handle this case <footnote> as an Advisory Non-Fatal Error. 69 A Receiver with AER signals the error (if enabled) by sending an ERR_COR Message. A Receiver without AER sends no error Message for this case. Refer to Section for special rules that apply for poisoned Memory Write Requests. <footnote> However, see Section regarding certain Requests with Poisoned data that must be handled as uncorrectable errors. 69 If the severity is fatal, the error is not an Advisory Non-Fatal Error, and must be signaled (if enabled) with ERR_FATAL. PCIe_Base_r3_0_Errata_ _clean.docx 13

14 A13 AT Field In section , page 66, line 3, make the following changes: For Memory Read, Memory Write, and AtomicOp Requests, the Address Type (AT) field is encoded as shown in Table 2-5, with full descriptions contained in the Address Translation Services Specification. For all other Requests, the AT field is Reserved unless explicitly stated otherwise. In section 2.2.7, page 79, line 14, make the following changes: I/O Requests have the following restrictions: TC[2:0] must be 000b TH is not applicable to I/O Requests and the bit is Reserved Attr[2] is Reserved Attr[1:0] must be 00b AT[1:0] must be 00b. Receivers are not required or encouraged to check this. In section 2.2.7, page 80, line 13, make the following changes: Configuration Requests have the following restrictions: TC[2:0] must be 000b TH is not applicable to Configuration Requests and the bit is Reserved Attr[2] is Reserved Attr[1:0] must be 00b AT[1:0] must be 00b. Receivers are not required or encouraged to check this. A14 D0uninitialized In Section , page 420, line 3, make the following changes: All Functions must support the D0 state. D0 is divided into two distinct substates, the uninitialized substate and the active substate. When a component comes out of Conventional Reset or FLR, it defaults to all Functions of the component enter the D0 uninitialized state. When a Function completes FLR, it enters the D0 uninitialized state. Components that are in this state will be enumerated and configured by the Hierarchy enumeration process. Following the completion of the enumeration and After configuration is complete a process the Function enters the D0 active state, the fully operational state for a PCI Express Function. A Function enters the D0 active state whenever any single or combination of the Function s Memory Space Enable, I/O Space Enable, or Bus Master Enable bits have been Set enabled by system software. <footnote> <footnote> A Function remains in D0active even if these enable bits are subsequently cleared. PCIe_Base_r3_0_Errata_ _clean.docx 14

15 A15 Recovery Errata for the PCI Express Base Specification, Revision 3.0 In Section , page 276, line 21, make the following changes: Else: The Transmitter must use the coefficient settings agreed upon at the conclusion of the last equalization procedure If this substate was entered from Recovery.Equalization, in the transmitted TS1 Ordered Sets, a Downstream Port must set the Pre-cursor, Cursor, and Post-cursor Coefficient fields to the current Transmitter settings, and if the last accepted request in Phase 2 of Recovery.Equalization was a preset request, it must set the Transmitter Preset field to the accepted preset of that request. It is recommended that in this substate, in the transmitted TS1 Ordered Sets, all Ports set the Pre-cursor, Cursor, and Post-cursor Coefficient fields to the current Transmitter settings, and set the Transmitter Preset field to the most recent preset that the Transmitter settings were set to. An Upstream Port that receives eight consecutive TS1 Ordered Sets on all configured Lanes with the following characteristics must transition to Recovery.Equalization. In Section , page 282, line 28, make the following changes: If the preset or coefficients requested in the most recent two consecutive TS1 Ordered Sets are legal and supported (see Section 4.2.3): Change the transmitter settings to the requested preset or coefficients such that the new settings are effective at the Transmitter pins within 500 ns of when the end of the second TS1 Ordered Set requesting the new setting was received at the Receiver pin. The change of Transmitter settings must not cause any illegal voltage level or parameter at the Transmitter pin for more than 1 ns. Reflect the new settings iin the transmitted TS1 Ordered Sets, the Transmitter Preset field is set to the requested preset (for a preset request), the Pre-cursor, Cursor, and Post-cursor Coefficient fields are set to the Transmitter settings (for a preset or a coefficients request), and clear the Reject Coefficient Values bit is set to 0b. Else (the requested preset or coefficients are illegal or unsupported): Do not change the Transmitter settings used, but reflect the requested preset or coefficient values in the transmitted TS1 Ordered Sets and set the Reject Coefficient Values bit to 1b. In Section , page 287, line 29, make the following changes: If the preset or coefficients requested in the most recent two consecutive TS Ordered Sets are legal and supported (see Section and 4.3): Change the transmitter settings to the requested preset or coefficients such that the new settings are effective at the Transmitter pins within 500 ns of when the end of the second TS1 Ordered Set requesting the new setting was received at the Receiver pin. The change of Transmitter settings must not cause any illegal voltage level or parameter at the Transmitter pin for more than 1 ns. Reflect the new requested settings iin the transmitted TS1 Ordered Sets, the Transmitter Preset field is set to the requested preset (for a preset request), the Precursor, Cursor, and Post-cursor Coefficient fields are set to the Transmitter settings PCIe_Base_r3_0_Errata_ _clean.docx 15

16 (for a preset or a coefficients request), and clear the Reject Coefficient Values bit is set to 0b. Else (the requested preset or coefficients are illegal or unsupported): Do not change the Transmitter settings used, but reflect the requested preset or coefficient values in the transmitted TS1 Ordered Sets and set the Reject Coefficient Values bit to 1b. A16 L1 Entry In Section 5.2, page 418, line 11, make the following changes: The L1 entry negotiation (whether invoked via PCI-PM or ASPM mechanisms) and the L2/L3 Ready entry negotiation map to a state machine which corresponds to the actions described later in this chapter. This state machine is reset to an idle state. For a Downstream component, the first action taken by the state machine, after leaving the idle state, is to start sending the appropriate entry DLLPs depending on the type of negotiation. If the negotiation is interrupted, for example by a trip through Recovery, the state machine in both components is reset back to the idle state. For tthe Upstream component, this must always means to go to the idle state, and wait to receive entry DLLPs. For tthe Downstream component, this means must always go to the idle state and must always proceed to sending entry DLLPs to restart the negotiation. A17 Power Budgeting Data Select Register In Section , page 721, line 5, make the following changes: The Data Select Register is an 8-bit This read-write register that indexes the Power Budgeting Data reported through the Data register and selects the DWORD of Power Budgeting Data that is to appear in the Data register. Index vvalues for this register start at zero to select the first DWORD of Power Budgeting Data; subsequent DWORDs of Power Budgeting Data are selected by increasing index values. The default value of this register is undefined. In Section , page 722, line 1, make the following changes: This read-only register returns the DWORD of Power Budgeting Data selected by the Data Select register. Each DWORD of the Power Budgeting Data describes the power usage of the device in a particular operating condition. Power Budgeting Data for different operating conditions is not required to be returned in any particular order, as long as incrementing the Data Select register causes information for a different operating condition to be returned. If the Data Select register contains a value greater than or equal to the number of operating conditions for which the device provides power information, this register must return all zeros. The default value of this register is undefined. Figure 7-73 details allocation of register fields in the Power Budgeting Data register; Table 7-64 provides the respective bit definitions. PCIe_Base_r3_0_Errata_ _clean.docx 16

17 In Section , page 722, Table 7-64, make the following changes: Table 7-110: TPH Requester Capability Register Bit Location Register Description 7:0 Base Power Specifies in watts the base power value in the given operating condition. This value must be multiplied by the data scale to produce the actual power consumption value except when the Data Scale field equals 00b (1.0x) and Base Power exceeds EFh, the following alternative encodings are used: Attributes RO F0h = F1h = F2h = F3h to FFh = 250 W Slot Power Limit 275 W Slot Power Limit 300 W Slot Power Limit Reserved for Slot Power Limit values above 300 W 14:13 PM State Specifies the power management state of the operating condition being described. RO Defined encodings are: 00b 01b 10b 11b D0 D1 D2 D3 A device returns 11b in this field and Aux or PME Aux in the Type field register to specify the D3-Cold PM State. An encoding of 11b along with any other Type field register value specifies the D3-Hot state. A18 Device and Multi-Function Device Terminology In the Terms and Acronyms section, page 29, make the following changes: ARI Device Completer ID A multi-function Device associated with an Upstream Port, capable of supporting up to 256 Functions whose Functions each contain an ARI Capability structure. The combination of a Completer's Bus Number, Device Number, and Function Number that uniquely identifies the Completer of the Request within a Hierarchy. With an ARI Completer ID, bits traditionally used for the Device Number field are used instead to expand the Function Number field, and the Device Number is implied to be 0. PCIe_Base_r3_0_Errata_ _clean.docx 17

18 Configuration Space Device Function Hierarchy Errata for the PCI Express Base Specification, Revision 3.0 One of the four address spaces within the PCI Express architecture. Packets with a Configuration Space address are used to configure a Functions within a device. A collection of one or more Functions within a single Hierarchy identified by common Bus Number and Device Number. An SR-IOV Device may have additional Functions accessed via additional Bus Numbers configured through one or more SR-IOV Capability structures. An Within a Device, an addressable entity in Configuration Space associated with a single Function Number. May be uused to refer to one Function of a multi-function ddevice, or to the only Function in a single-function ddevice. Specifically included are special types of Functions defined in the I/O Virtualization specifications, notably Physical Functions and Virtual Functions. The A tree-structured PCI Express I/O interconnect topology, wherein the Configuration Space addresses (IDs) used for routing and Requester/Completer identification are unique. A system may contain multiple Hierarchies. multi-function Device, MFD A Device that has multiple Functions. Requester ID The combination of a Requester's Bus Number, Device Number, and Function Number that uniquely identifies the Requester within a Hierarchy. With an ARI Requester ID, bits traditionally used for the Device Number field are used instead to expand the Function Number field, and the Device Number is implied to be 0. single-function Device, SFD A Device that has a single Function. SR-IOV SR-IOV Device Single Root I/O Virtualization and Sharing, a separate specification. A Device containing one or more Functions that have an SR-IOV Capability structure. In Section 7.3.2, page 584, line 10 make the following changes: PCIe_Base_r3_0_Errata_ _clean.docx 18

19 Function Number PCI Express also supports multi-function devices using the same discovery mechanism as PCI 3.0. A multi-function Device must fully decode the Function Number field. It is strongly recommended that a single-function Device also fully decode the Function Number field. With ARI Devices, discovery and enumeration of Extended Functions require ARI-aware software. See Section After Section , page 593, insert a new Section and renumber subsequent Sections in 7.5.1: Latency Timer Register (Offset 0Dh) This register is also referred to as Primary Latency Timer for Type 1 Configuration Space header Functions. The Latency Timer does not apply to PCI Express. This register must be hardwired to 00h Header Type Register (Offset 0Eh) This register identifies the layout of the second part of the predefined header (beginning at byte 10h in Configuration Space) and also whether or not the Device might contain multiple Functions. Table 7-x: Header Type Register Bit Location Register Description Attributes 7 Multi-Function Device When Set, indicates that the Device may contain multiple Functions, but not necessarily. Software is permitted to probe for Functions other than Function 0. When Clear, software must not probe for Functions other than Function 0 unless explicitly indicated by another mechanism, such as an ARI or SR-IOV Capability structure. Except where stated otherwise, it is recommended that this bit be Set if there are multiple Functions, and Clear if there is only one Function. RO Interrupt Line Register (Offset 3Ch) Interrupt Pin Register (Offset 3Dh) Error Registers A19 Host Bridge, Root Complex, and Root Port Terminology In the Terms and Acronyms section, page 32, make the following changes: Host Bridge The ppart of a Root Complex that connects a host CPU or CPUs to a Hierarchy. PCIe_Base_r3_0_Errata_ _clean.docx 19

20 In the Terms and Acronyms section, page 34, make the following changes: Root Complex, RC A defined System Element that includes zero or more a Host Bridges, zero or more Root Complex Integrated Endpoints, zero or more Root Complex Event Collectors, and one or more Root Ports. Root Complex Component A logical aggregation of Root Ports, Root Complex Register Blocks, and Root Complex Integrated Endpoints, and Root Complex Event Collectors. Root Port A PCI Express Port on a Root Complex that maps a portion of a the Hierarchy through an associated virtual PCI-PCI Bridge. A20 Hierarchy Domains Terminology In Section , page 536, line 1, make the following changes: subset of the Root Port hierarchies Hierarchy Domains to send peer-to-peer Requests to other Root Port hierarchies Hierarchy Domains. This is configured on a per Root Port basis. In Section , page 646, Table 7-21, make the following changes: Table 7-21: Root Control Register Bit Location Register Description Attributes 0 System Error on Correctable Error Enable If Set, this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the hhierarchy Domain associated with this Root Port, or by the Root Port itself. The mechanism for signaling a System Error to the system is system specific. Root Complex Event Collectors provide support for the abovedescribed functionality for Root Complex Integrated Endpoints. Default value of this bit is 0b. RW 1 System Error on Non-Fatal Error Enable If Set, this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the hhierarchy Domain associated with this Root Port, or by the Root Port itself. The mechanism for signaling a System Error to the system is system specific. Root Complex Event Collectors provide support for the abovedescribed functionality for Root Complex Integrated Endpoints. Default value of this bit is 0b. RW PCIe_Base_r3_0_Errata_ _clean.docx 20

21 Bit Location Register Description Attributes 2 System Error on Fatal Error Enable If Set, this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the hhierarchy Domain associated with this Root Port, or by the Root Port itself. The mechanism for signaling a System Error to the system is system specific. Root Complex Event Collectors provide support for the abovedescribed functionality for Root Complex Integrated Endpoints. Default value of this bit is 0b. RW In Section , page 684, Table 7-38, make the following change: Table 7-38: Root Error Command Register Bit Location Register Description Attributes 0 Correctable Error Reporting Enable When Set, this bit enables the generation of an interrupt when a correctable error is reported by any of the Functions in the hhierarchy Domain associated with this Root Port. Root Complex Event Collectors provide support for the above described functionality for Root Complex Integrated Endpoints. Refer to Section 6.2 for further details. RW 1 Non-Fatal Error Reporting Enable When Set, this bit enables the generation of an interrupt when a Non-fatal error is reported by any of the Functions in the hhierarchy Domain associated with this Root Port. Root Complex Event Collectors provide support for the above described functionality for Root Complex Integrated Endpoints. Refer to Section 6.2 for further details. 2 Fatal Error Reporting Enable When Set, this bit enables the generation of an interrupt when a Fatal error is reported by any of the Functions in the hhierarchy Domain associated with this Root Port. Root Complex Event Collectors provide support for the above described functionality for Root Complex Integrated Endpoints. Refer to Section 6.2 for further details. RW RW In the Lightweight Notification (LN) ECN (ECN_LN_Protocol_ pdf), page 10, line 10, make the following change: LN protocol permits multiple LNRs to register the same line concurrently. In this case the LNC notifies the multiple LNRs either by sending a directed LN Message to each LNR, or by sending a broadcast LN Message to each affected Hierarchy DomainRoot Port hierarchy. PCIe_Base_r3_0_Errata_ _clean.docx 21

22 In the Lightweight Notification (LN) ECN (ECN_LN_Protocol_ pdf), page 10, line 30, make the following change: IMPLEMENTATION NOTE Excessive Use of Broadcast LN Messages In order to avoid performance issues, LNCs that use broadcast LN Messages should be implemented to minimize the number of Hierarchy DomainsRP hierarchies each broadcast LN Message is sent to, and also to keep the rate of broadcast LN Messages within reasonable bounds. Each broadcast LN Message consumes Link bandwidth, and some Endpoints may process broadcast LN Messages at a relatively low rate. A21 L1 PM Substates In Section , page 15, line 12, of the L1 PM Substates ECN (ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf), make the following change: Next state is L1.0 after waiting for TPOWER_ON. Common mode is permitted to be established passively during L1.0, and actively during Recovery. In order to ensure common mode has been established, the Downstream Port must maintain a timer, and the Downstream Port must not send TS2 training sequences until a minimum of TCOMMONMODE has elapsed since the Downstream Port has started both transmitting and receiving TS1 training sequences. In order to ensure common mode has been established, the Downstream Port must maintain a timer, and the Downstream Port must continue to send TS1 training sequences until a minimum of T COMMONMODE has elapsed since the Downstream Port has started transmitting TS1 training sequences and has detected electrical idle exit on any Lane of the configured Link. A22 PTM Timestamp Measurement This erratum was previously published in a different format in Version 1.0a of this Errata Document. In Section 6.x.2, page 10 of the Precision Time Mechanism ECN (ECN PTM_31_Mar_2013.pdf), make the following change: A PTM Requester must update its stored t4 timestamp when receiving a PTM Response Message, even if received TLP is a duplicate. Timestamps must be measured based on the STP Symbol or Token that frames the TLP, as if observed fromobserving the first bit of that Symbol or Token at the Port s pins. Typically this will require an implementation specific adjustment to compensate for the inability to directly measure the time at the actual pins, as the time will commonly be measured at some internal point in the Rx or Tx path. The accuracy and consistency of this PCIe_Base_r3_0_Errata_ _clean.docx 22

23 measurement are not bounded by this specification, but it is strongly recommended that the highest practical level of accuracy and consistency be achieved. A23 CLKREQ# Rules in L1 PM Substates ECN This erratum is included in the L1 PM Substates ECN Revision 1.0a (ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf). In the L1 PM Substates ECN (ECN_L1_PM_Substates_with_CLKREQ_23_Aug_2012.pdf), page 10, make the following change: When CLKREQ# is de-asserted the Ports enter the L1.2.Entry substate of L1.2. If a Downstream Port is in PCI-PM L1.0 and PCI-PM L1.1 Enable and/or PCI-PM L1.2 Enable are Set, or if a Downstream Port is in ASPM L1.0 and ASPM L1.1 Enable and/or ASPM L1.2 Enable are Set, and the Downstream Port initiates an exit to Recovery without having entered L1.1 or L1.2, the Downstream Port must assert CLKREQ# until the Link exits Recovery L1.1 Requirements A24 Error Handling In Section 2.3.1, page 110, line 31, make the following changes: Request Handling Rules If the Request is a type which requires a Completion to be returned, generate a Completion according to the rules for Completion Formation (see Section 2.2.9) The Completion Status is determined by the result of handling the Request If the Request has an ECRC Check Failed error, then it is implementation-specific whether to return a Completion or not, and if so, which of the architected values to use for its Completion Status. However, it is strongly recommended that the Completer return a Completion with a UR Completion Status. In Section , page 139, line 10, make the following changes: FC Information Tracked by Transmitter For each FC update received, if CREDIT_LIMIT is not equal to the update value, set CREDIT_LIMIT to the update value If a Transmitter detects that a TLP it is preparing to transmit is malformed, it is strongly recommended that the Transmitter discard the TLP and handle the condition as an Uncorrectable Internal Error. If a Transmitter detects that a TLP it is preparing to transmit appears to be properly formed but with bad ECRC, it is strongly recommended that the Transmitter transmit the TLP and update its internal Flow Control credits accordingly PCIe_Base_r3_0_Errata_ _clean.docx 23

24 The Transmitter gating function must In Section , page 141, line 10, make the following changes: FC Information Tracked by Receiver Updated as shown: [Field Size] CREDITS_RECEIVED = (CREDITS_ RECEIVED + Increment) mod 2 (Where Increment corresponds to the credits made available, and [Field Size] is 8 for PH, NPH, and CPLH and 12 for PD, NPD, and CPLD) for each Received TLP, provided that TLP: passes the Data Link Layer integrity checks is not malformed or (optionally) is malformed and is not ambiguous with respect to which buffer to release and is mapped to an initialized Virtual Channel does not consume more credits than have been allocated (see following rule) For a TLP with an ECRC Check Failed error, but which otherwise is unambiguous with respect to which buffer to release, it is strongly recommended that CREDITS_RECEIVED be updated. In Section 2.7.1, page 147, line 9, make the following changes: ECRC Rules Receivers which support end-to-end data integrity checks report violations as an ECRC Error. This reported error is associated with the receiving Port (see Section 6.2). Beyond the stated error reporting semantics contained elsewhere in this specification, howhow ultimate PCI Express Receivers make use of the end-to-end data integrity check provided through the ECRC is beyond the scope of this document. Intermediate Receivers are still required to forward TLPs whose ECRC checks fail. A PCI Express-to-PCI/PCI-X Bridge is classified as an ultimate PCI Express Receiver with regard to ECRC checking. In Section , page 469, line 31, make the following change: Error Pollution For errors detected in the Transaction layer and Uncorrectable Internal Errors, it is permitted and recommended that no more than one error be reported for a single received TLP, and that the following precedence (from highest to lowest) be used: Uncorrectable Internal Error Receiver Overflow Flow Control Protocol Error ECRC Check Failed Malformed TLP PCIe_Base_r3_0_Errata_ _clean.docx 24

25 ECRC Check Failed AtomicOp Egress Blocked TLP Prefix Blocked ACS Violation Errata for the PCI Express Base Specification, Revision 3.0 Here s an example of the rationale behind the precedence list. If an ECRC Check fails for a given TLP, the entire contents of the TLP including its header is potentially corrupt, so it makes little sense to report errors like Malformed TLP or Unsupported Request detected with the TLP. A25 128b/130b SKP OS Rules In Section , page 316, line 14 make the following changes: Note: The changes shown in green text were part of the SRIS ECN (ECN_SRIS_2012_10_Jan_2013.pdf) and are shown here for reference. Note: The changes shown in purple text are part of Errata B34 (below) Rules for Transmitters When using 128b/130b encoding: If the Link is not operating in SRNS or in SRIS, or and the bit corresponding to the current Link speed is Set in the Enable Lower SKP OS Generation Vector field and the LTSSM is in L0, aa SKP Ordered Set must be scheduled for transmission at an interval between 370 to 375 blocks, when the LTSSM is not in the Polling.Compliance state and is not in the Loopback state or, unless the Transmitter is a Loopback Slave that has not started looping back the incoming bit stream. If the Link is operating in SRIS and either the bit corresponding to the current Link speed is Clear in the Enable Lower SKP OS Generation Vector field or the LTSSM is not in L0, a SKP Ordered Set must be scheduled for transmission at an interval less than 38 blocks, when the LTSSM is not in the Loopback state or is a Loopback Slave that has not started looping back the incoming bit stream. When the LTSSM is in the Loopback state and the Link is operating in SRNS, the Loopback Master must schedule two SKP Ordered Sets to be transmitted, at most two blocks apart from each other, at an interval between 370 to 375 blocks. When the LTSSM is in the Loopback state and the Link is operating in SRIS, the Loopback Master must schedule two SKP Ordered Sets to be transmitted, at most two blocks apart from each other, at an interval of less than 38 blocks. When using 128b/130b encoding: The Compliance SOS register bit has no effect. While in Polling.Compliance, Transmitters must not transmit any SKP Ordered Sets other than those specified as part of the Modified Compliance Pattern in Section A26 SRIS Modified Compliance Pattern In Section , page 322, line 8 make the following changes: Modified Compliance Pattern in 128b/130b Encoding The modified compliance pattern, when not operating in SRIS, consists of repeating the following sequence of Blocks: PCIe_Base_r3_0_Errata_ _clean.docx 25