CH340G USB to UART Interface Datasheet

Transcription

1 WCH CH0G Datasheet WCH CH0 Series USB Interface Integrated Circuit CH0G USB to UART Interface Datasheet WCH Version E DreamCity Version.0 Disclaimer from This is a third-party translation of WCH s CH0 Series chipset s Chinese datasheet, with information regarding CH0G chip extracted. The two other chips sharing the same datasheet, CH0R and C0T, have official English version.. Overview CH0 is a series of USB bus adapters, that provides serial, parallel or IrDA interfaces over the USB bus (note: CH0G supports serial interface only). The CH0G integrate circuit provides common MODEM signals to allow adding a UART to a computer, or converting existing UART devices to USB interface.. Features Full-speed USB interface, compatible with USB.0 interface. Operates with a minimum amount of external components: a crystal and a minimum of four capacitors. Provides a virtual serial port for upgrading existing serial port devices or adding serial ports to a PC. Supports all existing applications using serial ports without the need of changing existing code. Hardware full-duplex serial interface with internal FIFO. Baud rate range from 0bps to Mbps. Supports common flow control signals RTS,, DCD, RI, DSR and. Supports RS, RS and RS with external level shifting components. Uses CH driver. Supports V and.v operation. RoHS-compliant narrow body SO- package. Page of WCH CH0G Datasheet

2 Table of Contents WCH CH0G Datasheet CH0G USB to UART Interface Datasheet Disclaimer from. Overview. Features Table of Contents. Specifications.. Absolute Maximum Ratings.. DC characteristics.. AC characteristics. Pinout. Application Notes.. Example: USB RS adapter.. Example: Optically isolated USB to UART adapter Page of WCH CH0G Datasheet

3 . Specifications.. Absolute Maximum Ratings WCH CH0G Datasheet Operating the chip at or beyond those ratings will cause the chip to malfunction, even irreversibly damage the chip. Symbol Name Minimum Maximum Unit TA Operating temperature -0 ºC TS Storage temperature -0 ºC VCC Supply rail voltage, reference to pin -0.. V VIO IO pin voltage, reference to pin -0. VCC+0. V.. DC characteristics Symbol Name Minimum Typical Maximum Unit VCC Supply rail voltage V operation...v operation... V ICC Operating current 0 ma ISLP Sleeping current V operation 0 00.V operation 0 0 µa VIL Low input voltage V VIH High input voltage.0 VCC+0. V VOL Low output voltage 0. V VOH High output voltage VCC-0. V IUP Internal pull-up strength 0 00 µa IDN Internal pull-down strength µa VR Brown-out detector threshold voltage... V.. AC characteristics Symbol Name Minimum Typical Maximum Unit FCLK Clock frequency (at pin XI) MHz TPR Power-on reset time 0 0 ms Page of WCH CH0G Datasheet

4 . Pinout WCH CH0G Datasheet Pin # Name Direction Comment Power Ground reference of the chip. Connect to the ground pin of USB bus. Output UART Data Transmit output. Input UART Data Receive input. V Power Internal.V reference for USB physical layer. Decouple with a.-0nf capacitor when in V operation, or tie to VCC when in.v operation. U Analog USB signal. UD- Analog USB D- signal. XI Input XO Output Input of the crystal oscillator. Connect to the crystal resonator and load capacitors. Output of the crystal oscillator. Connect to the crystal resonator and load capacitors. # Input UART flow control signal Clear to Send. 0 DSR# Input UART flow control signal Data Set Ready. RI# Input UART flow control signal Ring In. DCD# Input UART flow control signal Data Carrier Detect. # Output UART flow control signal Data Terminal Ready. RTS# Output UART flow control signal Request to Send. R Input Auxiliary RS enable. Active high, internal pull down. VCC Power Supply rail for the chip.. Application Notes CH0 chip have built in USB bus pull-up resistors and on-chip signal termination, U and UD- pins should be connected to the USB bus lines directly. CH0 have built in power on reset circuitry. During operation CH0 requires a MHz clock signal present at XI pin. Generally this clock signal is provided by connecting a MHz crystal resonator and load capacitors between XI and XO pins, and the built-in crystal resonator will provide the required clock signal. When using an external oscillator feed the clock signal into XI pin, and leave XO pin unconnected. CH0 supports V and.v operation. When using V operation, supply V to VCC pin, and decouple the internal.v reference with a capacitor of.-0nf from V pin to ground. When using.v operation, tie V pin to VCC pin and supply.v power. CH0 supports USB device suspension to reduce energy consumption. When NOS# signal is active this feature is disabled. (Note: CH0G does not have this pin.) Supported hardware flow control signals: #, DSR#, RI#, DCD#, # and RTS#. All flow control pins are software controlled. Auxiliary pins: IR#, R, CKO and ACT#. (Note: only R is present on CH0G) When R signal is asserted the signal is inverted. R is latched during Power-On Reset. Page of WCH CH0G Datasheet

5 WCH CH0G Datasheet CH0 have built-in FIFO buffer, and supports simplex, half- and full-duplex asynchronous communication. The UART interface supports start bit, - data bits, or stop bits, and odd, even, space or mark parity bits. CH0 supports common baud rates: 0,, 00, 0,., 0, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 000, 00, 00, 00, 000, 00, 000, 000, 00, 00000, baud. Transmitter baud rate error is less than 0.%, receiver baud rate error tolerance is at most %. The emulated COM port is fully functional. Compatible with most applications using the serial port, without the need of changing existing code. CH0 can be used to upgrade existing peripherals using serial ports into USB devices, or adding serial ports to a PC. With external level shifting hardware, interfaces including RS, RS and RS can be provided. By adding infrared adapters, CH0 can be used to implement USB to SIR adapter, allowing a PC to communicate with IrDA peripheral... Example: USB RS adapter USB X PN-S U$ MF-SMDF00 D- +V C C 0µ 0n +V Q M C C p p D- IC VCC V RTS# # XI DCD# XO RI# DSR# # D- R 0 RTS DCD RI DSR ICP VCC 0 C 0µ C 00n 00n C RTS DCD RI DSR 0 IC C+ C+ C- C- TIN TIN TIN TIN ROUT ROUT ROUT ROUT ROUT EN TOUT TOUT TOUT TOUT RIN RIN RIN RIN RIN MAXECWI V+ V- SHDN C 00n H_ H_ H_RTS H_ H_ H_DCD H_RI H_DSR The schematic above implements a USB to RS adapter based on CH0G and external level adapter MAX. When implementing this regulator-less V board, place capacitor C close to the V pin. C 00n H_DCD H_RX H_TX H_ X H_DSR H_RTS H_ H_RI Page of WCH CH0G Datasheet

6 WCH CH0G Datasheet.. Example: Optically isolated USB to UART adapter +V USB X PN-S U$ MF-SMDF00 D- C 0µ C p C 0n Q M C p D- IC VCC V RTS# # XI DCD# XO RI# DSR# # D- R 0 RTS DCD RI DSR R 0k R 0 R 0k R 0 PC OK PC OK PC OK PC OK R 0 R 0k R 0 R 0k VDD IO ICG$ LVCG0DBV ICG$ LVCG0DBV This adapter provides optically isolated inputs and outputs with PC optoisolators. Respect the isolation border when laying out the board, and if possible, cut slots under the optoisolators. The two LVCG0 is optional, but helpful when the input pins cannot source too many current. DNP C VDD IO JP VCC TXO RXI VDD C ICG$ ICG$ 0µ IO VCC VCC Page of WCH CH0G Datasheet