Microcomputer Components

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1 Microcomputer Components 8-Bit CMOS Microcontroller C50 Data Sheet 04.97

2 Data Sheet Revision History : Previous Releases :.92,.93, 08.94, 08.95, 0.96 Page (previous version) general , 9, Page (new version) , 9, , 44 Subjects (changes since last revision) C50G-E OTP version included Ordering information resorted and C50G-E types added Table with literature hints added Pin configuration logic symbol for pins EA/Vpp and ALE/PROG updated Pin description for ALE/PROG and EA/Vpp completed Port, 3, 2 pin description: bidirectional replaced by quasibidirectional Block diagram updated for C50G-E New design of register (PSW) description Memory organization added Actualized design of the SFR tables Reset value of T2CON corrected Description for the C50-E OTP version added DC characteristics for C50-E added Timing External Clock Drive now behind Data Memory Cycle AC characteristics for C50-E added Edition Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 854 München Siemens AG 997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems 2 with the express written approval of the Semiconductor Group of Siemens AG. A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

3 8-Bit CMOS Microcontroller C50 Preliminary Fully compatible to standard 805 microcontroller Versions for 2/24/40 MHz operating frequency Program memory : completely external (C50-L) 8K 8 ROM (C50-R) 8K 8 OTP memory (C50-E) RAM Four 8-bit ports Three 6-bit timers / counters (timer 2 with up/down counter feature) USART Six interrupt sources, two priority levels Power saving modes Quick Pulse programming algorithm (C50-E only) 2-Level program memory lock (C50-E only) P-DIP-40, P-LCC-44, and P-MQFP-44 package Temperature ranges : SAB-C50 T A : 0 C to 70 C SAF-C50 T A : 40 C to 85 C Power Saving Modes RAM 256 x 8 Port 0 Ι/O T0 Port Ι/O T2 CPU USART T Port 2 Ι/O 8K x 8 ROM (C50-R) 8K x 8 OTP (C50-E) Port 3 Ι/O MCA03238 Figure C50G Functional Units Semiconductor Group

4 The C50-R contains a non-volatile 8K 8 read-only program memory, a volatile read/ write data memory, four ports, three 6-bit timers counters, a seven source, two priority level interrupt structure and a serial port. The C50-L is identical, except that it lacks the program memory on chip. The C50-E contains a one-time programmable (OTP) program memory on chip. The term C50 refers to all versions within this specification unless otherwise noted. Further, the term C50 refers to all versions which are available in the different temperature ranges, marked with SAB-C50... or SAF-C Ordering Information Type Ordering Code Package Description (8-Bit CMOS microcontroller) SAB-C50G-LN SAB-C50G-LP SAB-C50G-LM SAB-C50G-L24N SAB-C50G-L24P SAB-C50G-L24M SAB-C50G-L40N SAB-C50G-L40P SAB-C50G-L40M SAF-C50G-L24N SAF-C50G-L24P SAB-C50G-RN SAB-C50G-RP SAB-C50G-RM SAB-C50G-R24N SAB-C50G-R24P SAB-C50G-R24M SAB-C50G-R40N SAB-C50G-R40P SAB-C50G-R40M SAF-C50G-R24N SAF-C50G-R24P SAB-C50G-EN SAB-C50G-EP SAF-C50G-EN SAF-C50G-EP SAB-C50G-E24N SAB-C50G-E24P SAF-C50G-E24N SAF-C50G-E24P Q6720-C969 Q6720-C968 Q6727-C970 Q6720-C00 Q6720-C999 Q6727-C04 Q6720-C002 Q6720-C000 Q6727-C009 Q6720-C0 Q6720-C00 Q6720-DXXX Q6720-DXXX Q6727-DXXX Q6720-DXXX Q6720-DXXX Q6727-DXXX Q6720-DXXX Q6720-DXXX Q6727-DXXX Q6720-DXXX Q6720-DXXX Q6720-C054 Q6720-C056 Q6720-C2002 Q6720-C2003 Q6720-C2005 Q6720-C2006 Q6720-C2008 Q6720-C2009 P-LCC-44 P-DIP-40 P-MQFP-44 P-LCC-44 P-DIP-40 P-MQFP-44 P-LCC-44 P-DIP-40 P-MQFP-44 P-LCC-44 P-MQFP-44 P-LCC-44 P-DIP-40 P-MQFP-44 P-LCC-44 P-DIP-40 P-MQFP-44 P-LCC-44 P-DIP-40 P-MQFP-44 P-LCC-44 P-DIP-40 P-LCC-44 P-DIP-40 P-LCC-44 P-DIP-40 P-LCC-44 P-DIP-40 P-LCC-44 P-DIP-40 for external memory (2 MHz) for external memory (24 MHz) for external memory (40 MHz) for external memory (24 MHz) ext. temp. 40 C to 85 C with mask-programmable ROM (2 MHz) with mask-programmable ROM (24 MHz) with mask-programmable ROM (40 MHz) with mask-programmable ROM (24 MHz) ext. temp. 40 C to 85 C with OTP memory (2 MHz) with OTP memory (2 MHz)) ext. temp. 40 C to 85 C with OTP memory (24 MHz) with OTP memory (24 MHz)) ext. temp. 40 C to 85 C Semiconductor Group

5 Note: Versions for extended temperature range 40 C to 0 C (SAH-C50G) on request. The ordering number of ROM types (DXXX extensions) is defined after program release (verification) of the customer. Additional Literature For further information about the C50 the following literature is available : Title C50 8-Bit CMOS Microcontroller User s Manual C500 Microcontroller Family Architecture and Instruction Set User s Manual C500 Microcontroller Family - Pocket Guide Ordering Number B58-H6723-X-X-7600 B58-H6987-X-X-7600 B58-H6986-X-X-7600 P.4 P.3 P.2 P./T2EX P.0/T2 N.C V CC P0.0/AD0 P0./AD P0.2/AD2 P0.3/AD P.5 P.6 P.7 RESET RxD/P3.0 N.C. TxD/P3. INT0/P3.2 INT/P3.3 T0/P3.4 T/P C P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/ N.C. V PP ALE/PROG PSEN P2.7/A5 P2.6/A4 P2.5/A WR/P3.6 RD/P3.7 XTAL2 XTAL V SS N.C. P2.0/A8 P2./A9 P2.2/A0 P2.3/A P2.4/A2 MCP0324 Figure 2 Pin Configuration P-LCC-44 Package (Top view) Semiconductor Group

6 T2/P.0 40 V CC T2EX/P P0.0/AD0 P P0./AD P P0.2/AD2 P P0.3/AD3 P P0.4/AD4 P P0.5/AD5 P P0.6/AD6 RESET 9 32 P0.7/AD7 RxD/P3.0 TxD/P3. 0 C EA/ VPP ALE/PROG INT0/P PSEN INT/P P2.7/A5 T0/P P2.6/A4 T/P P2.5/A3 WR/P P2.4/A2 RD/P P2.3/A XTAL P2.2/A0 XTAL 9 22 P2./A9 V SS 20 2 P2.0/A8 MCP0325 Figure 3 Pin Configuration P-DIP-40 Package (top view) Semiconductor Group

7 P0.4/AD4 P0.5/AD5 P0.6/AD6 P.5 P.6 P.7 RESET P0.7/AD7 EA/ V PP N.C. ALE/PROG PSEN P2.7/A5 P2.6/A4 P0.3/AD P2.4/A2 P0.2/AD P2.3/A P0./AD P2.2/A0 P0.0/AD P2./A9 V CC 38 8 P2.0/A8 N.C. 39 C50 7 N.C. P.0/T V SS P./T2EX 4 5 XTAL P XTAL2 P RD/P3.7 P WR/P3.6 RxD/P3.0 N.C. TxD/P3. INT0/P3.2 INT/P3.3 T0/P3.4 T/P3.5 P2.5/A3 MCP0326 Figure 4 Pin Configuration P-MQFP-44 Package (top view) VCC V SS XTAL XTAL2 RESET EA /V PP ALE/PROG PSEN C50 Port 0 8-Bit Digital Ι /O Port 8-Bit Digital Ι /O Port 2 8-Bit Digital Ι /O Port 3 8-Bit Digital Ι /O MCL0327 Figure 5 Logic Symbol Semiconductor Group

8 Table Pin Definitions and Functions Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 P.0 P *) I = Input O = Output , 3, 40 4 I/O Port is a quasi-bidirectional I/O port with internal pull-up resistors. Port pins that have s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. Port also contains the timer 2 pins as secondary function. The output latch corresponding to a secondary function must be pro-grammed to a one () for that function to operate. The secondary functions are assigned to the pins of port, as follows: P.0 T2 Input to counter 2 P. T2EX Capture - Reload trigger of timer 2 / Up-Down count Semiconductor Group

9 Table Pin Definitions and Functions (cont d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 P3.0 P3.7, 3 9 *) I = Input O = Output , I/O Port 3 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 3 pins that have s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. Port 3 also contains the interrupt, timer, serial port 0 and external memory strobe pins which are used by various options. The output latch corresponding to a secondary function must be programmed to a one () for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 R D receiver data input (asynchronous) or data input output (synchronous) of serial interface 0 P3. T D transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 P3.2 INT0 interrupt 0 input/timer 0 gate control P3.3 INT interrupt input/timer gate control P3.4 T0 counter 0 input P3.5 T counter input P3.6 WR the write control signal latches the data byte from port 0 into the external data memory P3.7 RD the read control signal enables the external data memory to port 0 Semiconductor Group

10 Table Pin Definitions and Functions (cont d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 XTAL XTAL2 Output of the inverting oscillator amplifier. XTAL XTAL Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed. P2.0 P I/O Port 2 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 2 pins that have s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 6-bit addresses In this application it uses strong internal pull-up resistors when issuing s. During accesses to external data memory that use 8-bit addresses port 2 issues the contents of the P2 special function register. *) I = Input O = Output Semiconductor Group

11 Table Pin Definitions and Functions (cont d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 PSEN O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. Remains high during internal program execution. RESET I RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to V SS permits power-on reset using only an external capacitor to V CC. ALE/PROG I/O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. For the C50-E this pin is also the program pulse input (PROG) during OTP memory programming. EA/V PP I External Access Enable When held at high level, instructions are fetched from the internal ROM (C50-R and C50-E) when the PC is less than 2000 H. When held at low level, the C50 fetches all instructions from external program memory. For the C50-L this pin must be tied low. This pin also receives the programming supply voltage V PP during OTP memory programming (C50-E) only). *) I = Input O = Output Semiconductor Group

12 Table Pin Definitions and Functions (cont d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 P0.0 P I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-up resistors when issuing s. Port 0 also outputs the code bytes during program verification in the C50-R and C50-E. External pull-up resistors are required during program verification. V SS Circuit ground potential V CC Supply terminal for all operating modes N.C., 2, 23, 34 *) I = Input O = Output 6, 7, 28, 39 No connection Semiconductor Group

13 Functional Description The C50 is fully compatible to the standard 805 microcontroller family. It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational characteristics of the 805microcontroller family, the C50 incorporates some enhancements in the timer 2 unit. Figure 6 shows a block diagram of the C50. V CC V SS XTAL XTAL2 C50 OSC & Timing RAM 256 x 8 C50-R : ROM C50-E : OTP 8K x 8 RESET CPU ALE/PROG PSEN Timer 0 Port 0 Port 0 8-Bit Digit. Ι /O EA/ V PP Timer Port Port 8-Bit Digit. Ι /O Timer 2 Interrupt Unit Port 2 Port 2 8-Bit Digit. Ι /O Serial Channel (USART) Port 3 Port 3 8-Bit Digit. Ι /O MCB0329 Figure 6 Block Diagram of the C50 Semiconductor Group

14 CPU The C50 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 4 % two-byte, and 5% three-byte instructions. With a 2 MHz crystal, 58% of the instructions are executed in.0 µs 24 MHz: 500 ns, 40 MHz : 300 ns). Special Function Register PSW (Address D0 H ) Reset Value : 00 H Bit No. MSB LSB D7 H D6 H D5 H D4 H D3 H D2 H D H D0 H D0 H CY AC F0 RS RS0 OV F P PSW Bit CY AC F0 RS RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS RS0 Function 0 0 Bank 0 selected, data address 00 H -07 H 0 Bank selected, data address 08 H -0F H 0 Bank 2 selected, data address 0 H -7 H Bank 3 selected, data address 8 H -F H OV F P Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. Semiconductor Group

15 Memory Organization The C50 CPU manipulates data and operands in the following four address spaces: up to 64 Kbyte of internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 28 byte special function register area Figure 7 illustrates the memory address spaces of the C50. FFFF H FFFF H External External 2000 H Indirect Address Internal RAM FF H 80 H Direct Address Special Function Register FF H 80 H Internal (EA = ) External (EA = 0) FFF H 0000 H 0000 H Internal RAM 7F H 00 H "Code Space" "Data Space" "Internal Data Space" MCD03224 Figure 7 C50 Memory Map Semiconductor Group

16 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 27 special function registers (SFRs) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80 H, 88 H, 90 H, 98 H,..., F8 H, FF H ) are bitaddressable. The SFRs of the C50 are listed in table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C50. Table 3 illustrates the contents of the SFRs in numeric order of their addresses. Semiconductor Group

17 Table 2 Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU Interrupt System Ports Serial Channel Timer 0 / Timer Timer 2 Pow. Sav. Modes ACC B DPH DPL PSW SP IE IP P0 P P2 P3 PCON 2) SBUF SCON TCON TH0 TH TL0 TL TMOD T2CON T2MOD RC2H RC2L TH2 TL2 Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Interrupt Enable Register Interrupt Priority Register Port 0 Port Port 2 Port 3 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Timer 0/ Control Register Timer 0, High Byte Timer, High Byte Timer 0, Low Byte Timer, Low Byte Timer Mode Register Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture Register, High Byte Timer 2 Reload/Capture Register, Low Byt Timer 2 High Byte Timer 2 Low Byte E0 H ) F0 H ) 83 H 82 H D0 H ) 8 H A8 H ) B8 H ) 80 H ) 90 H ) A0 H ) B0 H ) 87 H 99 H 98 H ) 88 H ) 8C H 8D H 8A H 8B H 89 H C8 H ) C9 H CB H CA H CD H CC H 00 H 00 H 00 H 00 H 00 H 07 H 0X ) B XX ) B FF H FF H FF H FF H 0XXX0000 B 3) XX H 3) 00 H 00 H 00 H 00 H 00 H 00 H 00 H 00 H XXXXXXX0 B 3) 00 H 00 H 00 H 00 H PCON 2) Power Control Register 87 H 0XXX0000 B 3) ) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is undefined and the location is reserved Semiconductor Group

18 Table 3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content after Reset ) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit ) H P0 FF H H SP 07 H H DPL 00 H H DPH 00 H H PCON 0XXX B SMOD GF GF0 PDE IDLE 88 2) H TCON 00 H TF TR TF0 TR0 IE IT IE0 IT0 89 H TMOD 00 H GATE C/T M M0 GATE C/T M M0 8A H TL0 00 H B H TL 00 H C H TH0 00 H D H TH 00 H H 2) P FF H ) H SCON 00 H SM0 SM SM2 REN TB8 RB8 TI RI 99 H SBUF XX H A0 H 2) P2 FF H A8 H 2) IE 0X B EA ET2 ES ET EX ET0 EX0 B0 H 2) P3 FF H RD WR T T0 INT INT0 TxD RxD B8 H 2) IP XX B PT2 PS PT PX PT0 PX0 C8 H 2) T2CON 00 H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 DCEN C9 H T2MOD XXXX- XXX0 B CA H RC2L 00 H CB H RC2H 00 H CC H TL2 00 H CD H TH2 00 H D0 H 2) PSW 00 H CY AC F0 RS RS0 OV F P E0 H 2) ACC 00 H F0 H 2) B 00 H ) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group

19 _< C50 Timer / Counter 0 and Timer/counter 0 and can be used in four operating modes as listed in table 4. Table 4 Timer/Counter 0 and Operating Modes Mode Description TMOD Input Clock Gate C/T M M0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler X X 0 0 f OSC / 2 32 f OSC / bit timer/counter X X f OSC / 2 f OSC / bit timer/counter with 8-bit autoreload 3 Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer stops X X 0 0 f OSC / 2 f OSC / 24 X X f OSC / 2 f OSC / 24 In the timer function (C/T = 0 ) the register is incremented every machine cycle. Therefore the count rate is f OSC /2. In the counter function the register is incremented in response to a -to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T). Since it takes two machine cycles to detect a falling edge the max. count rate is f OSC /24. External inputs INTO and INT (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 8 illustrates the input clock logic. f OSC 2 f OSC /2 0 P3.4/T0 P3.5/T max f OSC/24 C/T TMOD Timer 0/ Input Clock TR 0/ TCON & Control P3.2/INT0 P3.3/INT Gate TMOD = MCS0768 Figure 8 Timer/Counter 0 and Input Clock Logic Semiconductor Group

20 Timer 2 Timer 2 is a 6-bit timer/counter with an up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.). It has three operating modes as shown in table 5. Table 5 Timer/Counter 2 Operating Modes Mode 6-bit Autoreload 6-bit Capture Baud Rate Generator R CLK or T CLK T2CON CP/ RL X X TR2 T2MOD DCEN 0 0 X X X X T2CON EXEN 0 X X 0 0 P./ T2EX Remarks X 0 X X reload upon overflow reload trigger (falling edge) Down counting Up counting 6 bit Timer/ Counter (only up-counting) capture TH2, TL2 RC2H, RC2L no overflow interrupt request (TF2) extra external interrupt ( Timer 2 ) Input Clock internal f OSC /2 f OSC /2 f OSC /2 external (P.0/T2) max f OSC /24 max f OSC /24 max f OSC /24 off X X 0 X X X Timer 2 stops Note: = falling edge Semiconductor Group

21 Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the formulas given in table 7. Table 6 USART Operating Modes Mode SCON Baudrate Description SM0 SM f OSC /2 Serial data enters and exits through R D. T D outputs the shift clock. 8-bit are transmitted/received (LSB first) 0 Timer /2 overflow rate 8-bit UART 0 bits are transmitted (through T D) or received (R D) 2 0 f OSC /32 or f OSC /64 9-bit UART bits are transmitted (T D) or received (R D) 3 Timer /2 overflow rate 9-bit UART Like mode 2 except the variable baud rate Table 7 Formulas for Calculating Baudrates Baud Rate Interface Mode derived from Oscillator 0 2 Timer (6-bit timer) (8-bit timer with 8-bit autoreload),3,3 Baudrate f OSC /2 (2 SMOD f OSC ) / 64 (2 SMOD timer overflow rate) /32 (2 SMOD f OSC ) / (32 2 (256-TH)) Timer 2,3 f OSC / (32 (65536-(RC2H, RC2L)) Semiconductor Group

22 _< _< C50 Interrupt System The C50 provides 6 interrupt sources with two priority levels. Figure 9 gives a general overview of the interrupt sources and illustrates the request and control flags. High Priority Timer 0 Overflow TF0 TCON.5 ET0 IE. PT0 IP. Low Priority Timer Overflow TCON.0 TF TCON.7 ET IE.3 PT IP.3 P./ T2EX Timer 2 Overflow EXEN2 T2CON.3 USART TF2 T2CON.7 EXF2 T2CON.6 RI SCON.0 TI SCON. ET2 IE.5 ES IE.4 PT2 IP.5 PS IP.4 P3.2/ INT0 IT0 TCON.0 IE0 TCON. EX0 IE.0 PX0 IP.0 P3.3/ INT IT TCON.2 IE TCON.3 EX IE.2 EA IE.7 PX IP.2 MCS0783 Figure 9 Interrupt Request Sources Semiconductor Group

23 Table 8 Interrupt Sources and their Corresponding Interrupt Vectors Source (Request Flags) Vector Vector Address IE0 TF0 IE TF RI + TI TF2 + EXF2 External interrupt 0 Timer 0 interrupt External interrupt Timer interrupt Serial port interrupt Timer 2 interrupt 0003 H 000B H 003 H 00B H 0023 H 002B H A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another lowpriority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 9. Table 9 Interrupt Priority-Within-Level External Interrupt 0, Timer 0 Interrupt, External Interrupt, Timer Interrupt, Serial Channel, Timer 2 Interrupt, Interrupt Source IE0 TF0 IE TF RI + TI TF2 + EXF2 Priority High Low Semiconductor Group

24 Power Saving Modes Two power down modes are available, the Idle Mode and Power Down Mode. The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 0 gives a general overview of the power saving modes. Table 0 Power Saving Modes Overview Mode Entering Instruction Example Leaving by Idle mode ORL PCON, #0H enabled interrupt Hardware Reset Power-Down Mode Remarks CPU is gated off CPU status registers maintain their data. Peripherals are active ORL PCON, #02H Hardware Reset Oscillator is stopped, contents of on-chip RAM and SFR s are maintained (leaving Power Down Mode means redefinition of SFR contents). In the Power Down mode of operation, V CC can be reduced to minimize power consumption. It must be ensured, however, that V CC is not reduced before the Power Down mode is invoked, and that V CC is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down mode also restarts the oscillator. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). Semiconductor Group

25 OTP Operation The C50-E is programmed by usng a modified Quick-Pulse Programming TM ) algorithm. It differs from older methods in the value used for V PP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The C50-E contains two signature bytes that can be read and used by a programming system to identify the device. The signature bytes identify the manufacturer of the device. Table shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in figures 0 to 2. Table OTP Programming Modes Mode RESET PSEN ALE/ EA/V PP P2.7 P2.6 P3.7 P3.6 PROG Read signature Program code data 0 0 V PP 0 Verify code data Progam encryption table 0 0 V PP 0 0 Program security bit 0 0 V PP Program security bit V PP 0 0 Notes :. 0 = valid low for that pin, = valid high for that pin. 2. V PP = 2.75 V ± 0.25V 3. V CC = 5 V ± 0% during programming and verification. 4. ALE/PROG receives 25 programming pulses while V PP is held at 2.75 V. Each programming pulse is low for 00 µs (± 0 µs) and high for a minimum of 0 µs. ) Quick-Pulse Programming TM is a trademark phrase of Intel Corporation Semiconductor Group

26 Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in figure 0. Note that the C50- E is running with a 4 to 6 MHz oscillator The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the OTP memory location to be programmed is applied to port and 2 as shown in figure 0. The code byte to be programmed into that location is applied to port 0. RESET, PSEN and pins of port 2 and 3 specified in table are held at the Program code data levels. The ALE/ PROG signal is pulsed low 25 times as shown in figure. For programming of the encryption table, the 25 pulse programming sequence must be repeated for addresses 0 through F H, using the Program encrytion table levels. After the encryption table is programmed, verification cycles will produce only encrypted data. For programming of the security bits, the 25 pulse programming sequence must be repeat using the Program security bit levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/V PP pin must not be allowed to go above the maximum specified V PP level. for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The V PP source should be well regulated and free of glitches and overshoots. Program Verification If security bit 2 has not been programmed, the on-chip OTP program memory can be read out for program verification. The address of the OTP program memory locations to be read is applied to ports and 2 as shown in figure 2. The other pins are held at the Verify code data levels indicated in table. The contents of the address location will be emitted on port 0. External pullups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the SIgnature Bytes The signature bytes are read by the same procedure as a normal verification of loctions 30 H and 3 H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are : 30 H = E0 H indicates manufacturer 3 H = 7 H indicates C50-E Semiconductor Group

27 +5 V A0 - A7 Port RESET P3.6 P3.7 XTAL2 C50-E V CC Port 0 EA/V PP ALE/PROG PSEN Programming Data V 25 x 00 µ s Low Pulses MHz P2.7 XTAL P2.6 0 V SS P2.0 - P2.4 A8 - A2 MCS03232 Figure 0 C50-E OTP Memory Programming Configuration 25 Pulses ALE/PROG ALE/PROG 0 0 µ s min. µ µ MCT03234 Figure C50-E ALE/PROG Waveform Semiconductor Group

28 +5 V A0 - A7 Port V CC RESET C50-E 0 k Ω P3.6 P3.7 XTAL2 Port 0 EA/V PP ALE/PROG Programming Data 4-6 MHz PSEN P Enable XTAL P2.6 P2.0 - P2.4 0 A8 - A2 V SS MCS03235 Figure 2 C50-E OTP Memory Verification Semiconductor Group

29 Absolute Maximum Ratings Ambient temperature under bias (T A ) to 85 C Storage temperature (T stg ) C to 50 C Voltage on V CC pins with respect to ground (V SS ) V to 6.5 V Voltage on any pin with respect to ground (V SS ) V to V CC +0.5 V Input current on any pin during overload condition... 0 ma to 0 ma Absolute sum of all input currents during overload condition... I 00 ma I Power dissipation... TBD Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (V IN > V CC or V IN < V SS ) the Voltage on V CC pins with respect to ground (V SS ) must not exceed the values defined by the absolute maximum ratings. Semiconductor Group

30 DC Characteristics for C50-L / C50-R V CC = 5 V + 0 %, 5 %; V SS = 0 V; T A = 0 C to 70 C for the SAB-C50 T A = 40 C to 85 C for the SAF-C50 Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage (except EA, V IL V CC 0. V RESET) Input low voltage (EA) V IL V CC 0.3 V Input low voltage (RESET) V IL V CC + 0. V Input high voltage (except V IH 0.2 V CC V CC V XTAL, EA, RESET) Input high voltage to XTAL V IH 0.7 V CC V CC V Input high voltage to EA, V IH V CC V CC V RESET Output low voltage V OL 0.45 V I OL =.6 ma ) (ports, 2, 3) Output low voltage (port 0, ALE, PSEN) V OL 0.45 V I OL = 3.2 ma ) Output high voltage (ports, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports, 2, 3) Logical -to-0 transition current (ports, 2, 3) Input leakage current (port 0, EA) Notes see page 32. V OH V CC V OH V CC V I OH = 80 µa, I OH = 0 µa V I OH = 800 µa 2), I OH = 80 µa 2) I IL 0 50 µa V IN = 0.45 V I TL µa V IN = 2 V I LI ± µa 0.45 < V IN < V CC Pin capacitance C IO 0 pf f C = MHz, T A = 25 C Power supply current: Active mode, 2 MHz 7) Idle mode, 2 MHz 7) Active mode, 24 MHz 7) Idle mode, 24 MHz 7) Active mode, 40 MHz 7) Idle mode, 40 MHz 7) Power Down Mode I CC I CC I CC I CC I CC I CC I PD ma ma ma ma ma ma µa V CC = 5 V, 4) V CC = 5 V, 5) V CC = 5 V, 4) V CC = 5 V, 5) V CC = 5 V, 4) V CC = 5 V, 5) V CC = V 3) Semiconductor Group

31 DC Characteristics for C50-E V CC = 5 V + 0 %, 5 %; V SS = 0 V; T A = 0 C to 70 C for the SAB-C50 T A = 40 C to 85 C for the SAF-C50 Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage (except V IL V CC 0. V EA/V PP, RESET) Input low voltage (EA/V PP ) V IL V CC 0. V Input low voltage (RESET) V IL V CC + 0. V Input high voltage (except V IH 0.2 V CC V CC V XTAL, EA/V PP, RESET) Input high voltage to XTAL V IH 0.7 V CC V CC V Input high voltage to EA/V PP, V IH V CC V CC V RESET Output low voltage V OL 0.45 V I OL =.6 ma ) (ports, 2, 3) Output low voltage (port 0, ALE/PROG, PSEN) V OL 0.45 V I OL = 3.2 ma ) Output high voltage (ports, 2, 3) Output high voltage (port 0 in external bus mode, ALE/PROG, PSEN) Logic 0 input current (ports, 2, 3) Logical -to-0 transition current (ports, 2, 3) Input leakage current (port 0, EA/V PP ) Notes see next page. V OH V CC V OH V CC V I OH = 80 µa, I OH = 0 µa V I OH = 800 µa 2), I OH = 80 µa 2) I IL 0 50 µa V IN = 0.45 V I TL µa V IN = 2 V I LI ± µa 0.45 < V IN < V CC Pin capacitance C IO 0 pf f C = MHz, T A = 25 C Power supply current: Active mode, 2 MHz 7) Idle mode, 2 MHz 7) Active mode, 24 MHz 7) Idle mode, 24 MHz 7) Power Down Mode I CC I CC I CC I CC I PD ma ma ma ma µa V CC = 5 V, 4) V CC = 5 V, 5) V CC = 5 V, 4) V CC = 5 V, 5) V CC = V 3) Semiconductor Group

32 Notes: ) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V OL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make -to-0 transitions during bus operation. In the worst case (capacitive loading > 00 pf), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the V OH on ALE and PSEN to momentarily fall bellow the 0.9 V CC specification when the address lines are stabilizing. 3) I PD (Power Down Mode) is measured under following conditions: EA = Port0 = V CC ; RESET = V SS ; XTAL2 = N.C.; XTAL = V SS ; all other pins are disconnected. 4) I CC (active mode) is measured with: XTAL driven with t CLCH, t CHCL = 5 ns, V IL = V SS V, V IH = V CC 0.5 V; XTAL2 = N.C.; EA = Port0 = RESET= V CC ; all other pins are disconnected. I CC would be slightly higher if a crystal oscillator is used (appr. ma). 5) I CC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL driven with t CLCH, t CHCL = 5 ns, V IL = V SS V, V IH = V CC 0.5 V; XTAL2 = N.C.; RESET = EA = V SS ; Port0 = V CC ; all other pins are disconnected; 7) I CC max at other frequencies is given by: active mode: I CC =.27 x f OSC idle mode: I CC = 0.28 x f OSC +.45 (C50-L and C50-R only) where f OSC is the oscillator frequency in MHz. I CC values are given in ma and measured at V CC = 5 V. Semiconductor Group

33 AC Characteristics for C50-L / C50-R / C50-E V CC = 5 V + 0 %, 5 %; V SS = 0 V T A = 0 C to 70 C for the SAB-C50 T A = 40 C to 85 C for the SAF-C50 (C L for port 0, ALE and PSEN outputs = 00 pf; C L for all other outputs = 80 pf) Program Memory Characteristics Parameter Symbol Limit Values Unit 2 MHz Clock Variable Clock /t CLCL = 3.5 MHz to 2 MHz min. max. min. max. ALE pulse width t LHLL 27 2t CLCL 40 ns Address setup to ALE t AVLL 43 t CLCL 40 ns Address hold after ALE t LLAX 30 t CLCL 53 ns ALE low to valid instr in t LLIV 233 4t CLCL 00 ns ALE to PSEN t LLPL 58 t CLCL 25 ns PSEN pulse width t PLPH 25 3t CLCL 35 ns PSEN to valid instr in t PLIV 50 3t CLCL 00 ns Input instruction hold after PSEN t PXIX 0 0 ns Input instruction float after PSEN t *) PXIZ 63 t CLCL 20 ns Address valid after PSEN *) t PXAV 75 t CLCL 8 ns Address to valid instr in t AVIV 302 5t CLCL 5 ns Address float to PSEN t AZPL 0 0 ns *) Interfacing the C50 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Semiconductor Group

34 AC Characteristics for C50-L / C50-R / C50-E (cont d) External Data Memory Characteristics Parameter Symbol Limit Values Unit 2 MHz Clock Variable Clock /t CLCL = 3.5 MHz to 2 MHz min. max. min. max. RD pulse width t RLRH 400 6t CLCL 00 ns WR pulse width t WLWH 400 6t CLCL 00 ns Address hold after ALE t LLAX2 30 t CLCL 53 ns RD to valid data in t RLDV 252 5t CLCL 65 ns Data hold after RD t RHDX 0 0 ns Data float after RD t RHDZ 97 2t CLCL 70 ns ALE to valid data in t LLDV 57 8t CLCL 50 ns Address to valid data in t AVDV 585 9t CLCL 65 ns ALE to WR or RD t LLWL t CLCL 50 3t CLCL + 50 ns Address valid to WR or RD t AVWL 203 4t CLCL 30 ns WR or RD high to ALE high t WHLH t CLCL 40 t CLCL + 40 ns Data valid to WR transition t QVWX 33 t CLCL 50 ns Data setup before WR t QVWH 433 7t CLCL 50 ns Data hold after WR t WHQX 33 t CLCL 50 ns Address float after RD t RLAZ 0 0 ns External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 2 MHz min. max. Oscillator period t CLCL ns High time t CHCX 20 t CLCL t CLCX ns Low time t CLCX 20 t CLCL t CHCX ns Rise time t CLCH 20 ns Fall time t CHCL 20 ns Semiconductor Group

35 AC Characteristics for C50-L24 / C50-R24 / C50-E24 V CC = 5 V + 0 %, 5 %; V SS = 0 V T A = 0 C to 70 C for the SAB-C50 T A = 40 C to 85 C for the SAF-C50 (C L for port 0, ALE and PSEN outputs = 00 pf; C L for all other outputs = 80 pf) Program Memory Characteristics Parameter Symbol Limit Values Unit 24 MHz Clock Variable Clock /t CLCL = 3.5 MHz to 24 MHz min. max. min. max. ALE pulse width t LHLL 43 2t CLCL 40 ns Address setup to ALE t AVLL 7 t CLCL 25 ns Address hold after ALE t LLAX 7 t CLCL 25 ns ALE low to valid instr in t LLIV 80 4t CLCL 87 ns ALE to PSEN t LLPL 22 t CLCL 20 ns PSEN pulse width t PLPH 95 3t CLCL 30 ns PSEN to valid instr in t PLIV 60 3t CLCL 65 ns Input instruction hold after PSEN t PXIX 0 0 ns Input instruction float after PSEN t *) PXIZ 32 t CLCL 0 ns Address valid after PSEN *) t PXAV 37 t CLCL 5 ns Address to valid instr in t AVIV 48 5t CLCL 60 ns Address float to PSEN t AZPL 0 0 ns *) Interfacing the C50 to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Semiconductor Group

36 AC Characteristics for C50-L24 / C50-R24 / C50-E24 (cont d) External Data Memory Characteristics Parameter Symbol Limit Values Unit 24 MHz Clock Variable Clock /t CLCL = 3.5 MHz to 24 MHz min. max. min. max. RD pulse width t RLRH 80 6t CLCL 70 ns WR pulse width t WLWH 80 6t CLCL 70 ns Address hold after ALE t LLAX2 5 t CLCL 27 ns RD to valid data in t RLDV 8 5t CLCL 90 ns Data hold after RD t RHDX 0 0 ns Data float after RD t RHDZ 63 2t CLCL 20 ns ALE to valid data in t LLDV 200 8t CLCL 33 ns Address to valid data in t AVDV 220 9t CLCL 55 ns ALE to WR or RD t LLWL t CLCL 50 3t CLCL + 50 ns Address valid to WR or RD t AVWL 67 4t CLCL 97 ns WR or RD high to ALE high t WHLH 7 67 t CLCL 25 t CLCL + 25 ns Data valid to WR transition t QVWX 5 t CLCL 37 ns Data setup before WR t QVWH 70 7t CLCL 22 ns Data hold after WR t WHQX 5 t CLCL 27 ns Address float after RD t RLAZ 0 0 ns External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 24 MHz min. max. Oscillator period t CLCL ns High time t CHCX 2 t CLCL t CLCX ns Low time t CLCX 2 t CLCL t CHCX ns Rise time t CLCH 2 ns Fall time t CHCL 2 ns Semiconductor Group

37 AC Characteristics for C50-L40 / C50-R40 V CC = 5 V + 0 %, 5 %; V SS = 0 V T A = 0 C to 70 C for the SAB-C50 T A = 40 C to 85 C for the SAF-C50 (C L for port 0, ALE and PSEN outputs = 00 pf; C L for all other outputs = 80 pf) Program Memory Characteristics Parameter Symbol Limit Values Unit 40 MHz Clock Variable Clock /t CLCL = 3.5 MHz to 40 MHz min. max. min. max. ALE pulse width t LHLL 35 2 t CLCL 5 ns Address setup to ALE t AVLL 0 t CLCL 5 ns Address hold after ALE t LLAX 0 t CLCL 5 ns ALE low to valid instr in t LLIV 55 4 t CLCL 45 ns ALE to PSEN t LLPL 0 t CLCL 5 ns PSEN pulse width t PLPH 60 3 t CLCL 5 ns PSEN to valid instr in t PLIV 25 3 t CLCL 50 ns Input instruction hold after PSEN t PXIX 0 0 ns Input instruction float after PSEN t *) PXIZ 20 t CLCL 5 ns Address valid after PSEN *) t PXAV 20 t CLCL 5 ns Address to valid instr in t AVIV 65 5 t CLCL 60 ns Address float to PSEN t AZPL 5 5 ns *) Interfacing the C50 to devices with float times up to 25ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Semiconductor Group

38 AC Characteristics for C50-L40 / C50-R40 (cont d) External Data Memory Characteristics Parameter Symbol Limit Values Unit 40 MHz Clock Variable Clock /t CLCL = 3.5 MHz to 40 MHz min. max. min. max. RD pulse width t RLRH 20 6 t CLCL 30 ns WR pulse width t WLWH 20 6 t CLCL 30 ns Address hold after ALE t LLAX2 0 t CLCL 5 ns RD to valid data in t RLDV 75 5 t CLCL 50 ns Data hold after RD t RHDX 0 0 ns Data float after RD t RHDZ 38 2 t CLCL 2 ns ALE to valid data in t LLDV 50 8 t CLCL 50 ns Address to valid data in t AVDV 50 9 t CLCL 75 ns ALE to WR or RD t LLWL t CLCL 5 3 t CLCL + 5 ns Address valid to WR or RD t AVWL 70 4 t CLCL 30 ns WR or RD high to ALE high t WHLH 0 40 t CLCL 5 t CLCL + 5 ns Data valid to WR transition t QVWX 5 t CLCL 20 ns Data setup before WR t QVWH 25 7 t CLCL 50 ns Data hold after WR t WHQX 5 t CLCL 20 ns Address float after RD t RLAZ 0 0 ns External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 40 MHz min. max. Oscillator period t CLCL ns High time t CHCX 0 t CLCL t CLCX ns Low time t CLCX 0 t CLCL t CHCX ns Rise time t CLCH 0 ns Fall time t CHCL 0 ns Semiconductor Group

39 t LHLL ALE t AVLL t PLPH t LLPL t LLIV t PLIV PSEN t AZPL t LLAX t PXAV t PXIZ t PXIX Port 0 A0 - A7 Instr.IN A0 - A7 t AVIV Port 2 A8 - A5 A8 - A5 MCT00096 Figure 3 Program Memory Read Cycle Semiconductor Group

40 t WHLH ALE PSEN t LLDV t LLWL t RLRH RD t RLDV t AVLL t RHDZ t LLAX2 t RLAZ t RHDX Port 0 A0 - A7 from Ri or DPL Data IN A0 - A7 from PCL Instr. IN t AVWL t AVDV Port 2 P2.0 - P2.7 or A8 - A5 from DPH A8 - A5 from PCH MCT00097 Figure 4 Data Memory Read Cycle Semiconductor Group

41 t WHLH ALE PSEN t LLWL t WLWH WR t QVWX t AVLL t WHQX t LLAX2 t QVWH Port 0 A0 - A7 from Ri or DPL Data OUT A0 - A7 from PCL Instr.IN t AVWL Port 2 P2.0 - P2.7 or A8 - A5 from DPH A8 - A5 from PCH MCT00098 Figure 5 Data Memory Write Cycle t CLCL V CC - 0.5V 0.45V 0.7 V CC 0.2 V - 0. CC t CHCL t CLCX t CLCH t CHCX MCT00033 Figure 6 External Clock Drive at XTAL2 Semiconductor Group

42 ROM Verification Characteristics for C50-R ROM Verification Mode Parameter Symbol Limit Values Unit min. max. Address to valid data t AVQV 48t CLCL ns ENABLE to valid data t ELQV 48t CLCL ns Data float after ENABLE t EHQZ 0 48t CLCL ns Oscillator frequency /t CLCL 4 6 MHz P.0 - P.7 P2.0 - P2.4 Address t AVQV Port 0 Data OUT t ELQV t EHQZ P2.7 ENABLE MCT00049 Address: P.0 - P.7 = A0 - A7 P2.0 - P2.4 = A8 - A2 Data: P0.0 - P0.7 = D0 - D7 Inputs: P2.5 - P2.6, PSEN = ALE, EA = RESET = V SS V IH V SS Figure 7 ROM Verification Mode Semiconductor Group

43 OTP Programming and Verification Characteristics V CC = 5 V ± 0%, V SS = 0 V, T A = 2 C to + 27 C Parameter Symbol Limit Values Unit min. max. Programming supply voltage V PP V Programming supply current I PP 50 ma Oscillator frequency / t CLCL 4 6 MHz Address setup to ALE/PROG low t AVGL 48 t CLCL ns Address hold after ALE/PROG t GHAX 48 t CLCL ns Data setup to ALE/PROG low t DVGL 48 t CLCL ns Data hold after ALE/PROG t GHDX 48 t CLCL ns P2.7 (ENABLE) high to V PP t EHSH 48 t CLCL ns V PP setup to ALE/PROG low t SHGL 0 µs V PP hold after ALE/PROG low t GHSL 0 µs ALE/PROG width t GLGH 90 0 µs Address to data valid t AVQV 48 t CLCL ns ENABLE low to data valid t ELQV 48 t CLCL ns Data float after ENABLE t EHQZ 0 48 t CLCL ns ALE/PROG high to ALE/PROG low t GHGL 0 µs Semiconductor Group

44 P.0 - P.7 P2.0 - P2.4 Programming Address t AVQV Verification Address Port 0 Data Data t DVGL t AVGL t GHDX t GHAX ALE/PROG t GLGH t GHGL t SHGL t GHSL EA/ V PP Logic Logic 0 t EHSH t ELQV t EHQZ P2.7 ENABLE MCT03237 Figure 8 C50-E OTP Memory Program/Read Cycle Semiconductor Group

45 V CC -0.5 V 0.2 V CC +0.9 Test Points 0.45 V Figure 9 AC Testing: Input, Output Waveforms 0.2 V CC -0. MCT00039 AC Inputs during testing are driven at V CC 0.5 V for a logic and 0.45 V for a logic 0. Timing measurements are made at V IHmin for a logic and V ILmax for a logic V V Load V OH -0. V V Load Timing Reference Points V Load -0. V V OL +0. V Figure 20 AC Testing: Float Waveforms MCT00038 For timing purposes a port pin is no longer floating when a 00 mv change from load voltage occurs and begins to float when a 00 mv change from the loaded V OH / V OL level occurs. I OL / I OH ± 20 ma. Crystal Oscillator Mode Driving from External Source C MHz XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 8 M-QFP-44/Pin 4 N.C. XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 8 M-QFP-44/Pin 4 C C = 20 pf 0 pf (incl. stray capacitance) XTAL P-LCC-44/Pin 2 P-DIP-40/Pin 9 M-QFP-44/Pin 5 External Oscillator Signal XTAL P-LCC-44/Pin 2 P-DIP-40/Pin 9 M-QFP-44/Pin 5 MCS02452 Note: During programming and verification of the C50-E OTP memory a clock signal of 4-6 MHz must be applied to the device. Figure 2 Recommended Oscillator Circuits Semiconductor Group

46 Package Outlines Plastic Package, P-DIP-40 for C50G-L / C50G-R (Plastic Dual in-line Package) GPD05883 Figure 22 P-DIP-40 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book Package Information Dimensions in mm Semiconductor Group

47 Plastic Package, P-LCC-44 SMD for C50G-L / C50G-R / C50G-E (Plastic Leaded Chip-Carrier) GPL05882 Figure 23 P-LCC-44 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book Package Information SMD = Surface Mounted Device Dimensions in mm Semiconductor Group

48 Plastic Package, P-MQFP-44 SMD for C50G-L / C50G-R (Plastic Metric Quad Flat Package) GPM05957 Figure 24 P-MQFP-44 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book Package Information SMD = Surface Mounted Device Dimensions in mm Semiconductor Group