Super Companion Chip with Audio Visual Interface for Cell Processor

Transcription

1 Super Companion Chip with Audio Visual Interface for Cell Processor Takayuki Mihara 1, Hiroki Muroga 1, Hiroshi Doi 1, Tadashi Yabuta 1, Yoichiro Iwagami 1, Kenichi Ishii 1, Naohiko Okamoto 1, Kazuki Iwata 1, Yoshimasa Aoyama 1, Takeshi Takamiya 1, Naoki Sugawa 2 1. Toshiba Corporation 2. Toshiba Microelectronics Corporation 1 1

2 Outline Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

3 Motivation To provide software based digital consumer solution for Cell processor such as Digital TV, Audio Visual Server, etc. To establish GHz high bandwidth connection between Cell and ultra high speed peripherals on Super Companion Chip (SCC).

4 Requirements from Market - Multi Tasks Processing Simultaneously - Storage HDD HD-DVD Satellite SDTV PC Monitor Terrestrial CATV HDTV -Multi Recording -Time Shift Play -Multi Screen Streaming DTV Internet Web, Streaming Key Feature Real Time Audio Video Processing Home Network

5 Cell Processor Overview Cell Processor SPEs Power Processor Element (PPE) Synergistic Processor Element (SPE) Dual XDR DRAM channels Flexible I/O Interface Element Interconnect Bus SXU LS SXU LS SXU LS PPE SXU LS EIB L2 L1 PXU SXU LS SXU LS MIC XIO Dual XDR TM SXU SXU LS LS BEI FlexIO SCC

6 Features of Cell Processor Resource Management Capability Reserve Memory & I/O Bandwidth for up to four tasks. Isolation Facility Each SPE is isolatable from outside for flexible secure programming. Multi OS Support Run multiple OSs simultaneously. e.g. Linux + Real-time OS

7 Features of SCC For Real Time Processing SCC internal bus has the bandwidth reservation capability for the each resources. -TDM arbitration For Tight Security The HW random number generator and several kinds of HW Encryption/Decryption functions are implemented For Multi OS Support Every bus master module have the address space restriction mechanism. To prevent the IO resource conflict between OSs.

8 Outline Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

9 SCC I/O Category For versatile A/V system -DDR2 DRAM I/F for Video RAM. -Video output / Audio output. -Video input / Audio input. -Digital AV equipment connection I/F (IEEE1394). -Digital tuner I/F (TS I/F). For computer system For computer system -Standard PC I/F (PCI-Express,PCI,USB2.0). -High-speed Network I/F (Giga Bit Ethernet). -Storage device I/F (Parallel ATA).

10 A/V functions in SCC XDR-DRAM 25.6GB/s Cell Processor 5GB/s 5GB/s DDRI2 DRAM D-Tuner D-Tuner A-Tuner A-Tuner 2.6GB/s 5MB/s 27MB/s NTSC A/D SCC A/V 555MB/s Modem V-DAC/HDMI V-DAC A-DAC S/PDIF TEL HD Output SD Output (D4, S2,CVBS) 2ch S,CVBS+Audio IEEE MB/s PC

11 Computer peripheral functions in SCC XDR-DRAM DDRI2 DRAM 25.6GB/s 2.6GB/s Cell Processor 5GB/s 5GB/s SCC AV Giga Bit Ether 1Port 250MB/s 2.0GB/s PCI express x4 Link USB2.0 4 Ports ATA Ports 60MB/s 133MB/s PC 133MB/s 133MB/s PCI 4 slot AC 97 Audio/Codec

12 Outline Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

13 From BS Digital Tuner TS Input Audio/Visual Processing Steps 1. < Digital Broadcasting > Multi2 Descramble Demux Audio Dec DAC Audio Output Video Dec I/P Scaling α Correction NTSC En or HDMI Video Output Character Descramble Scaling α Correction NTSC En VCR Output 2. Scramble 3. HDD

14 TS I/F Audio/Visual data flow Taking digital broadcasting and Outputting A/V data with time shift function FlexIO Cell XDR FlexIO ATA I/F FlexIO Cell XDR FlexIO DMAC 6. DDR2 Video Output Audio Output :SCC from/to Cell :Data Transfer in SCC

15 Data Processing Flow 1. Transferring the data from TS I/F to Cell Processor. 2. Processing the data with XDR. 3. Recording the data on HDD. 4. Reading the data on HDD. 5. Processing the data with XDR. 6. Transferring the data from XDR to DDR2, Audio I/F. 7. Transferring the data fromddr2 to Video out I/F. Digital Tuner

16 Outline Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

17 Video Out MBUS DDR2 Internal Bus Hierarchy DMAC Cell Processor FlexIO TBUS Best Effort Processing PCI- express PCI Real Time Processing HBUS SBUS USB ATA GbE Enc/ Dec GBUSC TS In IEEE 1394 Video In Audio In Audio Out GBUS EBUS DMA SIO PIO I2C Timer

18 Key Architecture (1/2) Internal Bus Architecture Quality of Service (QoS) -Bandwidth allocation by bus arbitration mechanism.(with priority in every cycle. TDM.) Hierarchical Architecture -Dividing the bus according to the required features. Real time bus and Best effort. DDR2 memory interface Dedicated DMA controller -For streaming data.

19 Key Architecture (2/2) Other Features Virtual Channel Mechanism To avoid blocking for data flow. Stuck or Long Latency Legacy I/O traffic Video Data traffic Multiple thread mechanism Multi/Single threads are alternative. Pipelined data processing Data ordering mechanism

20 FlexIO controller Virtual Channel/Thread correspond to Cell functionality Master Path : 8 Slave Path : 4 Priority Control

21 Dedicated DMA controller < For DDR2 memory > High bandwidth XDR DDR2 DDR2 XDR 4 Virtual Channel(thread) Multi/Single threads

22 Requirement vs. Bandwidth < MBUS, SBUS, HBUS > The each maximum bus bandwidth(2.66gbyte/s) is sufficient for the every required module bandwidth.

23 Bandwidth Allocation Results < TBUS > Adjusting to the optimized bandwidth. 2.66GByte/S The bandwidth allocation mechanism can satisfy the BUS requirement from each module/bus bridge.

24 Outline Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

25 Chip Photo Process 90nm CMOS Process 7 Layer Cu Frequency -333MHz Package PBGA[FC],1385pin, 40mm,1mm pitch Chip Size 12.71mm x 12.71mm VDD Core: 1.2V I/O: Multiple voltages for various peripherals

26 Outline Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

27 Conclusion Super Companion Chip for Cell processor system has been successfully developed. Both rich audio visual features supporting HD and PC I/O features are integrated on the chip. Simultaneous 48 MPEG-2 SD stream decoding has been demonstrated by utilizing SCC s high bandwidth bus with QoS capability.