# CMU Introduction to Computer Architecture, Spring 2013 HW 6 Solutions: Caching and Memory

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1 CMU Introduction to Computer Architecture, Spring 2013 HW 6 Solutions: Caching and Memory Instructor: Prof. Onur Mutlu TAs: Justin Meza, Yoongu Kim, Jason Lin 1 Virtual Memory and Caching [10 points] A 2-way set associative write back cache with perfect LRU replacement requires bits of storage to implement its tag store (including bits for valid, dirty and LRU). The cache is virtually indexed, physically tagged. The virtual address space is 1 MB, page size is 2 KB, cache block size is 8 bytes. (a) What is the size of the data store of the cache in bytes? 8 KB The cache is 2-way set associative. So, each set has 2 tags, each of size t, 2 valid bits, 2 dirty bits and 1 LRU bit (because a single bit is enough to implement perfect LRU for a 2-way set associative cache). Let i be the number of index bits. Tag store size = 2 i (2 t ) = Therefore, 2t = 10 t = 5 i = 9 Data store size = 2 i (2 8) bytes = 2 9 (2 8) bytes = 8 KB. (b) How many bits of the virtual index come from the virtual page number? 1 bit Page size is 2 KB. Hence, the page offset is 11 bits (bits 10:0). The cache block offset is 3 bits (bits 2:0) and the virtual index is 9 bits (bits 11:3). Therefore, one bit of the virtual index (bit 11) comes from the virtual page number. (c) What is the physical address space of this memory system? 64 KB The page offset is 11 bits. The physical frame number, which is the same as the physical tag is 5 bits. Therefore, the physical address space is 2 (11+5) = 2 16 bytes = 64 KB. 2 Memory Interleaving [15 points] A machine has a main memory of 4 KB, organized as 1 channel, 1 rank and N banks (where N > 1). The system does not have virtual memory. Data is interleaved using a cache block interleaving policy, as described in lecture, where consecutive cache blocks are placed on consecutive banks. The size of a cache block is 32 bytes. Size of a row is 128 bytes. An open row policy is used, i.e., a row is retained in the row-buffer after an access, until an access to another row is made. 1/9

2 A row-buffer hit is an access to a row that is present in the row-buffer. A row-buffer is an access to a row that is not present in the row-buffer. (a) For a program executing on the machine, accesses to the following bytes in the on-chip caches and go to memory. 0, 32, 320, 480, 4, 36, 324, 484, 8, 40, 328, 488, 12, 44, 332, 492 The row-buffer hit rate is 0%, i.e., all accesses in the row-buffer. What is the minimum value of N - the number of banks? 2 banks Size of a cache block is 32 bytes. Therefore, the cache block access sequence corresponding to the given byte access sequence is 0, 1, 10, 15, 0, 1, 10,15, 0, 1, 10, 15, 0, 1, 10, 15. When the number of banks is 1, all cache blocks are mapped to the same bank. Cache block 0, cache block 1, cache block 10 and cache block 15 are mapped to rows 0, 0, 2 and 3 respectively. Therefore, when cache block 1 is accessed right after cache block 0, it would hit in the row-buffer as row 0 would already be in the row-buffer. Hence, row-buffer hit rate would not be 0%. When the number of banks is 2, the 4 cache blocks 0, 1, 10 and 15 map to different rows and banks - (bank 0, row 0), (bank 1, row 0), (bank 0, row 1) and (bank 1, row 1) respectively. Hence, the access sequence would be (bank 0, row 0), (bank 1, row 0), (bank 0, row 1), (bank 1, row 1) (repeated four times). Therefore, rows 0 and 1 on each bank are accessed in an alternating fashion, resulting in a 0% row-buffer hit rate. (b) If the row-buffer hit rate for the same sequence were 75%, what would be minimum value of N - the number of banks? 4 banks When the number of banks is 1, cache blocks 0, 1, 10 and 15 map to rows 0, 0, 2 and 3 respectively (as we saw in part a). Thus, the row access sequence is 0, 0, 2, 3 (repeated four times). Three out of four accesses are row-buffer conflicts, hence the row-buffer hit rate is only 25%. For all other number of banks, the four cache blocks 0, 1, 10 and 15 map to different rows. Hence, assuming the rows containing the four cache blocks are not already open in the row-buffer, the maximum achievable hit rate is 75%, as the first access to each cache block would result in a (compulsory) row-buffer. This maximum hit rate of 75% can be achieved only if there are no row-buffer conflicts. Thus, rows containing the four cache blocks should map to different banks. Therefore, the minimum number of banks required to achieve this hit rate is 4. (c) i) Could the row-buffer hit rate for the sequence be 100%? Why or why not? Explain. The four cache blocks are mapped to different rows. Hence the row-buffer hit rate can be 100% only if the row containing each cache block is already open. ii) If yes, what is the minimum number of banks required to achieve a row-buffer hit rate of 100%? 4 banks is sufficient to achieve this, if the four rows containing the four cache blocks are already open (at each of the four banks). 2/9

6 5 Memory Scheduling [35 points] To serve a memory request, the memory controller issues one or multiple DRAM commands to access data from a bank. There are four different DRAM commands. ACTIVATE: Loads the row (that needs to be accessed) into the bank s row-buffer. This is called opening a row. (Latency: 15ns) PRECHARGE: Restores the contents of the bank s row-buffer back into the row. This is called closing a row. (Latency: 15ns) READ/WRITE: Accesses data from the row-buffer. (Latency: 15ns) The following figure shows the snapshot of the memory request buffers (in the memory controller) at t 0. Each request is color-coded to denote the application to which it belongs (assume that all applications are running on separate cores). Additionally, each request is annotated with the address (or index) of the row that the request needs to access (e.g., R3 means that the request is to the 3 rd row). Furthermore, assume that all requests are read requests. application A s request application B s request application C s request Request queue for Bank 0 (Channel 0) R21 R17 R3 R11 R3 R3 R12 R9 R3 R5 R3 youngest oldest Request queue for Bank 0 (Channel 1) R27 R2 R18 R12 R4 R1 R3 R19 R12 R18 R12 youngest oldest Channel 0 Bank 0 Row 3 Channel 1 Bank 0 Row 12 A memory request is considered to be served when the READ command is complete (i.e., 15ns after the request s READ command has been issued). In addition, each application (A, B, or C) is considered to be stalled until all of its memory requests (across all the request buffers) have been served. Assume that, initially (at t 0 ) each bank has the 3 rd and the 12 th row loaded in the row-buffer, respectively. Furthermore, no additional requests from any of the applications arrive at the memory controller. 5.1 Application-Unaware Scheduling Policies (a) Using the FCFS scheduling policy, what is the stall time of each application? App A: MAX(2H+7M, H+9M) = H+9M = = 420ns App B: MAX(2H+8M, H+8M) = 2H+8M = = 390ns App C: MAX(2H+9M, H+10M) = H+10M = = 465ns (b) Using the FR-FCFS scheduling policy, what is the stall time of each application? App A: MAX(5H+2M, (4H+2M)+4M) = 4H+6M = = 330ns App B: MAX((5H+2M)+3M, 4H+2M) = 5H+5M = = 300ns App C: MAX(((5H+2M)+3M)+M, ((4H+2M)+4M)+M) = 4H+7M = = 375ns (c) What property of memory references does the FR-FCFS scheduling policy exploit? (Three words or less.) Row-buffer locality 6/9

7 (d) Briefly describe the scheduling policy that would maximize the request throughput at any given bank, where request throughput is defined as the number of requests served per unit amount of time. (Less than 10 words.) FR-FCFS 5.2 Application-Aware Scheduling Policies Of the three applications, application C is the least memory-intensive (i.e., has the lowest number of outstanding requests). However, it experiences the largest stall time since its requests are served only after the numerous requests from other applications are first served. To ensure the shortest stall time for application C, one can assign its requests with the highest priority, while assigning the same low priority to the other two applications (A and B). (a) Scheduling Policy X: When application C is assigned a high priority and the other two applications are assigned the same low priority, what is the stall time of each application? (Among requests with the same priority, assume that FR-FCFS is used to break ties.) App A: MAX(M+(4H+3M), M+(3H+3M)+4M) = 3H+8M = = 405ns App B: MAX(M+(4H+3M)+3M, M+(3H+3M)) = 4H+7M = = 375ns App C: MAX(M, M) = M = 45ns application A s request application B s request application C s request Request queue for Bank 0 (Channel 0) R21 R17 R3 R11 R3 R3 R12 R9 R3 R5 R3 youngest oldest Request queue for Bank 0 (Channel 1) R27 R2 R18 R12 R4 R1 R3 R19 R12 R18 R12 youngest oldest Channel 0 Bank 0 Row 3 Channel 1 Bank 0 Row 12 Can you design an even better scheduling policy? While application C now experiences low stall time, you notice that the other two applications (A and B) are still delaying each other. (b) Assign priorities to the other two applications such that you minimize the average stall time across all applications. Specifically, list all three applications in the order of highest to lowest priority. (Among requests with the same priority, assume that FR-FCFS is used to break ties.) C > B > A (c) Scheduling Policy Y: Using your new scheduling policy, what is the stall time of each application? (Among requests with the same priority, assume that FR-FCFS is used to break ties.) App A: MAX(M+(3M)+(4H+3M), M+(3H+3M)+4M) = 3H+8M = = 405ns App B: MAX(M+(3M), M+(3H+3M)) = 3H+4M = = 225ns App C: MAX(M, M) = M = 45ns 7/9

9 (d) Propose a way to reduce/overcome the shortcoming of MagicRAM by modifying the given memory hierarchy. Be clear in your explanations and illustrate with drawings to aid understanding. A write-combining/coalescing buffer could be added. The memory hierarchy could also perform wearleveling, or it could predict which data is less likely to be modified and place only that data in MagicRAM. Figure(s): 9/9

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