TRACE32 Documents... ICD In-Circuit Debugger... Processor Architecture Manuals... TriCore... TriCore Monitor... 1

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1 TriCore Monitor TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... ICD In-Circuit Debugger... Processor Architecture Manuals... TriCore... TriCore Monitor... 1 Brief Overview of Documents for New Users... 4 General Note... 5 Quick Start of the TriCore Serial Monitor... 6 Troubleshooting... 7 FAQ... 7 Basics... 8 Monitor Features 8 Monitor Files 8 Exceptions 9 Configuration 9 General SYStem Settings and Restrictions SYStem.CPU CPU type 10 SYStem.CpuAccess Run-time memory access (intrusive) 10 SYStem.MemAccess Real-time memory access (non-intrusive) 11 SYStem.Mode Establish the communication with the CPU 12 SYStem.Option IMASKASM Disable interrupts while single stepping 13 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 13 TrOnchip TrOnchip.CONVert Adjust range breakpoint in on-chip resource 14 TrOnchip.VarCONVert Adjust complex breakpoint in on-chip resource 14 TrOnchip.RESet Set on-chip trigger to default state 15 TrOnchip.TEnable Set filter for the trace 15 TrOnchip.TOFF Switch the sampling to the trace to OFF 15 TrOnchip.TON Switch the sampling to the trace to ON 15 Support Available Tools 17 TriCore Monitor 1

2 Compilers 17 Realtime Operation System 18 3rd Party Tool Integrations 18 Products Product Information 20 Order Information 20 TriCore Monitor 2

3 TriCore Monitor Version 24-May-2016 TriCore Monitor 3

4 Brief Overview of Documents for New Users Architecture-independent information: Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a TRACE32 debugger. T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger. T32Start is only available for Windows. General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands. Architecture-specific information: Processor Architecture Manuals : These manuals describe commands that are specific for the processor architecture supported by your debug cable. To access the manual for your processor architecture, proceed as follows: - Choose Help menu > Processor Architecture Manual. RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware debugging. TriCore Monitor 4 Brief Overview of Documents for New Users

5 General Note This documentation describes the processor specific settings and features of the TriCore ROM Monitor. You can find the description of the OCDS-L1 Debugger for the TriCore family at TriCore Debugger and Trace (debugger_tricore.pdf). TriCore Monitor 5 General Note

6 Quick Start of the TriCore Serial Monitor Starting up the ROM Monitor is done as follows: 1. Select the device B: for the ROM Monitor. B: 2. Tranisition to the down mode before pressing the reset button. SYStem.Mode Down This instruction is necessary when the system is restarted. 3. Set the CPU type in the ROM Monitor program: SYStem.CPU TC Define the communication parameters. SYStem.PORT COM2 BAUD= Activate the ROM monitor SYStem.Up A typical start sequence is shown below: ; for this example the TriBoard TC1796 Evaluation board is used B: SYStem.Mode Down WinCLREAR SYStem.CPU tc1796 SYStem.PPORT COM2 BAUD=38400 ; select the Debugger device ; switch the system down ; clear all windows ; set the CPU type for the user interface SYStem.Mode Up The start up can be automated using the programming language PRACTICE. TriCore Monitor 6 Quick Start of the TriCore Serial Monitor

7 Troubleshooting No information available. FAQ No information available TriCore Monitor 7 Troubleshooting

8 Basics Monitor Features The monitor requires no stack. tbd. Monitor Files tbd. TriCore Monitor 8 Basics

9 Exceptions tbd. Configuration tbd. TriCore Monitor 9 Basics

10 General SYStem Settings and Restrictions SYStem.CPU CPU type SYStem.CPU <cpu> <cpu>: TC1792 TC1796 TC1796ED Selects the processor type. The ROM debugger requires also a modification in the debug monitor for different processor types. SYStem.CpuAccess Run-time memory access (intrusive) SYStem.CpuAccess Enable Denied Nonstop Default: Denied. Enable Denied Nonstop Allow intrusive run-time memory access. In order to perform a memory read or write while the CPU is executing the program the debugger stops the program execution shortly. Each short stop takes ms depending on the speed of the debug interface and on the number of the read/write accesses required. A red S in the state line of the TRACE32 screen indicates this intrusive behavior of the debugger. Lock intrusive run-time memory access. Lock all features of the debugger, that affect the run-time behavior. Nonstop reduces the functionality of the debugger to: run-time access to memory and variables trace display The debugger inhibits the following: to stop the program execution all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.) TriCore Monitor 10 General SYStem Settings and Restrictions

11 SYStem.Down Disables monitor SYStem.Down SYStem.MemAccess Real-time memory access (non-intrusive). SYStem.MemAccess CPU Denied NEXUS <cpu_specific> SYStem.ACCESS (deprecated) CPU Denied NEXUS Real-time memory access during program execution to target is enabled. Real-time memory access during program execution to target is disabled. Memory access is done via the NEXUS interface. Default: Denied. TriCore Monitor 11 General SYStem Settings and Restrictions

12 SYStem.Mode Establish the communication with the CPU SYStem.Mode <mode> <mode>: Down NoDebug Go Up Default: Down. Selects the target operating mode. tbd. Down NoDebug Go Up The CPU is in reset. Debug mode is not active. Default state and state after fatal errors. The CPU is running. Debug mode is not active. Debug port is tristate. In this mode the target should behave as if the debugger is not connected. The CPU is running. Debug mode is active. After this command the CPU can be stopped with the break command or if any break condition occurs. The CPU is not in reset but halted. Debug mode is active. In this mode the CPU can be started and stopped. This is the most typical way to activate debugging. If the mode Go is selected, this mode will be entered, but the control button in the SYStem window jumps to the mode UP. TriCore Monitor 12 General SYStem Settings and Restrictions

13 SYStem.Option IMASKASM Disable interrupts while single stepping SYStem.Option IMASKASM [ON OFF] Default: OFF. If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. SYStem.Option IMASKHLL Disable interrupts while HLL single stepping SYStem.Option IMASKHLL [ON OFF] Default: OFF. If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. TriCore Monitor 13 General SYStem Settings and Restrictions

14 TrOnchip TrOnchip.CONVert Adjust range breakpoint in on-chip resource TrOnchip.CONVert [ON OFF] The on-chip breakpoints can only cover specific ranges. If a range cannot be programmed into the breakpoint it will automatically be converted into a single address breakpoint when this option is active. This is the default. Otherwise an error message is generated. TrOnchip.CONVert ON Break.Set 0x x17ff /Write Break.Set 0x x17ff /Write TrOnchip.CONVert OFF Break.Set 0x x17ff /Write Break.Set 0x x17ff /Write ; sets breakpoint at range ; ff sets single breakpoint ; at address 1001 ; sets breakpoint at range ; ff ; gives an error message TrOnchip.VarCONVert Adjust complex breakpoint in on-chip resource TrOnchip.VarCONVert [ON OFF] The on-chip breakpoints can only cover specific ranges. If you want to set a marker or breakpoint to a complex variable, the on-chip break resources of the CPU may be not powerful enough to cover the whole structure. If the option TrOnchip.VarCONVert is ON the breakpoint will automatically be converted into a single address breakpoint. This is the default setting. Otherwise an error message is generated. TriCore Monitor 14 TrOnchip

15 TrOnchip.RESet Set on-chip trigger to default state TrOnchip.RESet Sets the TrOnchip settings and trigger module to the default settings. TrOnchip.TEnable Set filter for the trace TrOnchip.TEnable <par> Obsolete command. Refer to the Break.Set command to set trace filters. TrOnchip.TOFF Switch the sampling to the trace to OFF TrOnchip.TOFF Obsolete command. Refer to the Break.Set command to set trace filters. TrOnchip.TON Switch the sampling to the trace to ON TrOnchip.TON EXT Break Obsolete command. Refer to the Break.Set command to set trace filters. TriCore Monitor 15 TrOnchip

16 Memory Classes Memory Class D P C E A Description Data Program Memory access by CPU Emulation memory access Absolute (physical) memory access TriCore Monitor 16 TrOnchip

17 Support Available Tools tbd. Compilers Language Compiler Company Option Comment C/C++ GREENHILLS Greenhills Software Inc. ELF/DWARF2 C/C++ GCC HighTec EDV-Systeme ELF/DWARF2 GmbH C/C++ VX-TC TASKING ELF/DWARF2 C/C++ VX-TC TASKING IEEE C/C++ DIAB Wind River Systems ELF TriCore Monitor 17 Support

18 Realtime Operation System Name Company Comment Elektrobit tresos Elektrobit Automotive GmbH via ORTI Erika Evidence via ORTI Nucleus Mentor Graphics Corporation oscan Vector via ORTI OSE Epsilon Enea OSE Systems OSEK - via ORTI ProOSEK Elektrobit Automotive GmbH via ORTI PXROS-HR HighTec EDV-Systeme GmbH uc/os-ii Micrium Inc. 2.0 to 2.8 VxWorks Wind River Systems 5.x and 6.x 3rd Party Tool Integrations CPU Tool Company Host ALL ADENEO Adeneo Embedded ALL X-TOOLS / X32 blue river software GmbH Windows ALL CODEWRIGHT Borland Software Windows Corporation ALL CODE CONFIDENCE Code Confidence Ltd Windows TOOLS ALL CODE CONFIDENCE Code Confidence Ltd Linux TOOLS ALL EASYCODE EASYCODE GmbH Windows ALL ECLIPSE Eclipse Foundation, Inc Windows ALL RHAPSODY IN MICROC IBM Corp. Windows ALL RHAPSODY IN C++ IBM Corp. Windows ALL CHRONVIEW Inchron GmbH Windows ALL LDRA TOOL SUITE LDRA Technology, Inc. Windows ALL UML DEBUGGER LieberLieber Software Windows GmbH ALL ATTOL TOOLS MicroMax Inc. Windows ALL VISUAL BASIC Microsoft Corporation Windows INTERFACE ALL LABVIEW NATIONAL Windows INSTRUMENTS Corporation ALL CODE::BLOCKS Open Source - ALL C++TEST Parasoft Windows ALL RAPITIME Rapita Systems Ltd. Windows TriCore Monitor 18 Support

19 CPU Tool Company Host ALL DA-C RistanCASE Windows ALL TRACEANALYZER Symtavision GmbH Windows ALL SIMULINK The MathWorks Inc. Windows ALL TA INSPECTOR Timing Architects GmbH Windows ALL UNDODB Undo Software Linux ALL VECTORCAST UNIT Vector Software Windows TESTING ALL VECTORCAST CODE Vector Software Windows COVERAGE ALL WINDOWS CE PLATF. BUILDER Windows Windows TriCore Monitor 19 Support

20 Products Product Information OrderNo Code LA-7515D MON-TC-SER-UD Text ROM Monitor for TriCore Serial Access UD support TriCore AUDO family for serial access, includes HLL debugger, operation system, licensed for one host system via USB dongle for Windows32, Windows64, Linux32, Linux64 and MAC OS X Order Information Order No. Code Text LA-7515D MON-TC-SER-UD ROM Monitor for TriCore Serial Access UD TriCore Monitor 20 Products