Introducing the Dezyne Modelling Language Bits & Chips Smart Systems, 20 November 2014 Paul Hoogendijk. paul.hoogendijk@verum.com
Software Controlled Systems
Software Controlled Systems Event driven Concurrent, complex High cost-of-non-quality Field defects (SLA) and field updates Difficult and expensive to test Many scenario's: events interleaving, exceptions (errors) Dependency on hardware availability Managing complexity is key
designer/engineer wants Trust
designer/engineer wants Trust proper spec?
designer/engineer wants Trust proper spec? clean & clear architecture/design?
designer/engineer wants Trust proper spec? clean & clear architecture/design? code implements architecture/design?
designer/engineer wants Trust proper spec? clean & clear architecture/design? code implements architecture/design? code quality and complexity?
designer/engineer wants Trust proper spec? clean & clear architecture/design? code implements architecture/design? code quality and complexity? unit tests?
designer/engineer wants Trust proper spec? clean & clear architecture/design? code implements architecture/design? code quality and complexity? unit tests? end-to-end tests?
designer/engineer wants Trust proper spec? clean & clear architecture/design? code implements architecture/design? code quality and complexity? unit tests? end-to-end tests? test coverage, including all exceptions?
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Create. Dezyne Modelling Language System models subcomponents declaration bindings between ports Component models provides & requires ports declaration behaviour Interface models in & out events declaration behaviour
Components, ports and bindings
Components, ports and bindings
Interfaces: events and behaviour
Interfaces: events and behaviour
Interfaces: in and out events
Interfaces: in and out events
Component: ports and behaviour
Component: ports and behaviour
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Explore: Simulation and Views Sequence diagrams shown are simulator runs User selects next events from list of possible events Exploring interfaces proper specification? Exploring components use cases present?
Explore: Simulation and Views
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Verify: discover hidden defects Automatic full simulation based on Formal Methods For all possible execution scenarios for component check Adheres to its interfaces No deadlock No livelock Handles race conditions correctly If issue found: trace generated leading to problem 100% coverage while no test code written (!)
Verify: discover hidden defects Automatic full simulation based on Formal Methods For all possible execution scenarios for component check Adheres to its interfaces No deadlock No livelock Handles race conditions correctly If issue found: trace generated leading to problem 100% coverage while no test code written (!)
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Trust: code generation Efficient and readable code I could have written that 100% of code is generated No (foreign) code snippets in models Easy integration with external code Via an Dezyne Interface makes assumption about external code explicit Thin wrapper layer Connect to: Legacy software Hardware drivers Non Dezyne subsystem...
Trust: code generation (cont.) Due to Create Explore Verify cycle: Validated: proper specification (interfaces) all use cases present (components) Verified: All component implement their specification correctly No deadlock, no livelock and handles all races correctly Code that can be trusted
Trust based on hard evidence
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