Application Note 1V Timer (Next Gen 555) Page 1
1. Introduction The is a new kind of timer based on a precise clock and an analog to digital converter. Its simple architecture is making possible to have very predictible results even when operating a extremely low supply voltages. It can be compared to the 555 timer in the sense that it compares one input voltage to two present threshold voltages to set or reset an internal memory cell that controls a digital output and an open drain discharge pin. In addition to this old timer, the controls a charge pin and has a burst output that can be used to generate higher voltages. To reduce the size, weight and cost of small appliances, the is made to operate from a single AA or AAA cell. It monitors the supply voltage and indicates when it is above 1.4V, allowing for very simple NiMH or Nid rechargeable devices. 2. Description The main element of the is an 8-bit AD with a fixed LB of 7 mv. The acquires the and in a cyclic way with periodiciy of 200 us. If voltage is above 1.8V, the acquisition is saturated to 1.8V. The result of the acquisition is compared with the acquisition and if < /3 then the is set in charge mode, if > 2*/3 then the is reset in discharge mode. 2/3 1/3 DIHAGE 5 khz HAGE 1.4 V 41 khz In charge mode, the DIHAGE pin is open while the HAGE and the pins are connected to. In discharge mode, the HAGE pin is open while the DIHAGE and the pins are connected to. The pin is generating a 41 khz square wave signal during the charge mode. This signal is on for 2 us and off for 21 us, thus has a total cycle time of 23 us. It is connected to during the discharge mode. The NiMH pin is connected to when the voltage is below 1.4 V, it is connected to when the voltage is above 1.4 V. It has a 25-30 mv hysteresis around this threshold. Page 2
2.1. Monostable Operation (One hot) This is used to generate a single shot of a controlled width on the pin or a burst on the pin. The monostable timer is done with only two external elements: one resistor and one capacitor. The capacitor is connected between the pin and while the resistor is connected between the pin and. 2/3 1.2 V cell 1/3 DIHAGE button HAGE Vth The monostable is reset either by a button-switch or by another circuit with an open collector output that will short the pin to. At that time, the pin goes to and the pin starts to output its square wave. As soon as the pin is released, the capacitor will charge through the resistor and when the pin level reaches 2/3* then the and the pins go back to. The on time after the trigger is released (t ramp ) is directly proportional to * (if parasitics are negligible). t ramp = 1.1 tsw tramp 2/3 1/3 WITH Example: With = 10 kohm and = 1 uf, one get a t ramp of 11 ms. Page 3
2.2. awtooth Astable Operation This is used to generate a frequency. The sawtooth astable timer is done with only two external elements: one resistor and one capacitor. The capacitor is connected between the pin and while the resistor is connected between the pin and. Pin is also connected to pin DIHAGE. 2/3 1.2 V cell 1/3 DIHAGE HAGE Vth The resistor loads the capacitor until reaches 2/3*; during that time, pin is connected to and pin sends its square wave. At the next AD acquisition, will be evaluated above 2/3*, therefore the DIHAGE pin is connected to, unloading the capacitor for one full AD period (200 us). If the capacitor can be downloaded to in this amount of time, then the cycle restarts on the next AD acquisition. and pins go to during the discharge time. The ramp period t ramp is the same as for the monostable timer, the reset period is 200 us (if the capacitor can be discharge in a single period). t period = 1.1 + 0.2ms 2/3 1/3 Example: With = 10 kohm and = 1 uf, one get a t ramp of 11 ms and a full cycle period of 11.2 ms. Page 4
2.3. Astable Operation with 50% duty cycle This is used to generate a square wave on pin and a series of bursts on pin. The square astable timer is done with only two external elements: one resistor and one capacitor. The capacitor is connected between the pin and while the resistor is connected between the pin and pins DIHAGE and HAGE. 2/3 1.2 V cell 1/3 DIHAGE HAGE Vth Let s start in charge mode. In this mode, the resistor is connected to through the HAGE pin. The resistor loads the capacitor until reaches 2/3*; during that time, pin is connected to and pin sends its square wave. At the next AD acquisition, will be evaluated above 2/3*, therefore the chip switches to discharge mode: the HAGE pin is disconnected from and the DIHAGE pin is connected to, unloading the capacitor; and pins go to during the discharge time. When pins goes below 1/3*, then the chip switches back to charge mode. Page 5
The on time between two transitions (t ramp ) is directly proportional to * (if parasitics are negligible). This is half of the period of the full cycle. t period = 2 0.66 2/3 1/3 = 0.66 t ramp Example: With = 10 kohm and = 15 uf, one get a t ramp of 100 ms and a full cycle period of 200 ms. Page 6
2.4. Astable Operation with programmable duty cycle This is used to generate an uneven square wave on pin and a series of bursts on pin. The variable duty cycle astable timer (PWM) is done with only three external elements: two resistors and one capacitor. The capacitor is connected between the pin and while one resistor is connected between the pin and the DIHAGE pin and the other resistor between the pin and the HAGE pin. 2/3 1.2 V cell d c 1/3 DIHAGE HAGE Vth Let s start in charge mode. In this mode, the d resistor is connected to. d loads the capacitor until reaches 2/3*; during that time, pin is connected to and pin sends its square wave. At the next AD acquisition, will be evaluated above 2/3*, therefore the chip switches to discharge mode: the HAGE pin is disconnected from and the DIHAGE pin is connected to, unloading the capacitor through c; and pins go to during the discharge time. When pins goes below 1/3*, then the chip switches back to charge mode Page 7
The on time between two transitions is directly proportional to * (if parasitics are negligible). This is once for going up and once for going down on the period of the full cycle t charge = 0.66 ( c) t discharge = 0.66 ( d) t period = 0.66 ( d + c) 2/3 1/3 Example: With c = 5 kohm, d = 10kOhm and = 15 uf, one get a t rampup of 50 ms, a t rampdown of 100 ms and a full cycle period of 150 ms. Page 8
2.5. Higher Voltage Monitoring This is used to generate a square wave on when the input signal is lower than a preset value and stop it when its above another value. The square wave can be used to generate a higher voltage (booster). The basic principle is to use a resistive divider to reduce the higher voltage to the 1/3 * - 2/3 * range. As this is usually used for regulation, the hysteresis needs to be reduced from 50% of full scale. This is done by using a positive feedback with pin voltage that is added to the input voltage through another resistive divider. input i f 2/3 1.2 V cell s 1/3 DIHAGE HAGE Vth i/s are set so that the mean threshold voltage is as expected. f is set to limit the hysteresis. input 2/3 1/3 Input threshold This can be used to generate a controlled high voltage using the burst output to drive a booster: output is active as long as the input voltage is below the input threshold and stops when the input voltage is above the input threshold. The hysteresis is programmed. Page 9
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