Kojucharow Microwave Development Consulting

0 Design Note KOJUCHAROW-MICROWAVE-DEVELOPMENT-AND-CONSULTING-DRESDEN-GERMANY- 0.2-0.2 0.4 0.2-0.4 0.6-0.6 0.4 0.8 1.0 1.0 KMDC 0.6-0.8 0.8-1.0 2.0 3.0-2.0 2.0 4.0 5.0 3.0-3.0 Swp Max 1 10.0 4.0 5.0 10.0-10.0-5.0-4.0 Swp Min -1 Kojucharow Microwave Development Consulting Telefon: +49(0)351 216 5153 Telefax: +49(0)351 216 5154 Internet: kk@kmdc.de www.kmdc.de Post- und Liefer- Salbachstr. 1, anschrift: 01279 Dresden, Germany Nr. 1 Dresden, 12.01.08 Reconfigurable Dual Transmitter Unit and Dual Receiver Unit for LTE Test Applications -preliminary- (configuration: UL 2.53 GHz, DL 2.68 GHz) Dr.-Ing. K. Kojucharow 1

Table of Contents : 0 Introduction 1 Dual Transmitter Unit (DTxU)... 4 1.1 Architecture... 4 1.1.1 Block Diagram... 4 1.1.2 Functional Description... 4 1.1.3 Subcircuits and Components... 5 1.2 Interface Description... 6 1.2.1 Analogue Ports... 6 1.2.2 Digital Ports... 6 1.3 Specifications... 8 1.3.1 Main Specifications of Default Configuration... 8 1.3.2 Absolute Maximum Ratings... 9 1.4 Internal CPLD Control Functions...10 1.4.1 IF Gain Control...10 1.4.2 IF Switch Control...10 1.4.3 Frontend Control (PA)...11 1.4.4 Local Oscillator Frequency Control...12 1.4.5 Local Oscillator Switch Control...13 1.4.6 Auxiliary Control Signals...13 1.4.7 Reset...13 1.4.8 Start-up...14 2 Dual Receiver Unit (DRxU)...15 2.1 Architecture...15 2.1.1 Block Diagram...15 2.1.2 Functional Description...15 2.1.3 Subcircuits and Components...16 2.2 Interface Description...17 2.2.1 Analogue Ports...17 2.2.2 Digital Ports...17 2.3 Specifications...18 2.3.1 Main Specifications of Default Configuration...18 2.3.2 Absolute Maximum Ratings...19 2.4 Internal CPLD Control Functions...20 2.4.1 IF Gain Control...20 2.4.2 IF Switch Control...22 2.4.3 Frontend Control (Driver)...22 2.4.4 Local Oscillator Frequency Control...23 2.4.5 Local Oscillator Switch Control...24 2.4.6 Auxiliary Control Signals...24 2.4.7 Reset...24 2.4.8 Start-up...25 3 Test Setup...26 3.1 Introduction...26 3.2 Configuration...26 3.3 Bus and Signals...27 3.4 Sequence and Usage...27 3.5 External Switch Box Signals...28 4 ANNEX...29 2

0 INTRODUCTION The note summarises the block diagram, functional description, main specifications, control function description and test configuration of flexible and reconfigurable dual transmitter and dual receiver units referred to as DTxU and DRxU, respectively and designed for LTE test applications. 3

f0=70 MHz B=20 MHz f0=70 MHz B=20 MHz fbb=70 MHz fbb=70 MHz flo1=822 MHz REF to SYN2 f0=892 MHz B=20 MHz B=20 MHz REF fif=892 MHz fif=892 MHz fl02=3422 MHz frf=2530 MHz 1 DUAL TRANSMITTER UNIT (DTXU) 1.1 Architecture 1.1.1 Block Diagram LO1_aux CTR PROG Vcc12 Vcc5 GND LO2_aux2 LO2_aux1 (int.) SYN2 REF_in SYN1 PROG CPLD PSU REF_out LO1 CNTR LO2 1,2,4,8,16 db IF on / off BB0_in BPF_BB UC1 UC70 ATT1 SwTx AGC_Tx BPF_IF BPF_IF UC_2 Driver UC900 PA PA Tx0_out 1,2,4,8,16 db IF on / off f0=892 MHz frf=2530 MHz BB1_in BPF_BB UC1 UC70 ATT1 SwTx AGC_Tx BPF_IF BPF_IF UC_2 Driver UC900 PA PA Tx1_out Fig. 1.1-1 Simplified block diagram and mechanical structure of the dual transmitter unit DTxU, for larger view see additional file/section 1.1.2 Functional Description Double conversion architecture with low IF in- and outputs to and from baseband processing Coherent dual RF transmitter or dual receiver positioned within dedicated RF enclosure, attached externally: Separate high rejection dual diplexer 2 x 2 T/R unit formed by joint mechanical attachment and coax bridges Phys. dimensions and mounting scheme similar to previous platform for seamless integration Extendable operation to 4 x 4 T/R unit by local oscillator coax bridges Selectable by synthesizer board population options: single RF channel at low phase noise, full extension band at regular phase noise Stand alone operation possible (only 2 transmitters or only 2 receivers) flexible realisation with exchangeable internal subcircuits for straightforward reconfiguration possible operation modes: FDD, FDD/TDD, TDD (after reconfig.) external reference 38 MHz supply (default) with through loop each module with individual address and controlled/monitored by serial bus system (IAF) to/from IAF-AD/DA board digital gain control, loop via baseband 4

1.1.3 Subcircuits and Components LO1: first synthesizer (SYN1, UHF range) and reference loop through CNTR: control/supply board with control IC (CPLD) and voltage regulators (PSU) LO2: second synthesizer (SYN2, C-Band), optional: switching network UC70: input (low-if) bandpass filter (BPF_BB) and first upconverter to IF (UC1) AGC_Tx: transmitter buffer amplifier, dig. gain control (ATT1) and IF switch (SwTx) BPF_IF: main IF filter (BPF_IF), helical filter UC900: second upconverter UC2, image filter and PA preampl. (Driver) PA: main power amplifier (PA) 5

1.2 Interface Description 1.2.1 Analogue Ports Connector type: all coaxial ports SMA (f) and 50 Ohm, DC feedthrough pins Name Description Level REF_in REF signal input approx. 1 V pp sinewave REF_out loop through REF output approx. 1 V pp sinewave BB0_in low IF input, path 0 P in =-6 dbm rms OFDM 1) BB1_in low IF input, path 1 see above Tx0_out transmitter output, path 0 P out =+26 dbm max. rms OFDM Tx1_out transmitter output, path 1 P out =+26 dbm max. rms OFDM LO1_aux auxiliary LO1 output tbd. LO2_aux1 auxiliary LO2 output tbd. LO2_aux2 auxiliary LO2 in/output tbd. Vcc12 DC supply +12 V nominal Vcc5 DC supply for PA only 5.0...5.1 V nominal GND case ground 1) resulting from 1 Vpp DAC output (corresponding to +4 dbm sinewave into load R=50 Ohm) and -10 db backoff for OFDM modulation, minimum input level P in =-10 dbm 1.2.2 Digital Ports 1.2.2.1 Main Control Port CTR Connector type: SubD-9 filtered Name Description Level / Gate (IC Pin) CTR control interface to/from AD and DA TTL 3.3V (5V tbd.) board 1) Pin 1 MODEM_IO_7 2) IO_2_8 (63) Pin 2 MODEM_IO_6 IO_2_10 (1) Pin 3 MODEM_IO_5 IO_2_12 (4) Pin 4 MODEM_IO_4 IO_2_15 (6) Pin 5 MODEM_IO_3 IO_2_17 (7) Pin 6 MODEM_IO_2 IO_2_9 (64) Pin 7 MODEM_IO_1 IO_2_11 (2) Pin 8 Test_mode 3) IO_2_14 (5) Pin 9 GND case GND 1) possible: parallel usage of this bus by DTxU and DRxU tbd. 2) design of data telegram and individual addresses of units tbd. 3) used to activate test mode with ext. switch box, upon activation signal assignment changes, for description see next section 3 6

1.2.2.2 Programming Port for CPLD (internal) Connector type: internal pin row within RF enclosure Name Description Level / Gate (IC pin) PROG internal port for CPLD progr. 1) TTL 3.3V (5V tbd.) Pin 1 TDO TDO (53) Pin 2 TCK TCK (30) Pin 3 TMS TMS (29) Pin 4 TDI TDI (28) Pin 5 +3V3 +3.3V Pin 6 GND case GND 1) originally its has been planned to use connector J1 (Molex 3 311 420) however for board space restrictions a temporal pin type connector has to be used in conjunction with an external adapter to Molex type standard and the programming device 7

1.3 Specifications 1.3.1 Main Specifications of Default Configuration Parameter Value Centre frequency RF: UMTS extension band UL: 2530 MHz (DL: 2680 MHz) Tuning range: -5...+10 MHz 1) or -25...+25 MHz 2) System bandwidth: 20 MHz 3) Frequency LO1: 821.2 MHz 1) Frequency LO2: 3422 MHz 1) Centre frequency BB input: 70.8 MHz Reference frequency: 38.4 MHz Level range BB input: -6 dbm...-10 dbm rms OFDM PA compression point: +28 dbm typ., +26 dbm min. P 4) 1dB Max. modulated output: +26 dbm rms OFDM 7) Gain control range: 31 db, 1 db steps Transmitter max. gain: 32 db 7) Level range LO1: tbd. Level range LO2: tbd. IMD3 products at output(s): <-35 dbc typ. Total SSB Phase Noise: < 70 dbc/hz @ 1 khz offset 1) <-100 dbc/hz @ 10 khz offset <-120 dbc/hz @ 100 khz offset <-120 dbc/hz @ 1 MHz offset Front end attenuation: 3 db max. 5) Vector Accuracy: n/a Port impedance: 50 Ohm nom., all ports AGC_range Tx: 31 db, 1 db steps IF Switch Isolation : 45 dbc typ. Switching speed AGC : < 500ns 6) Switching speed Tx/Rx < 500ns 6) Supply voltage Vcc5: Vcc5=+ 5.00...+5.10 V Supply current to above: I=2 A max. Supply voltage Vcc12: Vcc12=+ 9.5...+14.5 V Supply current to above: I=1.5 A max. Temp.-range: T=0 50 C Supported modes: FDD, FDD/TDD 1) low phase noise setup 2) wide range setup 3) approx. -1 db points, can be changed for alternative by BPF_IF type 4) at each of DTxU outputs (Tx0_out and Tx1_out) 5) diplexer and cabling 6) 10%/90% RF level 7) for AGC_tx=0 db (min. attenuation in IF cascade) 8

1.3.2 Absolute Maximum Ratings Parameter Value Supply voltage Vcc12: 20 V Supply voltage for PA Vcc5: 5.3 V or <0 V! Level BB input: +6 dbm rms, +10 dbm peak Level REF input: 2 V pp DC level at all coax ports: 6.3 V to GND Level at all control lines: 5.5 V to GND Reverse RF power into PA: +30 dbm rms 9

1.4 Internal CPLD Control Functions In the following the internal control functions to be achieved by the CPLD circuit are specified and discussed. The activation of these functions is done by an external call via the CTR interface by means of specified data blocks (IAF). 1.4.1 IF Gain Control 1.4.1.1 Table Function Description CPLD Signal (IC pin), path ATT1_1dB Logic 0: att. on 1) I/O_4_6 (49), path 0 Logic 1: att. off I/O_4_11 (48), path 1 ATT1_2dB Logic 0: att. on I/O_4_14 (50), path 0 Logic 1: att. off I/O_4_4 (47), path 1 ATT1_4dB Logic 0: att. on I/O_4_10 (51), path 0 Logic 1: att. off I/O_4_3 (46), path 1 ATT1_8dB Logic 0: att. on I/O_4_12 (52), path 0 Logic 1: att. off I/O_4_8 (45), path 1 ATT1_16dB Logic 0: att. on I/O_4_15 (56), path 0 Logic 1: att. off I/O_4_5 (44), path 1 1) All elements have pull-down resistors 10 kohm to GND (logic 0). Pull up to level +3.3V (logic 1) by means of the CPLD gate. 1.4.1.2 Sequence Continuous 0...31 db attenuation for desired output power. 1.4.2 IF Switch Control 1.4.2.1 Table Function Description CPLD Signal (IC pin), path SwTx Logic 0: IF off 1) I/O_2_4 (59), path 0 Logic 1: IF on I/O_3_12 (40), path 1 1) All elements have pull-down resistors 10 kohm to GND (logic 0). Pull up to level +3.3V (logic 1) by means of the CPLD gate. 1.4.2.2 Sequence FDD mode: ON, permanently TDD mode: operate inversely to DRxU and conditions of PA control apply 10

1.4.3 Frontend Control (PA) 1.4.3.1 Table Function Description CPLD Signal (IC pin), path PAenable Logic 0: PA off 1) I/O_2_2 (60), path 0 Logic 1: PA on I/O_3_10 (39), path 1 1) All elements have pull-down resistors 10 kohm to GND (logic 0). Pull up to level +3.3V (logic 1) by means of the CPLD gate. 1.4.3.2 Sequence FDD mode: ON, permanently TDD mode: operate inversely to DRxU Further: important to prevent damage to PA circuit State Actions first start-up 1. PAenable OFF (always!) 2. SwTx OFF (always!) 3. Voltage_PA sense 5V then 4. Guard time T guard 5. PAenable ON 6. Guard time T guard 7. SwTx ON Vcc5 interruption 1. Voltage_PA sense <<5V 2. PAenable OFF (with min. delay) and SwTx OFF (with min. delay) 3. Resume start-up seq. when Voltage_PA sense 5V Tbd: proposed guard time T guard =50...100 ms. Tbd: voltage to logic relation of signal Voltage_PA 11

1.4.4 Local Oscillator Frequency Control 1.4.4.1 Table Function Description CPLD Signal (IC pin) CLK_LO1 tbd. I/O_3_17 (38) Data_LO1 tbd. I/O_3_15 (36) LE_LO1 tbd. I/O_3_14 (35) LD_LO1 tbd. I/O_3_6 (34) CLK_LO2 tbd. I/O_1_2 (8) Data_LO2 tbd. I/O_1_5 (9) LE_LO2 tbd. I/O_1_6 (10) LD_LO2 tbd. I/O_1_8 (11) 1) All elements have pull-down resistors 10 kohm to GND (logic 0). Pull up to level +3.3V (logic 1) by means of the CPLD gate. 1.4.4.2 Sequence Programming for given frequencies according to the scheme of the ADF-4106/ADF- 4107 PLL synthesizer integrated circuit (Analog Devices). Lock detect signals to be delivered to AD/DA board via CTR interfaces for monitor and indication of LO operation. The following frequencies will be stored in the CPLD: Synthesizer Frequency [ Settings Syn1 f LO1 =821.2 MHz N=2053, P=16, B=128, A=5, for further see Annex Syn2 (centre ch.) f LO2 =3422 MHz N=34220, P=16, B=2138, A=12, for further see Annex Syn2 f LO2 =tbd. MHz (add. ch.) Syn2 (add. ch.) f LO2 =tbd. MHz Values are valid for REF=38.4 MHz. Further settings: PFD=400kHz for Syn1 PFD=100kHz for Syn2 Rset=4.7kOhm CPcurrent=5mA Fastlock=OFF Digital Lock Detect=ON 12

1.4.5 Local Oscillator Switch Control 1.4.5.1 Table Function Description CPLD Signal (IC pin) SwLO1 tbd. I/O_3_11 (33) SwLO2a tbd. I/O_1_3 (12) SwLO2b tbd. I/O_1_4 (13) 1) All elements have pull-down resistors 10 kohm to GND (logic 0). Pull up to level +3.3V (logic 1) by means of the CPLD gate. The signals will be used for switching between two PLLs within subcircuit LO2, where implemented. Not used in default configuration. 1.4.5.2 Sequence For single LO2 and fixed frequency operation set functions SwLO1 and SwLO2a permanently to logic 1. 1.4.6 Auxiliary Control Signals 1.4.6.1 Table Function Description CPLD Signal (IC pin) Aux1 tbd. I/O_2_5 (61) Aux2 tbd. I/O_2_6 (62) 1) 1.4.6.2 Sequence tbd. 1.4.7 Reset 1.4.7.1 Table Function Description CPLD Signal (IC pin) Reset Logic 0: Reset I/O_1_17 (20) Logic 1: normal 1) Pin internally pulled up to +3.3V (logic 1) by default. When button of board switch is pressed the pin is pulled down to GND (logic 0). 1.4.7.2 Sequence Upon manual activation when required. 13

1.4.8 Start-up After initial application of supply voltage Vcc12, the CPLD shall perform the following actions independent of any connected elements to the CTR interface, i.e. with or without connected CTR cable: 1. IF gain control for min. Gain 2. SwTx for IF off 3. PAenable for PA off Once this state is set, the CPLD is enabled to read any inputs via the CTR bus. By level assignment (pull-down resistors and internal connections) the state is automatically achieved on start-up as long as the CPLD gates remain at logic 0 after application of supply. 14

f 0=70 M Hz B=20 M Hz f 0=70 M Hz B=20 M Hz f BB=70 M Hz f BB=70 M Hz flo 1=888 MHz REF to SYN2 f0=958 MHz B=20 M Hz f0=958 MHz B=20 M Hz REF fif=958 M Hz fif=958 M Hz fl02=3638 MHz frf=2680 M Hz frf=2680 M Hz 2 DUAL RECEIVER UNIT (DRXU) 2.1 Architecture 2.1.1 Block Diagram LO1_aux CTR PROG (int.) Vcc12 NC GND LO2_aux2 LO2_aux1 SYN2 PROG REF_in SYN1 CPLD PSU REF_out LO1 CNTR LO2 8,16 db 1,2,4,8,16 db IF on / off BB0_out BPF_BB DC2 DC900 ATT2 ATT1 SwRx AGC_Rx BPF_IF BPF_IF DC_1 Driver DC2600 LNA LNA Rx0_in 8,16 db 1,2,4,8,16 db IF on / off BB1_out DC_1 BPF_BB DC2 Driver ATT2 ATT1 SwRx BPF_IF DC900 AGC_Rx BPF_IF DC2600 LNA LNA Rx1_in Fig. 2.1-1 Simplified block diagram and mechanical structure of the dual receiver unit DRxU, for larger view see additional file/section 2.1.2 Functional Description Double conversion architecture with low IF in- and outputs to and from baseband processing Coherent dual RF transmitter or dual receiver positioned within dedicated RF enclosure, attached externally: Separate high rejection dual diplexer 2 x 2 T/R unit formed by joint mechanical attachment and coax bridges Phys. dimensions and mounting scheme similar to previous platform for seamless integration Extendable operation to 4 x 4 T/R unit by local oscillator coax bridges Selectable by synthesizer board population options: single RF channel at low phase noise, full extension band at regular phase noise Stand alone operation possible (only 2 transmitters or only 2 receivers) flexible realisation with exchangeable internal subcircuits for straightforward reconfiguration possible operation modes: FDD, FDD/TDD, TDD (after reconfig.) external reference 38 MHz supply (default) with through loop each module with individual address and controlled/monitored by serial bus system (IAF) to/from IAF-AD/DA board digital gain control, loop via baseband 15

2.1.3 Subcircuits and Components LO1: first synthesizer (SYN1, UHF range) and reference loop through CNTR: control/supply board with control IC (CPLD) and voltage regulators (PSU) LO2: second synthesizer (SYN2, C-Band), optional: switching network DC900: second downconverter (DC2) and output (low-if) bandpass filter (BPF_BB) AGC_Rx: receiver IF amplifier stages, dig. gain control (ATT1, ATT2) and IF switch (SwRx) BPF_IF: main IF filter (BPF_IF), helical filter DC2600: switched postamplifier (Driver), image filter and first downconverter to IF (DC1) LNA: first stage low noise amplifier (LNA) 16

2.2 Interface Description 2.2.1 Analogue Ports Connector type: all coaxial ports SMA (f) and 50 Ohm, DC feedthrough pins Name Description Level REF_in REF signal input approx. 1 V pp sinewave REF_out loop through REF output approx. 1 V pp sinewave BB0_out low IF output, path 0 P out =-6 dbm rms OFDM 1) BB1_out low IF output, path 1 see above Rx0_in receiver input, path 0 P in =-92...-17 dbm rms OFDM Rx1_in receiver input, path 1 P in =-92...-17 dbm rms OFDM LO1_aux auxiliary LO1 output tbd. LO2_aux1 auxiliary LO2 output tbd. LO2_aux2 auxiliary LO2 in/output tbd. Vcc12 DC supply +12 V nominal Vcc5 n/a n/a GND case ground 1) resulting from 1 Vpp ADC input (corresponding to +4 dbm sinewave into load R=50 Ohm) and -10 db backoff for OFDM modulation, input level range can be extended to -9 dbm without penalty in error performance 2.2.2 Digital Ports 2.2.2.1 Main Control Port CTR See section on DTxU. 2.2.2.2 Programming Port for CPLD (internal) See section on DTxU. 17

2.3 Specifications 2.3.1 Main Specifications of Default Configuration Parameter Value Centre frequency RF: UMTS extension band (UL: 2530 MHz) DL: 2680 MHz Tuning range: -5...+10 MHz 1) or -25...+25 MHz 2) System bandwidth: 20 MHz 3) Frequency LO1: 877.2 MHz 1) Frequency LO2: 3628 MHz 1) Centre frequency BB output: 70.8 MHz Reference frequency: 38.4 MHz Level range BB output: -6 dbm... -9 dbm rms OFDM 4) Level range RF input: -92...-17 dbm rms OFDM Receiver max. gain: 84 db 7) Gain control range: 75 db, 1 db steps Level range LO1: tbd. Level range LO2: tbd. IMD3 products at output(s): <-35 dbc typ. LNA noise figure: 1.5 db max., ª1.0 db typ. Total SSB Phase Noise: < 70 dbc/hz @ 1 khz offset 1) <-100 dbc/hz @ 10 khz offset <-120 dbc/hz @ 100 khz offset <-120 dbc/hz @ 1 MHz offset Front end attenuation: 3 db max. 5) Vector Accuracy: n/a Port impedance: 50 Ohm nom., all ports AGC_range Rx: 55 db, 1 db steps Driver amplif. switching: ª20 db step IF Switch Isolation : 45 dbc typ. Switching speed AGC : < 500ns 6) Switching speed Tx/Rx < 500ns 6) Supply voltage Vcc5: n/a Supply current to above: n/a Supply voltage Vcc12: Vcc12=+ 9.5...+14.5 V Supply current to above: I=1.5 A max. Temp.-range: T=0 50 C Supported modes: FDD, FDD/TDD 1) low phase noise setup 2) wide range setup 3) approx. -1 db points, can be changed for alternative by BPF_IF type 4) at each of DRxU outputs (BB0_out and BB1_out) 5) diplexer and cabling 6) 10%/90% RF level 7) for AGC_rx=0 db (min. attenuation in IF cascade) and Driver enabled 18

2.3.2 Absolute Maximum Ratings Parameter Supply voltage Vcc12: Supply voltage for PA Vcc5: Level RF input: Level REF input: DC level at all coax ports: Level at all control lines: Reverse BB power into DC900: Value 20 V n/a 0 dbm rms 2 V pp 6.3 V to GND 5.5 V to GND +10 dbm rms 19

2.4 Internal CPLD Control Functions In the following the internal control functions to be achieved by the CPLD circuit are specified and discussed. The activation of these functions is done by an external call via the CTR interface by means of specified data blocks (IAF). 2.4.1 IF Gain Control 2.4.1.1 Table Function Description CPLD Signal (IC pin), path ATT1_1dB Logic 0: att. on 1) I/O_4_6 (49), path 0 Logic 1: att. off I/O_4_11 (48), path 1 ATT1_2dB Logic 0: att. on I/O_4_14 (50), path 0 Logic 1: att. off I/O_4_4 (47), path 1 ATT1_4dB Logic 0: att. on I/O_4_10 (51), path 0 Logic 1: att. off I/O_4_3 (46), path 1 ATT1_8dB Logic 0: att. on I/O_4_12 (52), path 0 Logic 1: att. off I/O_4_8 (45), path 1 ATT1_16dB Logic 0: att. on I/O_4_15 (56), path 0 Logic 1: att. off I/O_4_5 (44), path 1 ATT2_8 db 2) Logic 0: att. on Logic 1: att. off ATT2_16 db Logic 0: att. on Logic 1: att. off I/O_4_17 (57), path 0 I/O_4_2 (43), path 1 I/O_2_3 (58), path 0 I/O_3_16 (42), path 1 1) All elements have pull-down resistors 10 kohm to GND (logic 0). Pull up to level +3.3V (logic 1) by means of the CPLD gate. 2) New: second attenuator has modified attenuation steps for the reason that the postamplifier stage (Driver) is also used for gain control 20

2.4.1.2 Sequence Please note that the IF attenuator switching sequence scheme has changed considerably. The reason is the extended dynamic range and the associated usage of the postamplifier (Driver) for additional gain control by RF stages. The table is shown for Rx0 but equally valid for Rx1 path. 2) Nom. P in at Relative Driver 1) ATT1 ATT2 Comment Rx0_in [dbm] att. [db] [db] [db] [db] -92 0 19 0 0 max. gain state : : : : : -85-84 7 8 19 19 7 0 0 8 Switchpoint 1 : : : : : -69-68 23 24 19 19 15 0 8 24 Switchpoint 2 : : : : : -48 44 19 20 24-47 45-2 0 24 Switchpoint 3-17 : 75 : -2 : 30 : 24 : min. nom. gain state -16 76-2 31 24 min. avail. gain state 1) Driver switching step is 20 db nominally, +18 db to -2 db insertion gain according to element data sheet. However, the switch sequence will be based on actual measured data of +19 db to -2 db. 2) Please consider approx. 2 db insertion loss for the diplexer unit and coax cables. At the backplane antenna port (ANT) the level range with thus result in P in =-90...-15 dbm. 21

2.4.2 IF Switch Control 2.4.2.1 Table Function Description CPLD Signal (IC pin), path SwRx Logic 0: IF off 1) I/O_2_4 (59), path 0 Logic 1: IF on I/O_3_12 (40), path 1 1) All elements have pull-down resistors 10 kohm to GND (logic 0). Pull up to level +3.3V (logic 1) by means of the CPLD gate. 2.4.2.2 Sequence FDD mode: ON, permanently TDD mode: operate inversely to DTxU 2.4.3 Frontend Control (Driver) 2.4.3.1 Table Function Description CPLD Signal (IC pin), path Driver_enable Logic 0: Driv. off 1) Logic 1: Driv. on I/O_2_2 (60), path 0 I/O_3_10 (39), path 1 1) All elements have pull-down resistors 10 kohm to GND (logic 0). Pull up to level +3.3V (logic 1) by means of the CPLD gate. 2.4.3.2 Sequence The postamplifier switching scheme is described in conjunction with the IF gain control in section 2.4.1. 22

2.4.4 Local Oscillator Frequency Control 2.4.4.1 Table Function Description CPLD Signal (IC pin) CLK_LO1 tbd. I/O_3_17 (38) Data_LO1 tbd. I/O_3_15 (36) LE_LO1 tbd. I/O_3_14 (35) LD_LO1 tbd. I/O_3_6 (34) CLK_LO2 tbd. I/O_1_2 (8) Data_LO2 tbd. I/O_1_5 (9) LE_LO2 tbd. I/O_1_6 (10) LD_LO2 tbd. I/O_1_8 (11) 1) All elements have pull-down resistors 10 kohm to GND (logic 0). Pull up to level +3.3V (logic 1) by means of the CPLD gate. 2.4.4.2 Sequence Programming for given frequencies according to the scheme of the ADF-4106/ADF- 4107 PLL synthesizer integrated circuit (Analog Devices). Lock detect signals to be delivered to AD/DA board via CTR interfaces for monitor and indication of LO operation. The following frequencies will be stored in the CPLD: Synthesizer Frequency [ Settings Syn1 f LO1 =877.2 MHz N=2193, P=16, B=137, A=1, for further see Annex Syn2 (centre ch.) f LO2 =3628 MHz N=36280, P=16, B=2267, A=8, for further see Annex Syn2 f LO2 =tbd. MHz (add. ch.) Syn2 (add. ch.) f LO2 =tbd. MHz Values are valid for REF=38.4 MHz. Further settings: PFD=400kHz for Syn1 PFD=100kHz for Syn2 Rset=4.7kOhm CPcurrent=5mA Fastlock=OFF Digital Lock Detect=ON 23

2.4.5 Local Oscillator Switch Control 2.4.5.1 Table Function Description CPLD Signal (IC pin) SwLO1 tbd. I/O_3_11 (33) SwLO2a tbd. I/O_1_3 (12) SwLO2b tbd. I/O_1_4 (13) 1) All elements have pull-down resistors 10 kohm to GND (logic 0). Pull up to level +3.3V (logic 1) by means of the CPLD gate. The signals will be used for switching between two PLLs within subcircuit LO2, where implemented. Not used in default configuration. 2.4.5.2 Sequence For single LO2 and fixed frequency operation set functions SwLO1 and SwLO2a permanently to logic 1. 2.4.6 Auxiliary Control Signals 2.4.6.1 Table Function Description CPLD Signal (IC pin) Aux1 tbd. I/O_2_5 (61) Aux2 tbd. I/O_2_6 (62) 1) 2.4.6.2 Sequence tbd. 2.4.7 Reset 2.4.7.1 Table Function Description CPLD Signal (IC pin) Reset Logic 0: Reset I/O_1_17 (20) Logic 1: normal 1) Pin internally pulled up to +3.3V (logic 1) by default. When button of board switch is pressed the pin is pulled down to GND (logic 0). 24

2.4.7.2 Sequence Upon manual activation when required. 2.4.8 Start-up After initial application of supply voltage Vcc12, the CPLD shall perform the following actions independent of any connected elements to the CTR interface, i.e. with or without connected CTR cable: 1. IF gain control for min. Gain 2. SwRx for IF off 3. Driver_enable for Driver_off Once this state is set, the CPLD is enabled to read any inputs via the CTR bus. By level assignment (pull-down resistors and internal connections) the state is automatically achieved on start-up as long as the CPLD gates remain at logic 0 after application of supply. 25

3 TEST SETUP 3.1 Introduction During final testing and tuning after assembly, reconfiguration and service it will be required to operate the units DTxU and DRxU in stand-alone mode, thus without connection to the AD/DA board and/or the FFP board. The following test configuration is proposed for discussion. Similar to previous setups, it is based on an external Switch Box with a data converter (parallel-toserial, CPLD) as an emulating tool. For both paths, manual switches are used to access all functions described in sections 1.4.1 1.4.6 and 2.4.1 2.4.6 except for the local oscillators frequency programming. For highest flexibility the latter is accomplished by PC test software using a direct feed through the CTR interface. For this signals, the DTxU/DRxU CPLD is merely used to retransmit bit-by-bit the received data towards the one particular synthesizer, which is selected by the LO Sel. switch. In the subsequent Switch Box version it is planned to use the Switch Box IC for programming of the synthesizers, this function will be activated by the LO Prog. selector switch. 3.2 Configuration Switch Box with Data Converter PA/Driver Path 0 PA/Driver Path 1 Test Mode SwIF SwIF 1 db 1 db 2 db 4 db...... 2 db 4 db...... parallel-to-serial conv. LO Prog. PC CPLD LO Sel. LO1 LO2 from PC parallel port Test software Analog Dev. or National Semi. Enter CLK manual switches via Switch Box CPLD to CTR direct path to CTR for progr. by PC connection for progr. by Switch Box CPLD CTR Fig. 3.2-1 DTxU or DRxU Simplified block diagram for DTxU or DRxU test setup using external Switch Box at CTR interface 26

3.3 Bus and Signals The DTxU, DRxU test mode is activated by using the Test_mode signal. For Test_mode=1 (3.3V): Test_mode=0 (0V): regular operation test mode operation are achieved. The pin is pulled up to 3.3V internally, therefore pull down externally for test mode. Once activated the modified CTR interface will read: Name Description Level / Gate (IC Pin) CTR control interface to/from AD and DA TTL 3.3V (5V tbd.) board 1) Pin 1 MODEM_IO_7 2) IO_2_8 (63) Pin 2 MODEM_IO_6 IO_2_10 (1) Pin 3 MODEM_IO_5 IO_2_12 (4) Pin 4 MODEM_IO_4 or LO select 4) IO_2_15 (6) Pin 5 CLK_LO1 or CLK_LO2 IO_2_17 (7) Pin 6 Data_LO1 or Data_LO2 IO_2_9 (64) Pin 7 LE_LO1 or LE_LO2 IO_2_11 (2) Pin 8 Test_mode 3) IO_2_14 (5) Pin 9 GND case GND 1) possible: parallel usage of this bus by DTxU and DRxU tbd. 2) design of data telegram and individual addresses of units tbd. 3) used to activate test mode with ext. switch box, upon activation signal assignment changes 4) used to directly address to which synthesizer the programming word from the PC has to be retransmitted by the CPLD, may also be included into the data telegram on pins 1-3 3.4 Sequence and Usage The usage of the external Switch Box and the associated sequence are described as follows for PC synth. programming: 1. Power-up DTxU or DRxU with connected Switch Box 2. CPLD runs start-up procedure 3. Activate test mode by manual switch 4. Set desired parallel data word by manual switch(es) for each function (frontend control, IF switch control, IF gain control, any auxiliary settings and select the synthesizer which is to be programmed by PC via bypass) 5. Press Enter Button, parallel to serial converter transmits telegram 6. Use PC synthesizer programming software to program selected LO 7. After achieved phase lock change LO_select for other synthesizer 8. Press Enter Button, parallel to serial converter transmits telegram 9. Use PC synthesizer programming software to program new LO 10. Proceed according to test requirements 27

3.5 External Switch Box Signals The table summarizes the signal-to-pin assignment for the CPLD circuit used within the external switch box. Name Level / Gate (IC Pin) TTL 3.3V Reset IO_3_11 (33) Aux IO_3_6 (34) FE_ON (both paths) IO_3_14 (35) Sw_IF (both paths) IO_3_15 (36) LO_select IO_3_17 (38) LO_prog IO_3_10 (39) ATT2_16dB path 0 IO_3_12 (40) ATT2_16dB path 1 IO_3_16 (42) ATT2_8dB path 0 IO_4_2 (43) ATT2_8dB path 1 IO_4_5 (44) ATT1_16dB path 0 IO_4_8 (45) ATT1_16dB path 1 IO_4_3 (46) ATT1_8dB path 0 IO_4_4 (47) ATT1_8dB path 1 IO_4_11 (48) ATT1_4dB path 0 IO_4_6 (49) ATT1_4dB path 1 IO_4_14 (50) ATT1_2dB path 0 IO_4_10 (51) ATT1_2dB path 1 IO_4_12 (52) ATT1_1dB path 0 IO_4_15 (56) ATT1_1dB path 1 IO_4_17 (57) Test_mode IO_2_3 (58) ENTER (transmit) IO_2_15 (6) Status IO_2_17 (7) via buffer to LED CLK IO_1_14 (17) Enable_CLK IO_1_10 (18) PC_CLK IO_1_12 (23) PC_Data IO_3_2 (22) PC_LE IO_1_17 (20) PC_Aux IO_1_15 (19) all Vcc TCK, TMS, TDI, TDO GND as required by data sheet as required by data sheet as required by data sheet 28

4 ANNEX Summary of Register Settings for Synthesizers Syn1, DTxU, f=821.2 MHz Syn2, DTxU, f=3422 MHz 29

Syn1, DRxU, f=877.2 MHz Syn2, DRxU, f=3628 MHz 30