HVM TP : A Time Predictable and Portable Java Virtual Machine for Hard Real-Time Embedded Systems JTRES 2014



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: A Time Predictable and Portable Java Virtual Machine for Hard Real-Time Embedded Systems JTRES 2014 Kasper Søe Luckow 1 Bent Thomsen 1 Stephan Erbs Korsholm 2 1 Department of Computer Science Aalborg University Denmark 2 VIA University College Horsens Denmark

Motivation 2 WCET analysis necessitates that the temporal behavior of the execution environment can be analysed Java Optimized Processor 1 Hardware Java Virtual Machine Execution times of the Java Bytecodes can be predicted This work addresses: Software Java Virtual Machine (Commodity) embedded hardware 1 http://www.jopdesign.com/

Contributions 3 Time-predictable, software Java Virtual Machine Temporal behavior of Java Bytecodes can be modeled and analysed HVMTP Accompanying tool support TETASARTSJVM TETASARTSTS

at a Glance SCJ Application Icecap SDK HW Interface HVM HVM-SCJ VM Interface 4 Interrupts I/O... HW CPU Clock Memory Based on the Hardware near Virtual Machine (HVM) 2 Java-to-C compiler ICECAP-TOOLS Supports (iterative) interpretation Ahead-Of-Time compilation Tailors and optimises HVM for the hosted program Requirements: 256 kb flash and 20 kb RAM Self-contained (runs on bare metal), ANSI C ARM, AVR, x86, cr16c,... 2 http://icelab.dk/

Time-Predictability of Time-predictability is possible by Harnessing the SCJ programming model implements SCJ Level 1 Harnessing information obtained statically (ICECAP-TOOLS) This work focuses on the iterative interpreter (constant time stages) Many Java Bytecodes from HVM are time-predictable Re-design comprises Object allocation Exceptions Method invocation Type checking of reference types... and a few others 5

Object Allocation HVM performs zeroing at allocation time Linear time operation In the heap structure is zeroed at Safelet initialisation Zeroing happens when scoped memory is exited Performed in Java space using native variables Variables in the HVM accessible in Java space 6

Exceptions SCJ permits exception objects to be pre-allocated before entering a time critical phase ICECAP-TOOLS approximates the set of exceptions that can be thrown E.g. athrow and idiv Exception handler is located in the call stack (linear time) Maximum call stack depth is estimated by ICECAP-TOOLS Reconstructs call graph Recursion is not allowed 7

Method Invocation 1 case INVOKEVIRTUAL_OPCODE : { 2 const MethodInfo * minfo ; 3 signed short excep ; 4 minfo = findmethodinfo (&sp [ top ], & method_code [ pc ] ) ; 5 excep = methodinterpreter(minfo, &sp[top]); 6 / /... 7 } Listing 1 : Original invokevirtual. 1 case INVOKEVIRTUAL_OPCODE : { 2 / /... 3 unsigned short pc = method_code ( unsigned char * ) pgm_read_pointer (&method >code, unsigned char * * ) ; 4 fp = pushstackframe(minfo, method, pc, fp, sp); 5 method = minfo ; 6 / /... 7 } Listing 2 : Using stack frames. The HVM employed recursion Difficult to analyse and model implements a call stack attempts to devirtualise call sites (using VTA) Method dispatch at virtual call sites (invokevirtual and invokeinterface) Treated (almost) equally for simplicity Consult method tables of objectref s class and superclasses Bounded by maximum height of class hierarchy (Obvious) future work: generate dispatch table (invokevirtual) 8

Type Checking Reference Types 9 The HVM iteratively consults objectref s class and superclasses exploits availability of the class hierarchy at construction time A bit matrix is constructed with entries denoting the type compatibility of (x,y)

Tool Support 10 for : TETASARTSJVM TETASARTSTS

1 case I2L_OPCODE : { 2 # i f defined (INSTRUMENT) 3 BEGIN_JBC ( I2L_OP ) ; 4 #endif 5 int32 lsb = * ( sp ) ; 6 i f ( lsb < 0) { 7 * sp++ = 1; 8 } else { 9 * sp++ = 0x0 ; 10 } 11 * sp++ = lsb ; 12 method_code ++; 13 # i f defined (INSTRUMENT) 14 END_JBC ( I2L_OP ) ; 15 #endif 16 } ldd_33 fetch! asm_inst = asm_ldd and_34 fetch! asm_inst = asm_and brge_35 fetch! fetch! asm_inst = asm_brge asm_inst = asm_brge movw_91 movw_36 fetch! fetch! asm_inst = asm_movw asm_inst = asm_movw subi_92 subi_37 fetch! fetch! asm_inst = asm_subi asm_inst = asm_subi sbci_93 sbci_38 11 Listing 3 : i2l. Generates a JVM Timing Model Figure : Excerpt of TA for i2l. Timed Automata (TA) (UPPAAL 3 model checker) Executable is instrumented Loop bounds provided comment-style All bounds are provided by ICECAP-TOOLS Reconstructs Control-Flow Graph and translates to TA 3 http://www.uppaal.org

Cont d 12 Figure : Fetch and execute TA from METAMOC 4. Composition with HW TA yields the JVM Timing Model Verification of properties (TCTL) E.g. estimate execution times of the Java Bytecodes 4 http://metamoc.dk/

generates a timing scheme from the JVM Timing Model A timing scheme captures an abstract timing model of the execution environment [BCETi,WCET i ] for instruction i 13

The Big Picture TetaSARTS TS Analysis Result 14 JVM Src TetaSARTS JVM JVM Timing Model (BCET and WCET) TetaSARTS analyser JVM Executable (AVR/ ARM/...) JVM Timing Model (Network of Timed Automata) SCJ Application Schedulability... WCET WCRT Blocking Time

Constructing complete JVM Timing Model: 16s Generating a timing scheme for all Java Bytecodes: 4.5hours (without exception handling) 5days (with exception handling) Application-dependent Java Bytecodes: Only these must be re-analysed if the program is modified 13 (without exception handling) 47 (with exception handling) In reality, only a subset of the Java Bytecodes are used The Minepump uses 49 distinct Bytecodes 5s (JVM Timing Model) and 6m (timing scheme) Only two Java Bytecodes are application-dependent (invokevirtual and invokeinterface) 15

Cont d Bytecode Measured BCET WCET Avg Low High i2l 129 136 130 130 130 aload_* 79 79 79 79 79 new 469 15 1568 1568 1568 ireturn 505 1080 893 865 976 invokespecial 501 977 710 639 772 iinc 191 194 192 192 192 16 Times are represented in clock cycles. Simulation on Atmel AVR Measurements obtained from Atmel Studio 6 Safety: BCET Low and High WCET

Further improve E.g. invokevirtual Improve precision of JVM Timing Model CFG contains both feasible and infeasible execution paths Symbolic execution Evaluate analysis approach on other (and more complex) hardware models