CM6500UN (1MHz PFC) GENERAL DESCRIPTION. EPA/90+ ZVS-Like PFC CONTROLLER. Design for High Efficient Power Supply at both Full Load and Light Load

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1 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER GENERAL DESCRIPTION CM6500UN is a ZVSLike Single PFC and it is designed to meet EPA 90 spec (total efficiency) It has the following key features ) Around % efficiency gain when the output load is below 60% of the full load ) High Voltage 40V bulk capacitor can be reduced, and also PFC Boost Capacitor ripple current can be reduced ) Turbo Speed PFC may reduce 40 Bulk Capacitor size further 4) A PGB function is designed for interfacing to next stage controller or the House Keeping IC at secondary side The PGB function pull low was decide by IC inside The PGB Pull high It has a customer programmable by PGTHL low threshold 5) Remember it was Light Load function and Remember it was Full Load function may reduce PFC 40V Bulk Capacitor size further It boosts the total efficiency as well 6) IAC, Vrms, pin resistor can be use > 5M ohm It will help No Load Consumption to reduce at 70VAC 7) Better Power Factor and Better THD 8) Clean Digital PFC Brown Out 9) Dynamic Soft PFC to ease the stress over the entire external power device is reduced and EMI noise reduced 0) Superior Surge Noise Immunity FEATURES Patents Pending V BiCMOS process Designed for EPA/90efficiency Customer Programmable the Low Threshold of PGB comparator at PGTHL pin Remember It was Light Load function to improve the efficiency and Hold up Time Remember It was Full Load function to improve the efficiency and Hold up Time Clean Digital PFC Brown Out All high voltage resistors can be greater than 5 Mega ohm (5 Mega to 8 Mega ohm) to improve the no load consumption Rail to rail CMOS Drivers with on, 4 ohm and off, ohm with 7V zeners Fast StartUP Circuit without extra bleed resistor to aid reaches V sooner Low startup current (50uA typ) Low operating current (ma typ) Adjustable Long Delay Time for Line Sagging (Up to Second) 7V shunt regulator Dynamic Soft PFC to ease the stress of the Power Device and Ease the EMIfilter design Better Power Factor and Better THD Average current mode control, continuous or discontinuous boost leading edge PFC Current fed Gain Modulator for improved noise immunity Gain Modulator is a constant maximum power limiter Precision Current Limit, overvoltage protection, UVLO, and soft start, and Reference OK CM6500UN is designed to meet the EPA/90 regulation With the proper design, its efficiency of power supply can easily approach 90/9 05//0 Rev 0 Champion Microelectronic Corporation

2 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER APPLICATIONS PIN CONFIGURATION EPA/90 related Power Supply Desktop PC Power Supply SOP4 & DIP4 TOP View Internet Server Power Supply LCD Power Supply IEAO VEAO 4 PDP Power Supply AC Adaptor IPC Power Supply IAC ISENSE UPS Battery Charger DC Motor Power Supply 4 VRMS 5 ISS PFCOUT 0 Monitor Power Supply 6 PGTHL PGB 9 Telecom System Power Supply Distributed Power 7 RTCT GND 8 PIN DESCRIPTION Pin No Symbol Description Operating Voltage Min Typ Max Unit I EAO I AC PFC transconductance current error amplifier output (GMi) IAC has functions: PFC gain modulator reference input Typical RAC resistor is about 6 Mega ohm to 8 Mega ohm to sense the line 0 V 0 00 ua I SENSE 4 V RMS PFC Current Sense: for both Gain Modulator and PFC current ILIMIT comparator Line Input Sense pin for multiplier and also it is the PFC Brown out sense pin 07 V 0 6 V 5 ISS )PFC Soft Start pin: It supplies ~ 0uA to SS pin It provides a closeloop soft start function during power supply start up PFC Soft Start function can adjust by a simple capacitor to ground and it can be around uf )When AC turn off voltage sense is lower than PGTHL(PGB comparator), SS pin is discharged through an internal ~ 70K Ohm resistor 0 V 05//0 Rev 0 Champion Microelectronic Corporation

3 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER 6 PGTHL PGTHL is an input I/O The user can program the Low Threshold of the Power Good which can determine the comparator output of PGB (open drain) to be pulled high 0 V 7 RTCT Oscillator timing node; timing set by RT and CT 08 4 V 8 GND Ground PGB is the PG comparator output The input of PG comparator is using Vfb (pin ) to compare with the high threshold 5V (preset internally) and the low threshold 9 PGB comparator with PGTHL (pin 6, Set up by user) When Bulk Voltage 80V is ready, pin 9 is opendrain and it will be pulled low When Bulk Voltage Drop (=PGTHL) set up point it will be pulled high 0 V 0 PFC OUT PFC driver output 0 V V CC Positive supply for CM6500UN Note : Vcc must keep 5V(UVLO high) or above for the sufficient turn on voltage V Maximum 5mA buffered output for the internal 75V reference when =4V 75 V V FB PFC transconductance voltage error amplifier input 0 5 V 4 VEAO PFC transconductance voltage error amplifier output (GMv) 0 6 V 05//0 Rev 0 Champion Microelectronic Corporation

4 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER SIMPLIFIED BLOCK DIAGRAM (CM6500UN) Bulk VEAO 4 GMv 75V REFEREE 6 PGTHL (PGB turn off set point) PGTHL 70V Shunt 9 PGB Kohm 5V V 55V RV (Voltage) 48V RV (Voltage) When Veao > 5V (RV)(full load) When Veao < 0V(RV)(light load) PGTHL50mV AC High Line Vrms 5V Vrms Vrms > AC High Line V SS 5V PGB PULL LOW Vrms 4 Vrms Control PGB PFC Brown Out Vrms > Brown In then PGB Pull Low 0V RAMP 7 78V Blanking RTCT Dynamic Soft Vrms < 0V Brown out Vrms > 78V Brown In IAC Adjustable Sagging Delay PFC AC Detect SS Discharge current ua RTCT PFC PFCCLK= RTCT Frequency 75V 6V PFC OVP PFC TriFault 04V PFC ILIMIT 5V ISENSE Green PFC 04V VEAO 80VOK V S Q R Q S Q R Q 4 Ohm ON Ohm OFF PFC OUT 0 7V ZENER IAC VEAO SUPPORT 0V 05V UVLO Vrms ISENSE 5 80V OK Charge Current 0uA SS Gain Modulator Imul Adjustable Sagging Delay 70K Rmul GMi ok SW OFF PGB low SW OFF Rmul PFC CMP 80V OK Adjustable Sagging Delay = SS 0uA 5V X Css ua(typ) Discharge ua Sagging Delay 5V Discharge by 70K T GND 8 REFOKB PGB IEAO 05//0 Rev 0 Champion Microelectronic Corporation 4

5 ORDERING INFORMATION CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER Part Number Temperature Range Package CM6500UNXIS* 40 to 5 4Pin SOP (S4) CM6500UNXISTR* 40 to 5 4Pin SOP (S4) CM6500UNXIP* 40 to 5 4Pin PDIP (P4) *Note: X : Suffix for Halogen Free and PB Free Product TR : Package is Tape & Reel ABSOLUTE MAXIMUM RATINGS Absolute Maximum ratings are those values beyond which the device could be permanently damaged Parameter Min Max Units V CC V GND 0 8 V (transient/load regulation) overshoot (period less than ms) 85 V (transient/load regulation) overshoot (period less than 00us) 0 V IEAO/VEAO/Vrms/RTCT/PGTHL GND 0 0 V IAC/PGB/SS GND 0 07 V GND 0 5 V I SENSE Voltage 5 07 V I SENSE Voltage (period less than ms) 0 07 V PFC OUT GND 0 0 V PFC Out Driver (period less than 50ns) GND 0 0 V PFC Out Driver (period less than 5ns) GND 50 0 V Peak PFC OUT Current, Source or Sink 05 A Peak PFC OUT Current, Source or Sink (period less than 5us) A PFC OUT, Energy Per Cycle 5 μ J I REF 5 ma I AC Input Current ma Junction Temperature 50 Storage Temperature Range Operating Temperature Range 40 5 Lead Temperature (Soldering, 0 sec) 60 Thermal Resistance (θ JA ) Plastic PDIP Plastic SOP Case Temperature (θ JC ) Plastic PDIP Plastic SOP /W /W /W /W 05//0 Rev 0 Champion Microelectronic Corporation 5

6 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply Vcc=4V, PGTHL=0V, R T = 7kΩ, C T = 000pF, T A =Operating Temperature Range (Note ) Symbol Parameter Test Conditions CM6500UN Min Typ Max Unit Clean Digital PFC Brown in/out VRMS Threshold High Room Temperature= V VRMS Threshold Low Room Temperature= V Hysteresis mv Voltage Error Amplifier (GMv) VEAO Input Voltage Range 0 6 V Transconductance V NONINV = V INV, VEAO = T= μ mho (high) Feedback Reference Voltage Vrms > AC High Line Threshold Full load Veao > 5V and Vrms < AC high Line Threshold V Light/Full Load determine (Veao Threshold) Output High Voltage V Output Low Voltage 0 04 V Source Current Overdrive Voltage = T=5 5 μ A Sink Current Overdrive Voltage = T= μ A Open Loop Gain DC gain 0 40 db Power Supply Rejection Ratio V < V CC < 65V db Current Error Amplifier (GMi) IEAO Transconductance V NONINV = V INV, IEAO = T= μ mho Input Offset Voltage VEAO=0V, IAC is open mv Output High Voltage V Output Low Voltage 0 04 V 05//0 Rev 0 Champion Microelectronic Corporation 6

7 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specifications apply Vcc=4V, PGTHL=0V, R T = 7kΩ, C T = 000pF, T A =Operating Temperature Range (Note ) Symbol Parameter Test Conditions CM6500UN Min Typ Max Unit Sink Current I SENSE = 05V, IEAO = 5V μ A Source Current I SENSE = 05V, IEAO = 40V μ A Open Loop Gain DC Gain 0 40 db Power Supply Rejection Ratio V < V CC < 65V db PFC OVP Comparator Threshold Voltage V Hysteresis mv PFC Green Power Detect Comparator TriFault Detect Veao Threshold Voltage V Fault Detect HIGH V Time to Fault Detect HIGH V FB =V FAULT DETECT LOW to V FB =OPEN, 470pF from V FB to GND 4 ms Fault Detect LOW V PFC I LIMIT Comparator(PFC current limit) Threshold Voltage V (PFCI LIMIT Gain Modulator Output) mv Delay to Output (Note 4) 700 ns PGTHL(set up PGB pull high;turn off point) PGB_CMP_LOW Sweep than check PGB CMP pull low PGB_CMP_HIGH Remember (Full Load) (Light Load) Hysteresis Setup Vref 分壓, PGTHL=V, VEAO=V Sweep Voltage Check PGB CMP PullHigh V mv 05//0 Rev 0 Champion Microelectronic Corporation 7

8 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply Vcc=4V, PGTHL=0V, R T = 7kΩ, C T = 000pF, T A =Operating Temperature Range (Note ) Symbol Parameter Test Conditions CM6500UN Min Typ Max Unit GAIN Modulator Gain (Note ) Gain (Note ) Gain (Note ) Gain4 (Note ) I AC = 0μ A, V RMS =5, V FB = T=5 I AC = 0 μ A, V RMS = 45588V, V FB = T=5 I AC = 0μ A, V RMS =9V, V FB = T=5 I AC = 0μ A, V RMS = 44V, V FB = T= Bandwidth (Note 4) I AC = 40μ A MHz Output Voltage = Rmul * (I SENSE I OFFSET ) I AC = 50μ A, V RMS = 5V, V FB = 75V VEAO=6V V I(V)mul Threshold (low) VEAO=V V Oscillator (Measuring fpfc) Initial fpfc Accuracy R T = 7 kω, C T = 000pF, T A = 5 IAC=0uA khz Voltage Stability V < V CC < 65V % Temperature Stability % Ramp Valley to Peak Voltage VEAO=6V and IAC=0uA 5 V PFC Dead Time (Note 4) ns CT Discharge Current V RAMP = 0V, V RAMP = 5V 9 0 ma 05//0 Rev 0 Champion Microelectronic Corporation 8

9 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply Vcc=4V, PGTHL=0V, R T = 7kΩ, C T = 000pF, T A =Operating Temperature Range (Note ) Symbol Parameter Test Conditions Reference CM6500UN Min Typ Max Unit Output Voltage T A = 5, I() = 0mA V Line Regulation V < V CC < T=5 8 mv Load Regulation =05V,0mA < I() < T=5 =4V,0mA < I() < 5mA; T A = 40 ~ mv 5 50 mv Temperature Stability 04 % Total Variation Line, Load, Temp 7 77 V Long Term Stability T J = 5, 000HRs 5 5 mv PFC Minimum Duty Cycle V IEAO > 45V 0 % Maximum Duty Cycle V IEAO < V 9 95 % I OUT = T=5 8 ohm Output Low Rdson I OUT = T=5 8 ohm I OUT = 0mA, V CC = T=5 05 V Output High Rdson I OUT = T= ohm I OUT = T=5 40 ohm Rise/Fall Time (Note 4) C L = T=5 50 ns Soft Start Soft Start Current Room Temperature=5 7 0 μ A Soft Start Discharge Current Vrms=brown out, Soft Start= to 5V 5 μ A Supply StartUp Current V CC = V, C L = T= ua Operating Current 4V, C L = ma TurnOn Under voltage Lockout Threshold CM6500UN 05 5 V TurnOff Under voltage Lockout Hysteresis CM6500UN V Shunt Regulator ( zener) Zener Threshold Voltage Apply with Iop=0mA V Note : Limits are guaranteed by 00% testing, sampling, or correlation with worstcase test conditions Note : Includes all bias currents to other circuits connected to the V FB pin Note : Gain ~ K x 5V; K = (I SENSE I OFFSET ) x [I AC (VEAO 07)] ; VEAO MAX = 6V Note 4: Guaranteed by design, not 00% production test 05//0 Rev 0 Champion Microelectronic Corporation 9

10 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER Getting Start Power Factor Correction To start evaluating CM6500UN from the exiting CM650, need to be taken care before doing the fine tune: ) Change RTCT pin (pin 7) from the existing value to RT=7K ohm and CT=000pF to have fpfc = frtct = 68Khz for CM6500UN ) Adjust all high voltage resistor around 5 mega ohm or higher first ) VRMS pin (pin 4) needs to be V at VIN=80Vac right before PFC brown out and to be 78V at VIN=85VAC right before PFC brown in for universal input application for line input from 85VAC to 70VAC 5) At full load, the average Veao needs to be around 4V and the ripple on the Veao needs to be less than 00mV when the light load comparator are triggered Functional Description CM6500UN is designed for high efficient power supply for both full load and light load It is a ZVSLike PFC supply controller The CM6500UN is an average current controlled, continuous/discontinuous boost Power Factor Correction (PFC) which uses leading edge modulation In addition to power factor correction, a number of protection features have been built into the CM6500UN These include softstart, PFC overvoltage protection, peak current limiting, brownout protection, duty cycle limiting, and undervoltage lockout Power factor correction makes a nonlinear load look like a resistive load to the AC line For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one) A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line The peakcharging effect, which occurs on the input filter capacitor in these supplies, causes brief highamplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage Such supplies present a power factor to the line of less than one (ie they cause significant current harmonics of the power line frequency to appear at their input) If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage The PFC section of the CM6500UN uses a boostmode DCDC converter to accomplish this The input to the converter is the full wave rectified AC line voltage No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input line voltage One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage A commonly used value is 85VDC, to allow for a high line of 70VAC rms The other condition is that the current drawn from the line at any given instant must be proportional to the line voltage Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver satisfies the first of these requirements The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage In order to prevent ripple, which will necessarily appear at the output of boost circuit (typically about 0VAC on a 85V DC level); from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low A final refinement is to adjust the overall gain of the PFC such to be proportional to /(Vin x Vin), which linearizes the transfer function of the system as the AC input to voltage varies Since the boost converter topology in the CM6500UN PFC is of the currentaveraging type, no slope compensation is required More exactly, the output current of the gain modulator is given by: 05//0 Rev 0 Champion Microelectronic Corporation 0

11 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER Dynamic Soft PFC (patent pending) Dynamic Soft PFC is the main feature of CM6500UN Dynamic Soft PFC is to improve the efficiency, to reduce power device stress, to ease EMI, and to ease the monotonic output design while it has the more protection such as the short circuit with powerfoldback protection Its unique sequential control maximizes the performance and the protections among steady state, transient and the power on/off conditions PFC Section: Gain Modulator Figure shows a block diagram of the PFC section of the CM6500UN The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltages There are three inputs to the gain modulator These are: A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at I AC Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments The gain modulator responds linearly to this current A voltage proportional to the longterm RMS AC line voltage, derived from the rectified line voltage after scaling and filtering This signal is presented to the gain modulator at VRMS The gain modulator s output is inversely proportional to V RMS The relationship between V RMS and gain is illustrated in the Typical Performance Characteristics of this page The output of the voltage error amplifier, VEAO The gain modulator responds linearly to variations in this voltage The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency This current is applied to the virtualground (negative) input of the current error amplifier In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line The general formula of the output of the gain modulator is: I mul = I AC (VEAO RMS V 07V) x constant () Gain=Imul/Iac K=Gain/(VEAO07V) I mul = K x (VEAO 07V) x I AC Where K is in units of [V ] Note that the output current of the gain modulator is limited around 40μ A and the maximum output voltage of the gain modulator is limited to 40uA x 57K=08V This 08V also will determine the maximum input power However, I GAINMOD cannot be measured directly from I SENSE I SENSE = I GAINMOD I OFFSET and I OFFSET can only be measured when VEAO is less than 05V and I GAINMOD is 0A Typical I OFFSET is around 5uA IAC=0uA, VEAO=6V Gain vs VRMS (pin4) When VRMS below V, the PFC is shut off Designer needs to design 80VAC with VRMS average voltage= 4V Gain = SENSE I I Selecting R AC for IAC pin I AC OFFSET = I I MUL IAC pin is the input of the gain modulator IAC also is a current mirror input and it requires current input By selecting a proper resistor R AC, it will provide a good sine wave current derived from the line voltage and it also helps program the maximum input power and minimum input line voltage R AC =Vin min peak x 50K For example, if the minimum line voltage is 85VAC, the R AC =85 x 44 x 50K = 60 Mega ohm AC 05//0 Rev 0 Champion Microelectronic Corporation

12 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER VRMS Description VRMS pin is designed for the following functions: VRMS is used to detect the AC Brown Out (Also, we can call it Clean Digital PFC brown out) When VRMS is less than 0 V /5%, PFCOUT will be turned off and VEAO will be softly discharged When VRMS is greater than 78V /5%, PFCOUT is enabled and VEAO is released Current Error Amplifier, IEAO The current error amplifier s output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the I SENSE pin The negative voltage on I SENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier In higher power applications, two current transformers are sometimes used, one to monitor the IF of the boost diode As stated above, the inverting input of the current error amplifier is a virtual ground Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on I SENSE is adequately negative to cancel this increased current Similarly, if the gain modulator s output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the I SENSE pin Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current This response dictates the proper compensation of the two transconductance error amplifiers Figure shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points The current loop compensation is returned to V REF to produce a softstart characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on I EAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter Clean Digital PFC Brown Out Clean Digital PFC Brown Out provides a clean cut off when AC input is much lower than regular AC input voltage such as 67Vac Inside of Clean Digital PFC Brown Out, there is a comparator monitors the VRMS (pin 4) voltage Clean Digital PFC Brown Out inhibits the PFC and VEAO (PFC error amplifier output) is pulled down when the VRMS is lower than off threshold, 04V (The off Vin voltage usually corresponds to 70Vac) When the VRMS voltage reaches 75V (The On Vin voltage usually corresponds to 866V and when Vin = 80Vac, VRMS = 4V), PFC is on Before PFC is turned on, VRMS (pin 4) represents the peak voltage of the AC input Before PFC is turned off, VRMS (pin 4) represents the VRMS voltage of the AC input CycleByCycle Current Limiter and Selecting R SENSE The I SENSE pin, as well as being a part of the current feedback loop, is a direct input to the cyclebycycle current limiter for the PFC section Should the input voltage at this pin ever be more negative than V, the output of the PFC will be disabled until the protection flipflop is reset by the clock pulse at the start of the next PFC power cycle R S is the sensing resistor of the PFC boost converter During the steady state, line input current x R SENSE = I mul x 57K Since the maximum output voltage of the gain modulator is I mul max x 57K= 08V during the steady state, R SENSE x line input current will be limited below 08V as well When VEAO reaches maximum VEAO which is 6V, Isense can reach 08V At 00% load, VEAO should be around 45V and ISENSE average peak is 06V It will provide the optimal dynamic response tolerance of the components Therefore, to choose R SENSE, we use the following equation: R SENSE R Parasitic =06V x Vinpeak / ( x Line Input power) For example, if the minimum input voltage is 80VAC, and the maximum input rms power is 00Watt, R SENSE R Parasitic = (06V x 80V x 44) / ( x 00) = 069 ohm The designer needs to consider the parasitic resistance and the margin of the power supply and dynamic response Assume R Parasitic = 0 mohm, R SENSE = 9 mohm PFC OVP In the CM6500UN, PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change A resistor divider from the high voltage DC output of the PFC is fed to When the voltage on exceeds 79V, the PFC output driver is shut down The PWM section will continue to operate The OVP comparator has 50mV of hysteresis, and the PFC will not restart until the voltage at drops below 54V The power components and the CM6500UN are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop 05//0 Rev 0 Champion Microelectronic Corporation

13 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER PFC Voltage Loop There are two major concerns when compensating the voltage loop error amplifier, V EAO ; stability and transient response Optimizing interaction between transient response and stability requires that the error amplifier s openloop crossover frequency should be / that of the line frequency, or Hz for a 47Hz line (lowest anticipated international power frequency) deviate from its 5V (nominal) value If this happens, the transconductance of the voltage error amplifier, GMv will increase significantly, as shown in the Typical Performance Characteristics This raises the gainbandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristics The Voltage Loop Gain (S) ΔV = ΔV V OUT EAO OUTDC Δ ΔV * * ΔVOUT Δ PIN * 5V * ΔVEAO * S * C EAO DC * GM V * Z Z CV : Compensation Net Work for the Voltage Loop GMv: Transconductance of VEAO P IN : Average PFC Input Power V OUTDC : PFC Boost Output Voltage; typical designed value is 80V C DC : PFC Boost Output Capacitor PFC Current Loop The current transcondutance amplifier, GMi, I EAO compensation is similar to that of the voltage error amplifier, V EAO with exception of the choice of crossover frequency The crossover frequency of the current amplifier should be at least 0 times that of the voltage amplifier, to prevent interaction with the voltage loop It should also be limited to less than /6th that of the switching frequency, eg 8kHz for a 50kHz switching frequency CV The Current Loop Gain (S) ΔVISENSE ΔDOFF ΔI = * * ΔDOFF ΔIEAO ΔI VOUTDC * RS * GMI * ZCI S * L * 5V EAO SENSE Z CI : Compensation Net Work for the Current Loop GM I : Transconductance of IEAO V OUTDC : PFC Boost Output Voltage; typical designed value is 80V and we use the worst condition to calculate the Z CI R SENSE : The Sensing Resistor of the Boost Converter 5V: The Amplitude of the PFC Leading Edge Modulation Ramp(typical) L: The Boost Inductor The gain vs input voltage of the CM6500UN s voltage error amplifier, V EAO has a specially shaped nonlinearity such that under steadystate operating conditions the transconductance of the error amplifier, GMv is at a local minimum Rapid perturbation in line or load conditions will cause the input to the voltage error amplifier (V FB ) to I SENSE Filter, the RC filter between R SENSE and I SENSE : There are purposes to add a filter at I SENSE pin: ) Protection: During start up or inrush current conditions, it will have a large voltage cross Rs which is the sensing resistor of the PFC boost converter It requires the I SENSE Filter to attenuate the energy ) To reduce L, the Boost Inductor: The I SENSE Filter To reduce L, the Boost Inductor: The I SENSE Filter also can reduce the Boost Inductor value since the I SENSE Filter behaves like an integrator before going I SENSE which is the input of the current error amplifier, IEAO The I SENSE Filter is a RC filter The resistor value of the I SENSE Filter is 50 ohm because I OFFSET x the resistor can generate an offset voltage of IEAO By selecting R FILTER equal to 50ohm will keep the offset of the IEAO less than 0mV Usually, we design the pole of I SENSE Filter at fpfc/6~fpfc=8khz, one sixth of the PFC switching frequency Therefore, the boost inductor can be reduced 6 times without disturbing the stability Therefore, the capacitor of the I SENSE Filter, C FILTER, will be around 8nF 05//0 Rev 0 Champion Microelectronic Corporation

14 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER Bulk VEAO 4 GMv 75V REFEREE 6 PGTHL (PGB turn off set point) PGTHL 70V Shunt 9 PGB Kohm 5V V 55V RV (Voltage) 48V RV (Voltage) When Veao > 5V (RV)(full load) When Veao < 0V(RV)(light load) PGTHL50mV AC High Line Vrms 5V Vrms Vrms > AC High Line V SS 5V PGB PULL LOW Vrms 4 Vrms Control PGB PFC Brown Out Vrms > Brown In then PGB Pull Low 0V RAMP 7 78V Blanking RTCT Dynamic Soft Vrms < 0V Brown out Vrms > 78V Brown In IAC Adjustable Sagging Delay PFC AC Detect SS Discharge current ua RTCT PFC PFCCLK= RTCT Frequency 75V 6V PFC OVP PFC TriFault 04V PFC ILIMIT 5V ISENSE Green PFC 04V VEAO 80VOK V S Q R Q S Q R Q 4 Ohm ON PFC OUT 0 Ohm OFF 7V ZENER IAC VEAO SUPPORT 0V 05V UVLO Vrms ISENSE 5 80V OK Charge Current 0uA SS Gain Modulator Imul Adjustable Sagging Delay 70K Rmul GMi ok SW OFF PGB low SW OFF Rmul PFC CMP 80V OK Adjustable Sagging Delay = SS 0uA 5V X Css ua(typ) Discharge ua Sagging Delay 5V Discharge by 70K T GND 8 REFOKB PGB IEAO Figure PFC Section Block Diagram 05//0 Rev 0 Champion Microelectronic Corporation 4

15 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER Oscillator (RAMP, or called RTCT) In CM6500UN, frtct = fpfc frtct =68Khz, when VEAO=0V, it provides the best performance in the PC application The oscillator frequency, frtct is the similar formula in CM6800: frtct = tramp tdeadtime The dead time of the oscillator is derived from the following equation: t RAMP = C T x R T x In Soft Start (ISS) There is a ~ 0uA to charge ISS pin The PFCsoftstart function is implemented with ISS pin After PFC Brown Out condition is removed (Vrms is greater than 75V), ISS potential will be raised by the 0uA charge current ISS potential also determines the threshold until ISS is greater than 5V Therefore, before ISS reaching 5V, PFC bulk output voltage is determined by ISS potential until ISS reaching 5V at = 75V: t RAMP = C T x R T x The dead time of the oscillator may be determined using: t DEADTIME = 9V x C T = 9 x C T 00mA The dead time is so small (t RAMP >> t DEADTIME ) that the operating frequency can typically be approximately by: frtct = tramp Ct should be greater than 470pF Let us use 000PF Solving for R T yields 7K Selecting standard components values, C T = 000pF, and R T = 7kΩ The dead time of the oscillator determined PFC minimum off time which is the dead time 05//0 Rev 0 Champion Microelectronic Corporation 5

16 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER Generating V CC After turning on CM6500UN at V, the operating voltage can vary from 0V to V That s the two ways to generate One way is to use auxiliary power supply around 5V, and the other way is to use bootstrap winding to selfbias CM6500UN system The bootstrap winding can be either taped from PFC boost choke or from the transformer of the DC to DC stage The ratio of winding transformer for the bootstrap should be set between 8V and 5V A filter network is recommended between (pin ) and bootstrap winding The resistor of the filter can be set as following R FILTER x I ~ V, I = I OP (Q PFCFET Q PWMFET ) x fsw I OP = ma (typ) If anything goes wrong, and goes beyond 94V, the PFC gate (pin 0) drive goes low remains function The resistor s value must be chosen to meet the operating current requirement of the CM6500UN itself (5mA, max) plus the current required by the two gate driver outputs EXAMPLE: With a wanting voltage called, V BIAS,of 8V, a of 5V and the CM6500UN driving a total gate charge of 90nC at 00kHz (eg IRF840 MOSFET and IRF80 MOSFET), the gate driver current required is: I GATEDRIVE = 00kHz x 90nC = 9mA R BIAS = R BIAS = VBIAS ICC IG 8V 5V 5mA 9mA In case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON The effective dutycycle of the leading edge modulation is determined during OFF time of the switch Figure 5 shows a leading edge control scheme One of the advantages of this control technique is that it required only one system clock Switch (SW) turns off and switch (SW) turns on at the same instant to minimize the momentary noload period, thus lowering ripple voltage generated by the switching action With such synchronized switching, the ripple voltage of the first stage is reduced Calculation and evaluation have shown that the 0Hz component of the PFC s output ripple voltage can be reduced by as much as 0% using this method Choose R BIAS = 4Ω The CM6500UN should be locally bypassed with a 0μ F ceramic capacitor In most applications, an electrolytic capacitor of between 47 μ F and 0 μ F is also required across the part, both for filtering and as part of the startup bootstrap circuitry Leading/Trailing Modulation Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock The error amplifier output is then compared with the modulating ramp up The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch Figure 4 shows a typical trailing edge control scheme 05//0 Rev 0 Champion Microelectronic Corporation 6

17 4 4 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER TYPICAL APPLCATION CIRCUIT PFC L H5 T F 50V 6A HSB TR8*0*0 T TR8*0*0 BD D0XB60 (0A/600V) N H4 FR 90K /W C5 0pF/KV C6 0pF/KV C 0uF 75V C 0uF 75V t RT 5Ω/5A 4 BC uf/450v (High inrush current resister) R 0 RL 85NLABC 9V 4 Q6 P C69 D ZD6 R9 80VDC C6 047uF M R 4K D0 N448 R6 47 R6 M R5 R M M % Vref/ R7 50K U C R00 P D8 C9 C0 CM6500/0 Family C 0K 047uF 000pF 00pF 4 R4 N448 n IEAO VEAO R5 Q M R D9 0K N M % R0 0K R9 R N448 IAC 0 C80 C 0047UF 47pF ISENSE 4 Vrms Vref/ C7 0uF P C70 uf/5v C0 0pF 80VDC R4 K % Q N907 L4 CS D4 SCS40P D6 N5406 R0 K (A/600V) D7 HFA08TB60 (8A/600V) Q 0N60C (0A/600V) C9 0uF/450V Vref/ R 65K R 7K C5 0uF C7 047uF R 698K % R8 7K C 000pF 5 0 SS PFC OUT 6 9 PGTHL PGB 7 8 RAMP GND PGB R9 R 0 C P R 0 PGIB/ C8 000pF Standby D EFM0 (A/50V) Q8 N VS 80VDC R4 W(S) C76 00uF/400V GND GND GND D BP 4 8 GND EN ZD P6KE50A 5% D BYV6E R48 5K C0 C4 00uF/5V R45 M R46 M D SF4 85TS 4 TS T EE9 4mH 6 8TS 8 D5 R49 N (A/000V) C8 00uF/5V 7 8TS C 000pF/50V 5 D4 SB000 R47 0 R44 47KΩ ZD ZMM(5V) C 470UF/5V C5 0uF/5V VDD R95 47KΩ 5TS L DR6*8 C 00UF/6V Q7 N700 PCA LTV87 ZD R96 47KΩ C75 047uF ZD9 ZMM(V) V ON/OFF VSB A C9 47uF/5V U TNY77P C7 0UF/50V V D0 VSB R54 0 C8 0uF/50V ZD5 HZ5 450~50V C68 M/50V Y ON/OFF 4 PCA 87C CN CON R94 56K C4 C6 R56 50 R5 K C40 0UF/5V IC KA4AZ R58 0K R55 0K % R59 54K % PCB LTV87 R50 75K R9 Q9 N ZD4 N4745A 5~68V P 05//0 Rev 0 Champion Microelectronic Corporation 7

18 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER DCDC 80VDC D6 N448 DRVH DRVL DRVHGND R60 0Ω R6 47KΩ D7 N448 R6 0Ω R65 47KΩ Q FCPN60 Q4 FCPN60 C5 C4 VSYNDRVL R6 Lp(7mH) 47KΩ PQ0 L Q 60uh/PQ5 C4 T4 IR F804PBF nF/800V TS 7TS 9 VSYNDRVH 0 TS Q5 IR F804PBF R64 47KΩ 7 TS D8 EFM04 (A/00V) C54 0uF R98 0KΩ C49 0uF C5 680uF/5V C45 470uF/6V VIS L 0nH/0A C46 C47 00uF/5V V 00uF/6V 00uF/6V R9 0 C48 C50 0uF JP V C5 0uF IPLIMIT OUT D9 BAV99 R66 56 C56 uf/50v C55 05pF R IPLIMIT D0 BAV99 SLS Controller Vref/ PGB PGB From CM6500/0 Family R40 5K PGI VS 4 R0 8K PCA 87B R4 0K ZD5 N448 SD R0 00K Q8 N700 V D SCS40P REMOTEOFF/FPOB VS C57 47uF/5V VS Q6 N C58 uf/50v VS Q7 N907 T5 EE9 5 6 DRVH DRVHGND C pF C6 R84 5K V R7 K R R78 K C6 uf/6v R4 C79 C7 C59 7 8K nf 4 DRVL Q0 N 8 R7 6K % R75 65KΩ R85 6KΩ R80 R deao KΩ M R77 0KΩ R deao M C64 47pF SD IPLIMIT U CM690 Family Rset FEAO D_IN D_IN DEAO CSS PRIDRV PRIDRVB SRDRV SRDRVB GND 8 9 Ilim RT/CT R88 R87 KΩ C65 7KΩ uf/5v R79 56KΩ C66 000pF VS VS C67 0uF/5V VS Q N Q N907 VS Q4 N Q5 N907 Q N907 R76 Ω D6 SCS40P R89 Ω D7 SCS40P VSYNDRVH VSYNDRVL 05//0 Rev 0 Champion Microelectronic Corporation 8

19 PACKAGE DIMENSION CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER 4PIN SOP (S4) 4PIN PDIP (P4) 05//0 Rev 0 Champion Microelectronic Corporation 9

20 CM6500UN (MHz PFC) EPA/90 ZVSLike PFC CONTROLLER IMPORTANT NOTICE Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current A few applications using integrated circuit products may involve potential risks of death, personal injury, or severe property or environmental damage CMC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in lifesupport applications, devices or systems or other critical applications Use of CMC products in such applications is understood to be fully at the risk of the customer In order to minimize risks associated with the customer s applications, the customer should provide adequate design and operating safeguards HsinChu Headquarter Sales & Marketing 5F, No, Park Avenue II, ScienceBased Industrial Park, HsinChu City, Taiwan F, No 96, Sec, Sintai 5th Rd, Sijhih City, Taipei County 0, Taiwan, ROC T E L : T E L : FAX: F A X : //0 Rev 0 Champion Microelectronic Corporation 0

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